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c351e290 MJ |
1 | /* |
2 | * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | #include "am33xx.dtsi" | |
11 | ||
12 | / { | |
13 | model = "Newflow AM335x NanoBone"; | |
14 | compatible = "ti,am33xx"; | |
15 | ||
16 | cpus { | |
17 | cpu@0 { | |
18 | cpu0-supply = <&dcdc2_reg>; | |
19 | }; | |
20 | }; | |
21 | ||
22 | memory { | |
23 | device_type = "memory"; | |
24 | reg = <0x80000000 0x10000000>; /* 256 MB */ | |
25 | }; | |
26 | ||
27 | leds { | |
28 | compatible = "gpio-leds"; | |
29 | ||
30 | led@0 { | |
31 | label = "nanobone:green:usr1"; | |
32 | gpios = <&gpio1 5 0>; | |
33 | default-state = "off"; | |
34 | }; | |
35 | }; | |
36 | }; | |
37 | ||
38 | &am33xx_pinmux { | |
39 | pinctrl-names = "default"; | |
40 | pinctrl-0 = <&misc_pins>; | |
41 | ||
42 | misc_pins: misc_pins { | |
43 | pinctrl-single,pins = < | |
44 | 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */ | |
45 | >; | |
46 | }; | |
47 | ||
48 | gpmc_pins: gpmc_pins { | |
49 | pinctrl-single,pins = < | |
50 | 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | |
51 | 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
52 | 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
53 | 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
54 | 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
55 | 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
56 | 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
57 | 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
58 | 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ | |
59 | 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ | |
60 | 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ | |
61 | 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ | |
62 | 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ | |
63 | 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ | |
64 | 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ | |
65 | 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ | |
66 | ||
67 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
68 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
69 | 0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */ | |
70 | 0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */ | |
71 | 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */ | |
72 | ||
73 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
74 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
75 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
76 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */ | |
77 | ||
78 | 0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */ | |
79 | 0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */ | |
80 | 0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */ | |
81 | 0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */ | |
82 | 0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */ | |
83 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */ | |
84 | 0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */ | |
85 | ||
86 | 0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */ | |
87 | 0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */ | |
88 | 0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */ | |
89 | >; | |
90 | }; | |
91 | ||
92 | i2c0_pins: i2c0_pins { | |
93 | pinctrl-single,pins = < | |
94 | 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
95 | 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
96 | >; | |
97 | }; | |
98 | ||
99 | uart0_pins: uart0_pins { | |
100 | pinctrl-single,pins = < | |
101 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | |
102 | 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
103 | >; | |
104 | }; | |
105 | ||
106 | uart1_pins: uart1_pins { | |
107 | pinctrl-single,pins = < | |
108 | 0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ | |
109 | 0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ | |
110 | 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ | |
111 | 0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ | |
112 | >; | |
113 | }; | |
114 | ||
115 | uart2_pins: uart2_pins { | |
116 | pinctrl-single,pins = < | |
117 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */ | |
118 | 0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */ | |
119 | 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ | |
120 | 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ | |
121 | >; | |
122 | }; | |
123 | ||
124 | uart3_pins: uart3_pins { | |
125 | pinctrl-single,pins = < | |
126 | 0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */ | |
127 | 0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */ | |
128 | 0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */ | |
129 | 0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ | |
130 | >; | |
131 | }; | |
132 | ||
133 | uart4_pins: uart4_pins { | |
134 | pinctrl-single,pins = < | |
135 | 0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */ | |
136 | 0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */ | |
137 | 0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */ | |
138 | 0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */ | |
139 | >; | |
140 | }; | |
141 | ||
142 | uart5_pins: uart5_pins { | |
143 | pinctrl-single,pins = < | |
144 | 0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */ | |
145 | 0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */ | |
146 | >; | |
147 | }; | |
148 | ||
149 | mmc1_pins: mmc1_pins { | |
150 | pinctrl-single,pins = < | |
151 | 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | |
152 | 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | |
153 | 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | |
154 | 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ | |
155 | 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | |
156 | 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | |
157 | 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ | |
158 | 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ | |
159 | >; | |
160 | }; | |
161 | }; | |
162 | ||
163 | &uart0 { | |
164 | pinctrl-names = "default"; | |
165 | pinctrl-0 = <&uart0_pins>; | |
166 | status = "okay"; | |
167 | }; | |
168 | ||
169 | &uart1 { | |
170 | pinctrl-names = "default"; | |
171 | pinctrl-0 = <&uart1_pins>; | |
172 | status = "okay"; | |
173 | rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; | |
174 | rs485-rts-active-high; | |
175 | rs485-rx-during-tx; | |
176 | rs485-rts-delay = <1 1>; | |
177 | linux,rs485-enabled-at-boot-time; | |
178 | }; | |
179 | ||
180 | &uart2 { | |
181 | pinctrl-names = "default"; | |
182 | pinctrl-0 = <&uart2_pins>; | |
183 | status = "okay"; | |
184 | rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; | |
185 | rs485-rts-active-high; | |
186 | rs485-rts-delay = <1 1>; | |
187 | linux,rs485-enabled-at-boot-time; | |
188 | }; | |
189 | ||
190 | &uart3 { | |
191 | pinctrl-names = "default"; | |
192 | pinctrl-0 = <&uart3_pins>; | |
193 | status = "okay"; | |
194 | }; | |
195 | ||
196 | &uart4 { | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&uart4_pins>; | |
199 | status = "okay"; | |
200 | }; | |
201 | ||
202 | &uart5 { | |
203 | pinctrl-names = "default"; | |
204 | pinctrl-0 = <&uart5_pins>; | |
205 | status = "okay"; | |
206 | }; | |
207 | ||
208 | &i2c0 { | |
209 | status = "okay"; | |
210 | pinctrl-names = "default"; | |
211 | clock-frequency = <400000>; | |
212 | pinctrl-names = "default"; | |
213 | pinctrl-0 = <&i2c0_pins>; | |
214 | ||
215 | gpio@20 { | |
10709c08 MJ |
216 | compatible = "microchip,mcp23017"; |
217 | gpio-controller; | |
218 | #gpio-cells = <2>; | |
c351e290 MJ |
219 | reg = <0x20>; |
220 | }; | |
221 | ||
222 | tps: tps@24 { | |
223 | reg = <0x24>; | |
224 | }; | |
225 | ||
226 | eeprom@53 { | |
10709c08 | 227 | compatible = "microchip,24c02"; |
c351e290 MJ |
228 | reg = <0x53>; |
229 | pagesize = <8>; | |
230 | }; | |
231 | ||
232 | rtc@68 { | |
233 | compatible = "dallas,ds1307"; | |
234 | reg = <0x68>; | |
235 | }; | |
236 | }; | |
237 | ||
238 | &elm { | |
239 | status = "okay"; | |
240 | }; | |
241 | ||
242 | &gpmc { | |
243 | compatible = "ti,am3352-gpmc"; | |
244 | ti,hwmods = "gpmc"; | |
245 | status = "okay"; | |
246 | gpmc,num-waitpins = <2>; | |
247 | pinctrl-names = "default"; | |
248 | pinctrl-0 = <&gpmc_pins>; | |
249 | ||
250 | #address-cells = <2>; | |
251 | #size-cells = <1>; | |
252 | ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */ | |
253 | ||
254 | nor@0,0 { | |
255 | reg = <0 0x00000000 0x08000000>; | |
256 | compatible = "cfi-flash"; | |
257 | linux,mtd-name = "spansion,s29gl010p11t"; | |
258 | bank-width = <2>; | |
259 | ||
260 | gpmc,mux-add-data = <2>; | |
261 | ||
262 | gpmc,sync-clk-ps = <0>; | |
263 | gpmc,cs-on-ns = <0>; | |
264 | gpmc,cs-rd-off-ns = <160>; | |
265 | gpmc,cs-wr-off-ns = <160>; | |
266 | gpmc,adv-on-ns = <10>; | |
267 | gpmc,adv-rd-off-ns = <30>; | |
268 | gpmc,adv-wr-off-ns = <30>; | |
269 | gpmc,oe-on-ns = <40>; | |
270 | gpmc,oe-off-ns = <160>; | |
271 | gpmc,we-on-ns = <40>; | |
272 | gpmc,we-off-ns = <160>; | |
273 | gpmc,rd-cycle-ns = <160>; | |
274 | gpmc,wr-cycle-ns = <160>; | |
275 | gpmc,access-ns = <150>; | |
276 | gpmc,page-burst-access-ns = <10>; | |
277 | gpmc,cycle2cycle-samecsen; | |
278 | gpmc,cycle2cycle-delay-ns = <20>; | |
279 | gpmc,wr-data-mux-bus-ns = <70>; | |
280 | gpmc,wr-access-ns = <80>; | |
281 | ||
282 | #address-cells = <1>; | |
283 | #size-cells = <1>; | |
284 | ||
285 | /* | |
286 | MTD partition table | |
287 | =================== | |
288 | +------------+-->0x00000000-> U-Boot start | |
289 | | | | |
290 | | |-->0x000BFFFF-> U-Boot end | |
291 | | |-->0x000C0000-> ENV1 start | |
292 | | | | |
293 | | |-->0x000DFFFF-> ENV1 end | |
294 | | |-->0x000E0000-> ENV2 start | |
295 | | | | |
296 | | |-->0x000FFFFF-> ENV2 end | |
297 | | |-->0x00100000-> Kernel start | |
298 | | | | |
299 | | |-->0x004FFFFF-> Kernel end | |
300 | | |-->0x00500000-> File system start | |
301 | | | | |
10709c08 MJ |
302 | | |-->0x01FFFFFF-> File system end |
303 | | |-->0x02000000-> User data start | |
c351e290 MJ |
304 | | | |
305 | | |-->0x03FFFFFF-> User data end | |
306 | | |-->0x04000000-> Data storage start | |
307 | | | | |
308 | +------------+-->0x08000000-> NOR end (Free end) | |
309 | */ | |
310 | partition@0 { | |
311 | label = "boot"; | |
312 | reg = <0x00000000 0x000c0000>; /* 768KB */ | |
313 | }; | |
314 | ||
315 | partition@1 { | |
316 | label = "env1"; | |
317 | reg = <0x000c0000 0x00020000>; /* 128KB */ | |
318 | }; | |
319 | ||
320 | partition@2 { | |
321 | label = "env2"; | |
322 | reg = <0x000e0000 0x00020000>; /* 128KB */ | |
323 | }; | |
324 | ||
325 | partition@3 { | |
326 | label = "kernel"; | |
327 | reg = <0x00100000 0x00400000>; /* 4MB */ | |
328 | }; | |
329 | ||
330 | partition@4 { | |
331 | label = "rootfs"; | |
10709c08 | 332 | reg = <0x00500000 0x01b00000>; /* 27MB */ |
c351e290 MJ |
333 | }; |
334 | ||
335 | partition@5 { | |
336 | label = "user"; | |
10709c08 | 337 | reg = <0x02000000 0x02000000>; /* 32MB */ |
c351e290 MJ |
338 | }; |
339 | ||
340 | partition@6 { | |
341 | label = "data"; | |
342 | reg = <0x04000000 0x04000000>; /* 64MB */ | |
343 | }; | |
344 | }; | |
345 | }; | |
346 | ||
347 | &mac { | |
10709c08 | 348 | dual_emac; |
16c75a13 JH |
349 | status = "okay"; |
350 | }; | |
351 | ||
352 | &davinci_mdio { | |
353 | status = "okay"; | |
c351e290 MJ |
354 | }; |
355 | ||
356 | &cpsw_emac0 { | |
357 | phy_id = <&davinci_mdio>, <0>; | |
10709c08 | 358 | phy-mode = "mii"; |
c351e290 MJ |
359 | dual_emac_res_vlan = <1>; |
360 | }; | |
361 | ||
362 | &cpsw_emac1 { | |
363 | phy_id = <&davinci_mdio>, <1>; | |
10709c08 | 364 | phy-mode = "mii"; |
c351e290 MJ |
365 | dual_emac_res_vlan = <2>; |
366 | }; | |
367 | ||
368 | &mmc1 { | |
369 | status = "okay"; | |
370 | vmmc-supply = <&ldo4_reg>; | |
371 | pinctrl-names = "default"; | |
372 | pinctrl-0 = <&mmc1_pins>; | |
373 | bus-width = <4>; | |
374 | cd-gpios = <&gpio3 8 0>; | |
375 | wp-gpios = <&gpio3 18 0>; | |
376 | }; | |
377 | ||
378 | #include "tps65217.dtsi" | |
379 | ||
380 | &tps { | |
381 | regulators { | |
382 | dcdc1_reg: regulator@0 { | |
383 | /* +1.5V voltage with ±4% tolerance */ | |
384 | regulator-min-microvolt = <1450000>; | |
385 | regulator-max-microvolt = <1550000>; | |
386 | regulator-boot-on; | |
387 | regulator-always-on; | |
388 | }; | |
389 | ||
390 | dcdc2_reg: regulator@1 { | |
391 | /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ | |
392 | regulator-name = "vdd_mpu"; | |
393 | regulator-min-microvolt = <915000>; | |
394 | regulator-max-microvolt = <1140000>; | |
395 | regulator-boot-on; | |
396 | regulator-always-on; | |
397 | }; | |
398 | ||
399 | dcdc3_reg: regulator@2 { | |
400 | /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ | |
401 | regulator-name = "vdd_core"; | |
402 | regulator-min-microvolt = <915000>; | |
403 | regulator-max-microvolt = <1140000>; | |
404 | regulator-boot-on; | |
405 | regulator-always-on; | |
406 | }; | |
407 | ||
408 | ldo1_reg: regulator@3 { | |
409 | /* +1.8V voltage with ±4% tolerance */ | |
410 | regulator-min-microvolt = <1750000>; | |
411 | regulator-max-microvolt = <1870000>; | |
412 | regulator-boot-on; | |
413 | regulator-always-on; | |
414 | }; | |
415 | ||
416 | ldo2_reg: regulator@4 { | |
417 | /* +3.3V voltage with ±4% tolerance */ | |
418 | regulator-min-microvolt = <3175000>; | |
419 | regulator-max-microvolt = <3430000>; | |
420 | regulator-boot-on; | |
421 | regulator-always-on; | |
422 | }; | |
423 | ||
424 | ldo3_reg: regulator@5 { | |
425 | /* +1.8V voltage with ±4% tolerance */ | |
426 | regulator-min-microvolt = <1750000>; | |
427 | regulator-max-microvolt = <1870000>; | |
428 | regulator-boot-on; | |
429 | regulator-always-on; | |
430 | }; | |
431 | ||
432 | ldo4_reg: regulator@6 { | |
433 | /* +3.3V voltage with ±4% tolerance */ | |
434 | regulator-min-microvolt = <3175000>; | |
435 | regulator-max-microvolt = <3430000>; | |
436 | regulator-boot-on; | |
437 | regulator-always-on; | |
438 | }; | |
439 | }; | |
440 | }; |