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Merge tag 'topic/drm-fixes-2015-07-04' of git://anongit.freedesktop.org/drm-intel
[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
7136d457 18 interrupt-parent = <&wakeupgen>;
6cfd8117
AM		 19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
9e3269b8
LV		 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
6cfd8117
AM		 28 };
29
30 cpus {
738c7409
AM		 31 #address-cells = <1>;
32 #size-cells = <0>;
08ecb28a 33 cpu: cpu@0 {
6cfd8117 34 compatible = "arm,cortex-a9";
738c7409
AM		 35 device_type = "cpu";
36 reg = <0>;
8d766fa2
NM		 37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
7136d457
MZ		 51 interrupt-parent = <&gic>;
52 };
53
54 wakeupgen: interrupt-controller@48281000 {
55 compatible = "ti,omap4-wugen-mpu";
56 interrupt-controller;
57 #interrupt-cells = <3>;
58 reg = <0x48281000 0x1000>;
59 interrupt-parent = <&gic>;
6cfd8117
AM		 60 };
61
9e3269b8
LV		 62 l2-cache-controller@48242000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x48242000 0x1000>;
65 cache-unified;
66 cache-level = <2>;
67 };
68
6cfd8117 69 ocp {
2eeddb8a 70 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
9e3269b8 74 ti,hwmods = "l3_main";
2eeddb8a
AM		 75 reg = <0x44000000 0x400000
76 0x44800000 0x400000>;
77 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 79
83a5d6c9
TK		 80 l4_wkup: l4_wkup@44c00000 {
81 compatible = "ti,am4-l4-wkup", "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges = <0 0x44c00000 0x287000>;
6a679208 85
83a5d6c9
TK		 86 prcm: prcm@1f0000 {
87 compatible = "ti,am4-prcm";
88 reg = <0x1f0000 0x11000>;
6a679208 89
83a5d6c9
TK		 90 prcm_clocks: clocks {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 };
6a679208 94
83a5d6c9
TK		 95 prcm_clockdomains: clockdomains {
96 };
6a679208
TK		 97 };
98
83a5d6c9
TK		 99 scm: scm@210000 {
100 compatible = "ti,am4-scm", "simple-bus";
101 reg = <0x210000 0x4000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x210000 0x4000>;
105
106 am43xx_pinmux: pinmux@800 {
107 compatible = "ti,am437-padconf",
108 "pinctrl-single";
109 reg = <0x800 0x31c>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <32>;
115 pinctrl-single,function-mask = <0xffffffff>;
116 };
117
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
120 reg = <0x0 0x800>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 scm_clocks: clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128 };
129
130 scm_clockdomains: clockdomains {
131 };
6a679208
TK		 132 };
133 };
134
9e3269b8
LV		 135 edma: edma@49000000 {
136 compatible = "ti,edma3";
137 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
138 reg = <0x49000000 0x10000>,
139 <0x44e10f90 0x10>;
140 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
143 #dma-cells = <1>;
9e3269b8 144 };
6cfd8117
AM		 145
146 uart0: serial@44e09000 {
147 compatible = "ti,am4372-uart","ti,omap2-uart";
148 reg = <0x44e09000 0x2000>;
149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 150 ti,hwmods = "uart1";
151 };
152
153 uart1: serial@48022000 {
154 compatible = "ti,am4372-uart","ti,omap2-uart";
155 reg = <0x48022000 0x2000>;
156 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
157 ti,hwmods = "uart2";
158 status = "disabled";
159 };
160
161 uart2: serial@48024000 {
162 compatible = "ti,am4372-uart","ti,omap2-uart";
163 reg = <0x48024000 0x2000>;
164 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
165 ti,hwmods = "uart3";
166 status = "disabled";
167 };
168
169 uart3: serial@481a6000 {
170 compatible = "ti,am4372-uart","ti,omap2-uart";
171 reg = <0x481a6000 0x2000>;
172 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
173 ti,hwmods = "uart4";
174 status = "disabled";
175 };
176
177 uart4: serial@481a8000 {
178 compatible = "ti,am4372-uart","ti,omap2-uart";
179 reg = <0x481a8000 0x2000>;
180 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
181 ti,hwmods = "uart5";
182 status = "disabled";
183 };
184
185 uart5: serial@481aa000 {
186 compatible = "ti,am4372-uart","ti,omap2-uart";
187 reg = <0x481aa000 0x2000>;
188 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
189 ti,hwmods = "uart6";
190 status = "disabled";
6cfd8117
AM		 191 };
192
9e3269b8
LV		 193 mailbox: mailbox@480C8000 {
194 compatible = "ti,omap4-mailbox";
195 reg = <0x480C8000 0x200>;
196 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
197 ti,hwmods = "mailbox";
24df0453 198 #mbox-cells = <1>;
9e3269b8
LV		 199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <8>;
d27704d1
SA		 201 mbox_wkupm3: wkup_m3 {
202 ti,mbox-tx = <0 0 0>;
203 ti,mbox-rx = <0 0 3>;
204 };
9e3269b8
LV		 205 };
206
6cfd8117
AM		 207 timer1: timer@44e31000 {
208 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
209 reg = <0x44e31000 0x400>;
210 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
211 ti,timer-alwon;
73456012 212 ti,hwmods = "timer1";
6cfd8117
AM		 213 };
214
215 timer2: timer@48040000 {
216 compatible = "ti,am4372-timer","ti,am335x-timer";
217 reg = <0x48040000 0x400>;
218 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 219 ti,hwmods = "timer2";
220 };
221
222 timer3: timer@48042000 {
223 compatible = "ti,am4372-timer","ti,am335x-timer";
224 reg = <0x48042000 0x400>;
225 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
226 ti,hwmods = "timer3";
227 status = "disabled";
228 };
229
230 timer4: timer@48044000 {
231 compatible = "ti,am4372-timer","ti,am335x-timer";
232 reg = <0x48044000 0x400>;
233 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
234 ti,timer-pwm;
235 ti,hwmods = "timer4";
236 status = "disabled";
237 };
238
239 timer5: timer@48046000 {
240 compatible = "ti,am4372-timer","ti,am335x-timer";
241 reg = <0x48046000 0x400>;
242 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
243 ti,timer-pwm;
244 ti,hwmods = "timer5";
245 status = "disabled";
246 };
247
248 timer6: timer@48048000 {
249 compatible = "ti,am4372-timer","ti,am335x-timer";
250 reg = <0x48048000 0x400>;
251 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
252 ti,timer-pwm;
253 ti,hwmods = "timer6";
254 status = "disabled";
255 };
256
257 timer7: timer@4804a000 {
258 compatible = "ti,am4372-timer","ti,am335x-timer";
259 reg = <0x4804a000 0x400>;
260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
261 ti,timer-pwm;
262 ti,hwmods = "timer7";
263 status = "disabled";
264 };
265
266 timer8: timer@481c1000 {
267 compatible = "ti,am4372-timer","ti,am335x-timer";
268 reg = <0x481c1000 0x400>;
269 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
270 ti,hwmods = "timer8";
271 status = "disabled";
272 };
273
274 timer9: timer@4833d000 {
275 compatible = "ti,am4372-timer","ti,am335x-timer";
276 reg = <0x4833d000 0x400>;
277 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
278 ti,hwmods = "timer9";
279 status = "disabled";
280 };
281
282 timer10: timer@4833f000 {
283 compatible = "ti,am4372-timer","ti,am335x-timer";
284 reg = <0x4833f000 0x400>;
285 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
286 ti,hwmods = "timer10";
287 status = "disabled";
288 };
289
290 timer11: timer@48341000 {
291 compatible = "ti,am4372-timer","ti,am335x-timer";
292 reg = <0x48341000 0x400>;
293 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
294 ti,hwmods = "timer11";
295 status = "disabled";
6cfd8117
AM		 296 };
297
298 counter32k: counter@44e86000 {
299 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
300 reg = <0x44e86000 0x40>;
73456012
AM		 301 ti,hwmods = "counter_32k";
302 };
303
08ecb28a 304 rtc: rtc@44e3e000 {
73456012
AM		 305 compatible = "ti,am4372-rtc","ti,da830-rtc";
306 reg = <0x44e3e000 0x1000>;
307 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "rtc";
310 status = "disabled";
311 };
312
08ecb28a 313 wdt: wdt@44e35000 {
73456012
AM		 314 compatible = "ti,am4372-wdt","ti,omap3-wdt";
315 reg = <0x44e35000 0x1000>;
316 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
317 ti,hwmods = "wd_timer2";
73456012
AM		 318 };
319
320 gpio0: gpio@44e07000 {
321 compatible = "ti,am4372-gpio","ti,omap4-gpio";
322 reg = <0x44e07000 0x1000>;
323 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 ti,hwmods = "gpio1";
329 status = "disabled";
330 };
331
332 gpio1: gpio@4804c000 {
333 compatible = "ti,am4372-gpio","ti,omap4-gpio";
334 reg = <0x4804c000 0x1000>;
335 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 ti,hwmods = "gpio2";
341 status = "disabled";
342 };
343
344 gpio2: gpio@481ac000 {
345 compatible = "ti,am4372-gpio","ti,omap4-gpio";
346 reg = <0x481ac000 0x1000>;
347 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 ti,hwmods = "gpio3";
353 status = "disabled";
354 };
355
356 gpio3: gpio@481ae000 {
357 compatible = "ti,am4372-gpio","ti,omap4-gpio";
358 reg = <0x481ae000 0x1000>;
359 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 ti,hwmods = "gpio4";
365 status = "disabled";
366 };
367
368 gpio4: gpio@48320000 {
369 compatible = "ti,am4372-gpio","ti,omap4-gpio";
370 reg = <0x48320000 0x1000>;
371 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 ti,hwmods = "gpio5";
377 status = "disabled";
378 };
379
380 gpio5: gpio@48322000 {
381 compatible = "ti,am4372-gpio","ti,omap4-gpio";
382 reg = <0x48322000 0x1000>;
383 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 ti,hwmods = "gpio6";
389 status = "disabled";
390 };
391
fd4a8a68
SA		 392 hwspinlock: spinlock@480ca000 {
393 compatible = "ti,omap4-hwspinlock";
394 reg = <0x480ca000 0x1000>;
395 ti,hwmods = "spinlock";
396 #hwlock-cells = <1>;
397 };
398
73456012
AM		 399 i2c0: i2c@44e0b000 {
400 compatible = "ti,am4372-i2c","ti,omap4-i2c";
401 reg = <0x44e0b000 0x1000>;
402 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
403 ti,hwmods = "i2c1";
404 #address-cells = <1>;
405 #size-cells = <0>;
406 status = "disabled";
407 };
408
409 i2c1: i2c@4802a000 {
410 compatible = "ti,am4372-i2c","ti,omap4-i2c";
411 reg = <0x4802a000 0x1000>;
412 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
413 ti,hwmods = "i2c2";
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 };
418
419 i2c2: i2c@4819c000 {
420 compatible = "ti,am4372-i2c","ti,omap4-i2c";
421 reg = <0x4819c000 0x1000>;
422 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
423 ti,hwmods = "i2c3";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 status = "disabled";
427 };
428
429 spi0: spi@48030000 {
430 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
431 reg = <0x48030000 0x400>;
432 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "spi0";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 status = "disabled";
437 };
438
9e3269b8
LV		 439 mmc1: mmc@48060000 {
440 compatible = "ti,omap4-hsmmc";
441 reg = <0x48060000 0x1000>;
442 ti,hwmods = "mmc1";
443 ti,dual-volt;
444 ti,needs-special-reset;
445 dmas = <&edma 24
446 &edma 25>;
447 dma-names = "tx", "rx";
448 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
449 status = "disabled";
450 };
451
452 mmc2: mmc@481d8000 {
453 compatible = "ti,omap4-hsmmc";
454 reg = <0x481d8000 0x1000>;
455 ti,hwmods = "mmc2";
456 ti,needs-special-reset;
457 dmas = <&edma 2
458 &edma 3>;
459 dma-names = "tx", "rx";
460 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
461 status = "disabled";
462 };
463
464 mmc3: mmc@47810000 {
465 compatible = "ti,omap4-hsmmc";
466 reg = <0x47810000 0x1000>;
467 ti,hwmods = "mmc3";
468 ti,needs-special-reset;
469 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
470 status = "disabled";
471 };
472
73456012
AM		 473 spi1: spi@481a0000 {
474 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
475 reg = <0x481a0000 0x400>;
476 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
477 ti,hwmods = "spi1";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 status = "disabled";
481 };
482
483 spi2: spi@481a2000 {
484 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
485 reg = <0x481a2000 0x400>;
486 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "spi2";
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
493 spi3: spi@481a4000 {
494 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
495 reg = <0x481a4000 0x400>;
496 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
497 ti,hwmods = "spi3";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 status = "disabled";
501 };
502
503 spi4: spi@48345000 {
504 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
505 reg = <0x48345000 0x400>;
506 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
507 ti,hwmods = "spi4";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 status = "disabled";
511 };
512
513 mac: ethernet@4a100000 {
514 compatible = "ti,am4372-cpsw","ti,cpsw";
515 reg = <0x4a100000 0x800
516 0x4a101200 0x100>;
517 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
518 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
519 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
520 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 521 #address-cells = <1>;
522 #size-cells = <1>;
73456012 523 ti,hwmods = "cpgmac0";
de21b26e
GC		 524 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
525 clock-names = "fck", "cpts";
73456012 526 status = "disabled";
9e3269b8
LV		 527 cpdma_channels = <8>;
528 ale_entries = <1024>;
529 bd_ram_size = <0x2000>;
530 no_bd_ram = <0>;
531 rx_descs = <64>;
532 mac_control = <0x20>;
533 slaves = <2>;
534 active_slave = <0>;
535 cpts_clock_mult = <0x80000000>;
536 cpts_clock_shift = <29>;
537 ranges;
538
539 davinci_mdio: mdio@4a101000 {
540 compatible = "ti,am4372-mdio","ti,davinci_mdio";
541 reg = <0x4a101000 0x100>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 ti,hwmods = "davinci_mdio";
545 bus_freq = <1000000>;
546 status = "disabled";
547 };
548
549 cpsw_emac0: slave@4a100200 {
550 /* Filled in by U-Boot */
551 mac-address = [ 00 00 00 00 00 00 ];
552 };
553
554 cpsw_emac1: slave@4a100300 {
555 /* Filled in by U-Boot */
556 mac-address = [ 00 00 00 00 00 00 ];
557 };
a9682cfb
M		 558
559 phy_sel: cpsw-phy-sel@44e10650 {
560 compatible = "ti,am43xx-cpsw-phy-sel";
561 reg= <0x44e10650 0x4>;
562 reg-names = "gmii-sel";
563 };
73456012
AM		 564 };
565
566 epwmss0: epwmss@48300000 {
567 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
568 reg = <0x48300000 0x10>;
9e3269b8
LV		 569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges;
73456012
AM		 572 ti,hwmods = "epwmss0";
573 status = "disabled";
9e3269b8
LV		 574
575 ecap0: ecap@48300100 {
576 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 577 #pwm-cells = <3>;
9e3269b8
LV		 578 reg = <0x48300100 0x80>;
579 ti,hwmods = "ecap0";
580 status = "disabled";
581 };
582
583 ehrpwm0: ehrpwm@48300200 {
584 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 585 #pwm-cells = <3>;
9e3269b8
LV		 586 reg = <0x48300200 0x80>;
587 ti,hwmods = "ehrpwm0";
588 status = "disabled";
589 };
73456012
AM		 590 };
591
592 epwmss1: epwmss@48302000 {
593 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
594 reg = <0x48302000 0x10>;
9e3269b8
LV		 595 #address-cells = <1>;
596 #size-cells = <1>;
597 ranges;
73456012
AM		 598 ti,hwmods = "epwmss1";
599 status = "disabled";
9e3269b8
LV		 600
601 ecap1: ecap@48302100 {
602 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 603 #pwm-cells = <3>;
9e3269b8
LV		 604 reg = <0x48302100 0x80>;
605 ti,hwmods = "ecap1";
606 status = "disabled";
607 };
608
609 ehrpwm1: ehrpwm@48302200 {
610 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 611 #pwm-cells = <3>;
9e3269b8
LV		 612 reg = <0x48302200 0x80>;
613 ti,hwmods = "ehrpwm1";
614 status = "disabled";
615 };
73456012
AM		 616 };
617
618 epwmss2: epwmss@48304000 {
619 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
620 reg = <0x48304000 0x10>;
9e3269b8
LV		 621 #address-cells = <1>;
622 #size-cells = <1>;
623 ranges;
73456012
AM		 624 ti,hwmods = "epwmss2";
625 status = "disabled";
9e3269b8
LV		 626
627 ecap2: ecap@48304100 {
628 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 629 #pwm-cells = <3>;
9e3269b8
LV		 630 reg = <0x48304100 0x80>;
631 ti,hwmods = "ecap2";
632 status = "disabled";
633 };
634
635 ehrpwm2: ehrpwm@48304200 {
636 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 637 #pwm-cells = <3>;
9e3269b8
LV		 638 reg = <0x48304200 0x80>;
639 ti,hwmods = "ehrpwm2";
640 status = "disabled";
641 };
73456012
AM		 642 };
643
644 epwmss3: epwmss@48306000 {
645 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
646 reg = <0x48306000 0x10>;
9e3269b8
LV		 647 #address-cells = <1>;
648 #size-cells = <1>;
649 ranges;
73456012
AM		 650 ti,hwmods = "epwmss3";
651 status = "disabled";
9e3269b8
LV		 652
653 ehrpwm3: ehrpwm@48306200 {
654 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 655 #pwm-cells = <3>;
9e3269b8
LV		 656 reg = <0x48306200 0x80>;
657 ti,hwmods = "ehrpwm3";
658 status = "disabled";
659 };
73456012
AM		 660 };
661
662 epwmss4: epwmss@48308000 {
663 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
664 reg = <0x48308000 0x10>;
9e3269b8
LV		 665 #address-cells = <1>;
666 #size-cells = <1>;
667 ranges;
73456012
AM		 668 ti,hwmods = "epwmss4";
669 status = "disabled";
9e3269b8
LV		 670
671 ehrpwm4: ehrpwm@48308200 {
672 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 673 #pwm-cells = <3>;
9e3269b8
LV		 674 reg = <0x48308200 0x80>;
675 ti,hwmods = "ehrpwm4";
676 status = "disabled";
677 };
73456012
AM		 678 };
679
680 epwmss5: epwmss@4830a000 {
681 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
682 reg = <0x4830a000 0x10>;
9e3269b8
LV		 683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges;
73456012
AM		 686 ti,hwmods = "epwmss5";
687 status = "disabled";
9e3269b8
LV		 688
689 ehrpwm5: ehrpwm@4830a200 {
690 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 691 #pwm-cells = <3>;
9e3269b8
LV		 692 reg = <0x4830a200 0x80>;
693 ti,hwmods = "ehrpwm5";
694 status = "disabled";
695 };
696 };
697
0f39f7b9
V		 698 tscadc: tscadc@44e0d000 {
699 compatible = "ti,am3359-tscadc";
700 reg = <0x44e0d000 0x1000>;
701 ti,hwmods = "adc_tsc";
702 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&adc_tsc_fck>;
704 clock-names = "fck";
705 status = "disabled";
706
707 tsc {
708 compatible = "ti,am3359-tsc";
709 };
710
711 adc {
712 #io-channel-cells = <1>;
713 compatible = "ti,am3359-adc";
714 };
715
716 };
717
9e3269b8
LV		 718 sham: sham@53100000 {
719 compatible = "ti,omap5-sham";
720 ti,hwmods = "sham";
721 reg = <0x53100000 0x300>;
722 dmas = <&edma 36>;
723 dma-names = "rx";
724 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 725 };
6e70a510
JF		 726
727 aes: aes@53501000 {
728 compatible = "ti,omap4-aes";
729 ti,hwmods = "aes";
730 reg = <0x53501000 0xa0>;
731 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 732 dmas = <&edma 6
733 &edma 5>;
734 dma-names = "tx", "rx";
6e70a510 735 };
099f3a85
JF		 736
737 des: des@53701000 {
738 compatible = "ti,omap4-des";
739 ti,hwmods = "des";
740 reg = <0x53701000 0xa0>;
741 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 742 dmas = <&edma 34
743 &edma 33>;
744 dma-names = "tx", "rx";
099f3a85 745 };
9e3269b8 746
b9c95bf4
PU		 747 mcasp0: mcasp@48038000 {
748 compatible = "ti,am33xx-mcasp-audio";
749 ti,hwmods = "mcasp0";
750 reg = <0x48038000 0x2000>,
751 <0x46000000 0x400000>;
752 reg-names = "mpu", "dat";
753 interrupts = <80>, <81>;
ae107d06 754 interrupt-names = "tx", "rx";
b9c95bf4
PU		 755 status = "disabled";
756 dmas = <&edma 8>,
757 <&edma 9>;
758 dma-names = "tx", "rx";
759 };
760
761 mcasp1: mcasp@4803C000 {
762 compatible = "ti,am33xx-mcasp-audio";
763 ti,hwmods = "mcasp1";
764 reg = <0x4803C000 0x2000>,
765 <0x46400000 0x400000>;
766 reg-names = "mpu", "dat";
767 interrupts = <82>, <83>;
ae107d06 768 interrupt-names = "tx", "rx";
b9c95bf4
PU		 769 status = "disabled";
770 dmas = <&edma 10>,
771 <&edma 11>;
772 dma-names = "tx", "rx";
773 };
f68e355c
PG		 774
775 elm: elm@48080000 {
776 compatible = "ti,am3352-elm";
777 reg = <0x48080000 0x2000>;
778 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
779 ti,hwmods = "elm";
780 clocks = <&l4ls_gclk>;
781 clock-names = "fck";
782 status = "disabled";
783 };
784
785 gpmc: gpmc@50000000 {
786 compatible = "ti,am3352-gpmc";
787 ti,hwmods = "gpmc";
788 clocks = <&l3s_gclk>;
789 clock-names = "fck";
790 reg = <0x50000000 0x2000>;
791 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
792 gpmc,num-cs = <7>;
793 gpmc,num-waitpins = <2>;
794 #address-cells = <2>;
795 #size-cells = <1>;
796 status = "disabled";
797 };
a0ae47ea
GC		 798
799 am43xx_control_usb2phy1: control-phy@44e10620 {
800 compatible = "ti,control-phy-usb2-am437";
801 reg = <0x44e10620 0x4>;
802 reg-names = "power";
803 };
804
805 am43xx_control_usb2phy2: control-phy@0x44e10628 {
806 compatible = "ti,control-phy-usb2-am437";
807 reg = <0x44e10628 0x4>;
808 reg-names = "power";
809 };
810
811 ocp2scp0: ocp2scp@483a8000 {
20431db9 812 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 813 #address-cells = <1>;
814 #size-cells = <1>;
815 ranges;
816 ti,hwmods = "ocp2scp0";
817
818 usb2_phy1: phy@483a8000 {
819 compatible = "ti,am437x-usb2";
820 reg = <0x483a8000 0x8000>;
821 ctrl-module = <&am43xx_control_usb2phy1>;
822 clocks = <&usb_phy0_always_on_clk32k>,
823 <&usb_otg_ss0_refclk960m>;
824 clock-names = "wkupclk", "refclk";
825 #phy-cells = <0>;
826 status = "disabled";
827 };
828 };
829
830 ocp2scp1: ocp2scp@483e8000 {
20431db9 831 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 832 #address-cells = <1>;
833 #size-cells = <1>;
834 ranges;
835 ti,hwmods = "ocp2scp1";
836
837 usb2_phy2: phy@483e8000 {
838 compatible = "ti,am437x-usb2";
839 reg = <0x483e8000 0x8000>;
840 ctrl-module = <&am43xx_control_usb2phy2>;
841 clocks = <&usb_phy1_always_on_clk32k>,
842 <&usb_otg_ss1_refclk960m>;
843 clock-names = "wkupclk", "refclk";
844 #phy-cells = <0>;
845 status = "disabled";
846 };
847 };
848
849 dwc3_1: omap_dwc3@48380000 {
850 compatible = "ti,am437x-dwc3";
851 ti,hwmods = "usb_otg_ss0";
852 reg = <0x48380000 0x10000>;
853 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
854 #address-cells = <1>;
855 #size-cells = <1>;
856 utmi-mode = <1>;
857 ranges;
858
859 usb1: usb@48390000 {
860 compatible = "synopsys,dwc3";
4b143f0f 861 reg = <0x48390000 0x10000>;
a0ae47ea
GC		 862 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
863 phys = <&usb2_phy1>;
864 phy-names = "usb2-phy";
865 maximum-speed = "high-speed";
866 dr_mode = "otg";
867 status = "disabled";
60f0e628
FB		 868 snps,dis_u3_susphy_quirk;
869 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 870 };
871 };
872
873 dwc3_2: omap_dwc3@483c0000 {
874 compatible = "ti,am437x-dwc3";
875 ti,hwmods = "usb_otg_ss1";
876 reg = <0x483c0000 0x10000>;
877 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
878 #address-cells = <1>;
879 #size-cells = <1>;
880 utmi-mode = <1>;
881 ranges;
882
883 usb2: usb@483d0000 {
884 compatible = "synopsys,dwc3";
4b143f0f 885 reg = <0x483d0000 0x10000>;
a0ae47ea
GC		 886 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
887 phys = <&usb2_phy2>;
888 phy-names = "usb2-phy";
889 maximum-speed = "high-speed";
890 dr_mode = "otg";
891 status = "disabled";
60f0e628
FB		 892 snps,dis_u3_susphy_quirk;
893 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 894 };
895 };
2a1a5043
SP		 896
897 qspi: qspi@47900000 {
898 compatible = "ti,am4372-qspi";
899 reg = <0x47900000 0x100>;
900 #address-cells = <1>;
901 #size-cells = <0>;
902 ti,hwmods = "qspi";
903 interrupts = <0 138 0x4>;
904 num-cs = <4>;
905 status = "disabled";
906 };
741cac5f
SP		 907
908 hdq: hdq@48347000 {
a895b8a0 909 compatible = "ti,am4372-hdq";
741cac5f
SP		 910 reg = <0x48347000 0x1000>;
911 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&func_12m_clk>;
913 clock-names = "fck";
914 ti,hwmods = "hdq1w";
915 status = "disabled";
916 };
8c793367
SP		 917
918 dss: dss@4832a000 {
919 compatible = "ti,omap3-dss";
920 reg = <0x4832a000 0x200>;
921 status = "disabled";
922 ti,hwmods = "dss_core";
923 clocks = <&disp_clk>;
924 clock-names = "fck";
925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
928
08ecb28a 929 dispc: dispc@4832a400 {
8c793367
SP		 930 compatible = "ti,omap3-dispc";
931 reg = <0x4832a400 0x400>;
932 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
933 ti,hwmods = "dss_dispc";
934 clocks = <&disp_clk>;
935 clock-names = "fck";
936 };
937
938 rfbi: rfbi@4832a800 {
939 compatible = "ti,omap3-rfbi";
940 reg = <0x4832a800 0x100>;
941 ti,hwmods = "dss_rfbi";
942 clocks = <&disp_clk>;
943 clock-names = "fck";
944 };
945 };
8b9a2810
RN		 946
947 ocmcram: ocmcram@40300000 {
948 compatible = "mmio-sram";
949 reg = <0x40300000 0x40000>; /* 256k */
950 };
9e63b0d4
RQ		 951
952 dcan0: can@481cc000 {
953 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
954 ti,hwmods = "d_can0";
955 clocks = <&dcan0_fck>;
956 clock-names = "fck";
957 reg = <0x481cc000 0x2000>;
83a5d6c9 958 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 959 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
960 status = "disabled";
961 };
962
963 dcan1: can@481d0000 {
964 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
965 ti,hwmods = "d_can1";
966 clocks = <&dcan1_fck>;
967 clock-names = "fck";
968 reg = <0x481d0000 0x2000>;
83a5d6c9 969 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 970 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
971 status = "disabled";
972 };
9d0df0a6
BP		 973
974 vpfe0: vpfe@48326000 {
975 compatible = "ti,am437x-vpfe";
976 reg = <0x48326000 0x2000>;
977 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
978 ti,hwmods = "vpfe0";
979 status = "disabled";
980 };
981
982 vpfe1: vpfe@48328000 {
983 compatible = "ti,am437x-vpfe";
984 reg = <0x48328000 0x2000>;
985 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
986 ti,hwmods = "vpfe1";
987 status = "disabled";
988 };
6cfd8117
AM		 989 };
990};
6a679208
TK		 991
992/include/ "am43xx-clocks.dtsi"
Linux kernel - Deliverables
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