[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi

/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&gic>;


	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	am43xx_pinmux: pinmux@44e10800 {
		compatible = "pinctrl-single";
		reg = <0x44e10800 0x31c>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		prcm: prcm@44df0000 {
			compatible = "ti,am4-prcm";
			reg = <0x44df0000 0x11000>;

			prcm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prcm_clockdomains: clockdomains {
			};
		};

		scrm: scrm@44e10000 {
			compatible = "ti,am4-scrm";
			reg = <0x44e10000 0x2000>;

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		edma: edma@49000000 {
			compatible = "ti,edma3";
			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
			reg =	<0x49000000 0x10000>,
				<0x44e10f90 0x10>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <64>;
			ti,edma-regions = <4>;
			ti,edma-slots = <256>;
		};

		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
		};

		mailbox: mailbox@480C8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480C8000 0x200>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <8>;
			ti,mbox-names = "wkup_m3";
			ti,mbox-data = <0 0 0 0>;
			status = "disabled";
		};

		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
			ti,hwmods = "timer1";
		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
			ti,hwmods = "counter_32k";
		};

		rtc@44e3e000 {
			compatible = "ti,am4372-rtc","ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
			status = "disabled";
		};

		wdt@44e35000 {
			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

		hwspinlock: spinlock@480ca000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x480ca000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <1>;
		};

		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x1000>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&edma 24
				&edma 25>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc2: mmc@481d8000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x481d8000 0x1000>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&edma 2
				&edma 3>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x47810000 0x1000>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "cpgmac0";
			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
			clock-names = "fck", "cpts";
			status = "disabled";
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			rx_descs = <64>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			ranges;

			davinci_mdio: mdio@4a101000 {
				compatible = "ti,am4372-mdio","ti,davinci_mdio";
				reg = <0x4a101000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				status = "disabled";
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss0";
			status = "disabled";

			ecap0: ecap@48300100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				#pwm-cells = <3>;
				reg = <0x48300100 0x80>;
				ti,hwmods = "ecap0";
				status = "disabled";
			};

			ehrpwm0: ehrpwm@48300200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x48300200 0x80>;
				ti,hwmods = "ehrpwm0";
				status = "disabled";
			};
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss1";
			status = "disabled";

			ecap1: ecap@48302100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				#pwm-cells = <3>;
				reg = <0x48302100 0x80>;
				ti,hwmods = "ecap1";
				status = "disabled";
			};

			ehrpwm1: ehrpwm@48302200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x48302200 0x80>;
				ti,hwmods = "ehrpwm1";
				status = "disabled";
			};
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss2";
			status = "disabled";

			ecap2: ecap@48304100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				#pwm-cells = <3>;
				reg = <0x48304100 0x80>;
				ti,hwmods = "ecap2";
				status = "disabled";
			};

			ehrpwm2: ehrpwm@48304200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x48304200 0x80>;
				ti,hwmods = "ehrpwm2";
				status = "disabled";
			};
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss3";
			status = "disabled";

			ehrpwm3: ehrpwm@48306200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x48306200 0x80>;
				ti,hwmods = "ehrpwm3";
				status = "disabled";
			};
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss4";
			status = "disabled";

			ehrpwm4: ehrpwm@48308200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x48308200 0x80>;
				ti,hwmods = "ehrpwm4";
				status = "disabled";
			};
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss5";
			status = "disabled";

			ehrpwm5: ehrpwm@4830a200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				#pwm-cells = <3>;
				reg = <0x4830a200 0x80>;
				ti,hwmods = "ehrpwm5";
				status = "disabled";
			};
		};

		sham: sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x53100000 0x300>;
			dmas = <&edma 36>;
			dma-names = "rx";
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
		};

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 6
				&edma 5>;
			dma-names = "tx", "rx";
		};

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 34
				&edma 33>;
			dma-names = "tx", "rx";
		};

		mcasp0: mcasp@48038000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp0";
			reg = <0x48038000 0x2000>,
			      <0x46000000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <80>, <81>;
			interrupt-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 8>,
			       <&edma 9>;
			dma-names = "tx", "rx";
		};

		mcasp1: mcasp@4803C000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x4803C000 0x2000>,
			      <0x46400000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <82>, <83>;
			interrupt-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 10>,
			       <&edma 11>;
			dma-names = "tx", "rx";
		};

		elm: elm@48080000 {
			compatible = "ti,am3352-elm";
			reg = <0x48080000 0x2000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "elm";
			clocks = <&l4ls_gclk>;
			clock-names = "fck";
			status = "disabled";
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			clocks = <&l3s_gclk>;
			clock-names = "fck";
			reg = <0x50000000 0x2000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpmc,num-cs = <7>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			status = "disabled";
		};
	};
};

/include/ "am43xx-clocks.dtsi"
Commit	Line	Data
6cfd8117 AM	1	/*
	2	* Device Tree Source for AM4372 SoC
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
d2885dbb	11	#include <dt-bindings/gpio/gpio.h>
6cfd8117 AM	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13
	14	#include "skeleton.dtsi"
	15
	16	/ {
	17	compatible = "ti,am4372", "ti,am43";
	18	interrupt-parent = <&gic>;
	19
	20
	21	aliases {
6a968678 NM	22	i2c0 = &i2c0;
	23	i2c1 = &i2c1;
	24	i2c2 = &i2c2;
6cfd8117	25	serial0 = &uart0;
9e3269b8 LV	26	ethernet0 = &cpsw_emac0;
9e3269b8 LV	27	ethernet1 = &cpsw_emac1;
6cfd8117 AM	28	};
	29
	30	cpus {
738c7409 AM	31	#address-cells = <1>;
738c7409 AM	32	#size-cells = <0>;
6cfd8117 AM	33	cpu@0 {
6cfd8117 AM	34	compatible = "arm,cortex-a9";
738c7409 AM	35	device_type = "cpu";
738c7409 AM	36	reg = <0>;
8d766fa2 NM	37
	38	clocks = <&dpll_mpu_ck>;
	39	clock-names = "cpu";
	40
	41	clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117 AM	42	};
	43	};
	44
	45	gic: interrupt-controller@48241000 {
	46	compatible = "arm,cortex-a9-gic";
	47	interrupt-controller;
	48	#interrupt-cells = <3>;
	49	reg = <0x48241000 0x1000>,
	50	<0x48240100 0x0100>;
	51	};
	52
9e3269b8 LV	53	l2-cache-controller@48242000 {
	54	compatible = "arm,pl310-cache";
	55	reg = <0x48242000 0x1000>;
	56	cache-unified;
	57	cache-level = <2>;
	58	};
	59
	60	am43xx_pinmux: pinmux@44e10800 {
	61	compatible = "pinctrl-single";
	62	reg = <0x44e10800 0x31c>;
	63	#address-cells = <1>;
	64	#size-cells = <0>;
	65	pinctrl-single,register-width = <32>;
	66	pinctrl-single,function-mask = <0xffffffff>;
	67	};
	68
6cfd8117 AM	69	ocp {
	70	compatible = "simple-bus";
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	ranges;
9e3269b8 LV	74	ti,hwmods = "l3_main";
9e3269b8 LV	75
6a679208 TK	76	prcm: prcm@44df0000 {
	77	compatible = "ti,am4-prcm";
	78	reg = <0x44df0000 0x11000>;
	79
	80	prcm_clocks: clocks {
	81	#address-cells = <1>;
	82	#size-cells = <0>;
	83	};
	84
	85	prcm_clockdomains: clockdomains {
	86	};
	87	};
	88
	89	scrm: scrm@44e10000 {
	90	compatible = "ti,am4-scrm";
	91	reg = <0x44e10000 0x2000>;
	92
	93	scrm_clocks: clocks {
	94	#address-cells = <1>;
	95	#size-cells = <0>;
	96	};
	97
	98	scrm_clockdomains: clockdomains {
	99	};
	100	};
	101
9e3269b8 LV	102	edma: edma@49000000 {
	103	compatible = "ti,edma3";
	104	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
	105	reg = <0x49000000 0x10000>,
	106	<0x44e10f90 0x10>;
	107	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	108	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	109	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	110	#dma-cells = <1>;
	111	dma-channels = <64>;
	112	ti,edma-regions = <4>;
	113	ti,edma-slots = <256>;
	114	};
6cfd8117 AM	115
	116	uart0: serial@44e09000 {
	117	compatible = "ti,am4372-uart","ti,omap2-uart";
	118	reg = <0x44e09000 0x2000>;
	119	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	120	ti,hwmods = "uart1";
	121	};
	122
	123	uart1: serial@48022000 {
	124	compatible = "ti,am4372-uart","ti,omap2-uart";
	125	reg = <0x48022000 0x2000>;
	126	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	127	ti,hwmods = "uart2";
	128	status = "disabled";
	129	};
	130
	131	uart2: serial@48024000 {
	132	compatible = "ti,am4372-uart","ti,omap2-uart";
	133	reg = <0x48024000 0x2000>;
	134	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	135	ti,hwmods = "uart3";
	136	status = "disabled";
	137	};
	138
	139	uart3: serial@481a6000 {
	140	compatible = "ti,am4372-uart","ti,omap2-uart";
	141	reg = <0x481a6000 0x2000>;
	142	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	143	ti,hwmods = "uart4";
	144	status = "disabled";
	145	};
	146
	147	uart4: serial@481a8000 {
	148	compatible = "ti,am4372-uart","ti,omap2-uart";
	149	reg = <0x481a8000 0x2000>;
	150	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	151	ti,hwmods = "uart5";
	152	status = "disabled";
	153	};
	154
	155	uart5: serial@481aa000 {
	156	compatible = "ti,am4372-uart","ti,omap2-uart";
	157	reg = <0x481aa000 0x2000>;
	158	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	159	ti,hwmods = "uart6";
	160	status = "disabled";
6cfd8117 AM	161	};
6cfd8117 AM	162
9e3269b8 LV	163	mailbox: mailbox@480C8000 {
	164	compatible = "ti,omap4-mailbox";
	165	reg = <0x480C8000 0x200>;
	166	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	167	ti,hwmods = "mailbox";
	168	ti,mbox-num-users = <4>;
	169	ti,mbox-num-fifos = <8>;
	170	ti,mbox-names = "wkup_m3";
	171	ti,mbox-data = <0 0 0 0>;
	172	status = "disabled";
	173	};
	174
6cfd8117 AM	175	timer1: timer@44e31000 {
	176	compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
	177	reg = <0x44e31000 0x400>;
	178	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	179	ti,timer-alwon;
73456012	180	ti,hwmods = "timer1";
6cfd8117 AM	181	};
	182
	183	timer2: timer@48040000 {
	184	compatible = "ti,am4372-timer","ti,am335x-timer";
	185	reg = <0x48040000 0x400>;
	186	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	187	ti,hwmods = "timer2";
	188	};
	189
	190	timer3: timer@48042000 {
	191	compatible = "ti,am4372-timer","ti,am335x-timer";
	192	reg = <0x48042000 0x400>;
	193	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	194	ti,hwmods = "timer3";
	195	status = "disabled";
	196	};
	197
	198	timer4: timer@48044000 {
	199	compatible = "ti,am4372-timer","ti,am335x-timer";
	200	reg = <0x48044000 0x400>;
	201	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	202	ti,timer-pwm;
	203	ti,hwmods = "timer4";
	204	status = "disabled";
	205	};
	206
	207	timer5: timer@48046000 {
	208	compatible = "ti,am4372-timer","ti,am335x-timer";
	209	reg = <0x48046000 0x400>;
	210	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	211	ti,timer-pwm;
	212	ti,hwmods = "timer5";
	213	status = "disabled";
	214	};
	215
	216	timer6: timer@48048000 {
	217	compatible = "ti,am4372-timer","ti,am335x-timer";
	218	reg = <0x48048000 0x400>;
	219	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	220	ti,timer-pwm;
	221	ti,hwmods = "timer6";
	222	status = "disabled";
	223	};
	224
	225	timer7: timer@4804a000 {
	226	compatible = "ti,am4372-timer","ti,am335x-timer";
	227	reg = <0x4804a000 0x400>;
	228	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	229	ti,timer-pwm;
	230	ti,hwmods = "timer7";
	231	status = "disabled";
	232	};
	233
	234	timer8: timer@481c1000 {
	235	compatible = "ti,am4372-timer","ti,am335x-timer";
	236	reg = <0x481c1000 0x400>;
	237	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	238	ti,hwmods = "timer8";
	239	status = "disabled";
	240	};
	241
	242	timer9: timer@4833d000 {
	243	compatible = "ti,am4372-timer","ti,am335x-timer";
	244	reg = <0x4833d000 0x400>;
	245	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	246	ti,hwmods = "timer9";
	247	status = "disabled";
	248	};
	249
	250	timer10: timer@4833f000 {
251	compatible = "ti,am4372-timer","ti,am335x-timer";
252	reg = <0x4833f000 0x400>;
253	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
254	ti,hwmods = "timer10";
255	status = "disabled";
256	};
257
258	timer11: timer@48341000 {
259	compatible = "ti,am4372-timer","ti,am335x-timer";
260	reg = <0x48341000 0x400>;
261	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
262	ti,hwmods = "timer11";
263	status = "disabled";
6cfd8117 AM	264	};
	265
	266	counter32k: counter@44e86000 {
	267	compatible = "ti,am4372-counter32k","ti,omap-counter32k";
	268	reg = <0x44e86000 0x40>;
73456012 AM	269	ti,hwmods = "counter_32k";
	270	};
	271
	272	rtc@44e3e000 {
	273	compatible = "ti,am4372-rtc","ti,da830-rtc";
	274	reg = <0x44e3e000 0x1000>;
	275	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
	276	GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	277	ti,hwmods = "rtc";
	278	status = "disabled";
	279	};
	280
	281	wdt@44e35000 {
	282	compatible = "ti,am4372-wdt","ti,omap3-wdt";
	283	reg = <0x44e35000 0x1000>;
	284	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	285	ti,hwmods = "wd_timer2";
73456012 AM	286	};
	287
	288	gpio0: gpio@44e07000 {
	289	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	290	reg = <0x44e07000 0x1000>;
	291	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	292	gpio-controller;
	293	#gpio-cells = <2>;
	294	interrupt-controller;
	295	#interrupt-cells = <2>;
	296	ti,hwmods = "gpio1";
	297	status = "disabled";
	298	};
	299
	300	gpio1: gpio@4804c000 {
	301	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	302	reg = <0x4804c000 0x1000>;
	303	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	304	gpio-controller;
	305	#gpio-cells = <2>;
	306	interrupt-controller;
	307	#interrupt-cells = <2>;
	308	ti,hwmods = "gpio2";
	309	status = "disabled";
	310	};
	311
	312	gpio2: gpio@481ac000 {
	313	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	314	reg = <0x481ac000 0x1000>;
	315	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	316	gpio-controller;
	317	#gpio-cells = <2>;
	318	interrupt-controller;
	319	#interrupt-cells = <2>;
	320	ti,hwmods = "gpio3";
	321	status = "disabled";
	322	};
	323
	324	gpio3: gpio@481ae000 {
	325	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	326	reg = <0x481ae000 0x1000>;
	327	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	328	gpio-controller;
	329	#gpio-cells = <2>;
	330	interrupt-controller;
	331	#interrupt-cells = <2>;
	332	ti,hwmods = "gpio4";
	333	status = "disabled";
	334	};
	335
	336	gpio4: gpio@48320000 {
	337	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	338	reg = <0x48320000 0x1000>;
	339	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	340	gpio-controller;
	341	#gpio-cells = <2>;
	342	interrupt-controller;
	343	#interrupt-cells = <2>;
	344	ti,hwmods = "gpio5";
	345	status = "disabled";
	346	};
	347
	348	gpio5: gpio@48322000 {
	349	compatible = "ti,am4372-gpio","ti,omap4-gpio";
350	reg = <0x48322000 0x1000>;
351	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
352	gpio-controller;
353	#gpio-cells = <2>;
354	interrupt-controller;
355	#interrupt-cells = <2>;
356	ti,hwmods = "gpio6";
357	status = "disabled";
358	};
359
fd4a8a68 SA	360	hwspinlock: spinlock@480ca000 {
	361	compatible = "ti,omap4-hwspinlock";
	362	reg = <0x480ca000 0x1000>;
	363	ti,hwmods = "spinlock";
	364	#hwlock-cells = <1>;
	365	};
	366
73456012 AM	367	i2c0: i2c@44e0b000 {
	368	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	369	reg = <0x44e0b000 0x1000>;
	370	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	371	ti,hwmods = "i2c1";
	372	#address-cells = <1>;
	373	#size-cells = <0>;
	374	status = "disabled";
	375	};
	376
	377	i2c1: i2c@4802a000 {
	378	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	379	reg = <0x4802a000 0x1000>;
	380	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	381	ti,hwmods = "i2c2";
	382	#address-cells = <1>;
	383	#size-cells = <0>;
	384	status = "disabled";
	385	};
	386
	387	i2c2: i2c@4819c000 {
	388	compatible = "ti,am4372-i2c","ti,omap4-i2c";
	389	reg = <0x4819c000 0x1000>;
	390	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	391	ti,hwmods = "i2c3";
	392	#address-cells = <1>;
	393	#size-cells = <0>;
	394	status = "disabled";
	395	};
	396
	397	spi0: spi@48030000 {
	398	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	399	reg = <0x48030000 0x400>;
	400	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	401	ti,hwmods = "spi0";
	402	#address-cells = <1>;
	403	#size-cells = <0>;
	404	status = "disabled";
	405	};
	406
9e3269b8 LV	407	mmc1: mmc@48060000 {
	408	compatible = "ti,omap4-hsmmc";
	409	reg = <0x48060000 0x1000>;
	410	ti,hwmods = "mmc1";
	411	ti,dual-volt;
	412	ti,needs-special-reset;
	413	dmas = <&edma 24
	414	&edma 25>;
	415	dma-names = "tx", "rx";
	416	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	417	status = "disabled";
	418	};
	419
	420	mmc2: mmc@481d8000 {
	421	compatible = "ti,omap4-hsmmc";
	422	reg = <0x481d8000 0x1000>;
	423	ti,hwmods = "mmc2";
	424	ti,needs-special-reset;
	425	dmas = <&edma 2
	426	&edma 3>;
	427	dma-names = "tx", "rx";
	428	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	429	status = "disabled";
	430	};
	431
	432	mmc3: mmc@47810000 {
	433	compatible = "ti,omap4-hsmmc";
	434	reg = <0x47810000 0x1000>;
	435	ti,hwmods = "mmc3";
	436	ti,needs-special-reset;
	437	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	438	status = "disabled";
	439	};
	440
73456012 AM	441	spi1: spi@481a0000 {
	442	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	443	reg = <0x481a0000 0x400>;
	444	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	445	ti,hwmods = "spi1";
	446	#address-cells = <1>;
	447	#size-cells = <0>;
	448	status = "disabled";
	449	};
	450
	451	spi2: spi@481a2000 {
	452	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	453	reg = <0x481a2000 0x400>;
	454	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	455	ti,hwmods = "spi2";
	456	#address-cells = <1>;
	457	#size-cells = <0>;
	458	status = "disabled";
	459	};
	460
	461	spi3: spi@481a4000 {
	462	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	463	reg = <0x481a4000 0x400>;
	464	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	465	ti,hwmods = "spi3";
	466	#address-cells = <1>;
	467	#size-cells = <0>;
	468	status = "disabled";
	469	};
	470
	471	spi4: spi@48345000 {
	472	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	473	reg = <0x48345000 0x400>;
	474	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	475	ti,hwmods = "spi4";
	476	#address-cells = <1>;
	477	#size-cells = <0>;
	478	status = "disabled";
	479	};
	480
	481	mac: ethernet@4a100000 {
	482	compatible = "ti,am4372-cpsw","ti,cpsw";
	483	reg = <0x4a100000 0x800
	484	0x4a101200 0x100>;
	485	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
	486	GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
	487	GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
	488	GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	489	#address-cells = <1>;
9e3269b8 LV	490	#size-cells = <1>;
73456012	491	ti,hwmods = "cpgmac0";
de21b26e GC	492	clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
de21b26e GC	493	clock-names = "fck", "cpts";
73456012	494	status = "disabled";
9e3269b8 LV	495	cpdma_channels = <8>;
	496	ale_entries = <1024>;
	497	bd_ram_size = <0x2000>;
	498	no_bd_ram = <0>;
	499	rx_descs = <64>;
	500	mac_control = <0x20>;
	501	slaves = <2>;
	502	active_slave = <0>;
	503	cpts_clock_mult = <0x80000000>;
	504	cpts_clock_shift = <29>;
	505	ranges;
	506
	507	davinci_mdio: mdio@4a101000 {
	508	compatible = "ti,am4372-mdio","ti,davinci_mdio";
	509	reg = <0x4a101000 0x100>;
	510	#address-cells = <1>;
	511	#size-cells = <0>;
	512	ti,hwmods = "davinci_mdio";
	513	bus_freq = <1000000>;
	514	status = "disabled";
	515	};
	516
	517	cpsw_emac0: slave@4a100200 {
	518	/* Filled in by U-Boot */
	519	mac-address = [ 00 00 00 00 00 00 ];
	520	};
	521
	522	cpsw_emac1: slave@4a100300 {
	523	/* Filled in by U-Boot */
	524	mac-address = [ 00 00 00 00 00 00 ];
	525	};
73456012 AM	526	};
	527
	528	epwmss0: epwmss@48300000 {
	529	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	530	reg = <0x48300000 0x10>;
9e3269b8 LV	531	#address-cells = <1>;
	532	#size-cells = <1>;
	533	ranges;
73456012 AM	534	ti,hwmods = "epwmss0";
73456012 AM	535	status = "disabled";
9e3269b8 LV	536
	537	ecap0: ecap@48300100 {
	538	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305	539	#pwm-cells = <3>;
9e3269b8 LV	540	reg = <0x48300100 0x80>;
	541	ti,hwmods = "ecap0";
	542	status = "disabled";
	543	};
	544
	545	ehrpwm0: ehrpwm@48300200 {
	546	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	547	#pwm-cells = <3>;
9e3269b8 LV	548	reg = <0x48300200 0x80>;
	549	ti,hwmods = "ehrpwm0";
	550	status = "disabled";
	551	};
73456012 AM	552	};
	553
	554	epwmss1: epwmss@48302000 {
	555	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	556	reg = <0x48302000 0x10>;
9e3269b8 LV	557	#address-cells = <1>;
	558	#size-cells = <1>;
	559	ranges;
73456012 AM	560	ti,hwmods = "epwmss1";
73456012 AM	561	status = "disabled";
9e3269b8 LV	562
	563	ecap1: ecap@48302100 {
	564	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305	565	#pwm-cells = <3>;
9e3269b8 LV	566	reg = <0x48302100 0x80>;
	567	ti,hwmods = "ecap1";
	568	status = "disabled";
	569	};
	570
	571	ehrpwm1: ehrpwm@48302200 {
	572	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	573	#pwm-cells = <3>;
9e3269b8 LV	574	reg = <0x48302200 0x80>;
	575	ti,hwmods = "ehrpwm1";
	576	status = "disabled";
	577	};
73456012 AM	578	};
	579
	580	epwmss2: epwmss@48304000 {
	581	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	582	reg = <0x48304000 0x10>;
9e3269b8 LV	583	#address-cells = <1>;
	584	#size-cells = <1>;
	585	ranges;
73456012 AM	586	ti,hwmods = "epwmss2";
73456012 AM	587	status = "disabled";
9e3269b8 LV	588
	589	ecap2: ecap@48304100 {
	590	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305	591	#pwm-cells = <3>;
9e3269b8 LV	592	reg = <0x48304100 0x80>;
	593	ti,hwmods = "ecap2";
	594	status = "disabled";
	595	};
	596
	597	ehrpwm2: ehrpwm@48304200 {
	598	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	599	#pwm-cells = <3>;
9e3269b8 LV	600	reg = <0x48304200 0x80>;
	601	ti,hwmods = "ehrpwm2";
	602	status = "disabled";
	603	};
73456012 AM	604	};
	605
	606	epwmss3: epwmss@48306000 {
	607	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	608	reg = <0x48306000 0x10>;
9e3269b8 LV	609	#address-cells = <1>;
	610	#size-cells = <1>;
	611	ranges;
73456012 AM	612	ti,hwmods = "epwmss3";
73456012 AM	613	status = "disabled";
9e3269b8 LV	614
	615	ehrpwm3: ehrpwm@48306200 {
	616	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	617	#pwm-cells = <3>;
9e3269b8 LV	618	reg = <0x48306200 0x80>;
	619	ti,hwmods = "ehrpwm3";
	620	status = "disabled";
	621	};
73456012 AM	622	};
	623
	624	epwmss4: epwmss@48308000 {
	625	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	626	reg = <0x48308000 0x10>;
9e3269b8 LV	627	#address-cells = <1>;
	628	#size-cells = <1>;
	629	ranges;
73456012 AM	630	ti,hwmods = "epwmss4";
73456012 AM	631	status = "disabled";
9e3269b8 LV	632
	633	ehrpwm4: ehrpwm@48308200 {
	634	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	635	#pwm-cells = <3>;
9e3269b8 LV	636	reg = <0x48308200 0x80>;
	637	ti,hwmods = "ehrpwm4";
	638	status = "disabled";
	639	};
73456012 AM	640	};
	641
	642	epwmss5: epwmss@4830a000 {
	643	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	644	reg = <0x4830a000 0x10>;
9e3269b8 LV	645	#address-cells = <1>;
	646	#size-cells = <1>;
	647	ranges;
73456012 AM	648	ti,hwmods = "epwmss5";
73456012 AM	649	status = "disabled";
9e3269b8 LV	650
	651	ehrpwm5: ehrpwm@4830a200 {
	652	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305	653	#pwm-cells = <3>;
9e3269b8 LV	654	reg = <0x4830a200 0x80>;
	655	ti,hwmods = "ehrpwm5";
	656	status = "disabled";
	657	};
	658	};
	659
	660	sham: sham@53100000 {
	661	compatible = "ti,omap5-sham";
	662	ti,hwmods = "sham";
	663	reg = <0x53100000 0x300>;
	664	dmas = <&edma 36>;
	665	dma-names = "rx";
	666	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117	667	};
6e70a510 JF	668
	669	aes: aes@53501000 {
	670	compatible = "ti,omap4-aes";
	671	ti,hwmods = "aes";
	672	reg = <0x53501000 0xa0>;
	673	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	674	dmas = <&edma 6
	675	&edma 5>;
	676	dma-names = "tx", "rx";
6e70a510	677	};
099f3a85 JF	678
	679	des: des@53701000 {
	680	compatible = "ti,omap4-des";
	681	ti,hwmods = "des";
	682	reg = <0x53701000 0xa0>;
	683	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	684	dmas = <&edma 34
	685	&edma 33>;
	686	dma-names = "tx", "rx";
099f3a85	687	};
9e3269b8	688
b9c95bf4 PU	689	mcasp0: mcasp@48038000 {
	690	compatible = "ti,am33xx-mcasp-audio";
	691	ti,hwmods = "mcasp0";
	692	reg = <0x48038000 0x2000>,
	693	<0x46000000 0x400000>;
	694	reg-names = "mpu", "dat";
	695	interrupts = <80>, <81>;
ae107d06	696	interrupt-names = "tx", "rx";
b9c95bf4 PU	697	status = "disabled";
	698	dmas = <&edma 8>,
	699	<&edma 9>;
	700	dma-names = "tx", "rx";
	701	};
	702
	703	mcasp1: mcasp@4803C000 {
	704	compatible = "ti,am33xx-mcasp-audio";
	705	ti,hwmods = "mcasp1";
	706	reg = <0x4803C000 0x2000>,
	707	<0x46400000 0x400000>;
	708	reg-names = "mpu", "dat";
	709	interrupts = <82>, <83>;
ae107d06	710	interrupt-names = "tx", "rx";
b9c95bf4 PU	711	status = "disabled";
	712	dmas = <&edma 10>,
	713	<&edma 11>;
	714	dma-names = "tx", "rx";
	715	};
f68e355c PG	716
	717	elm: elm@48080000 {
	718	compatible = "ti,am3352-elm";
	719	reg = <0x48080000 0x2000>;
	720	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	721	ti,hwmods = "elm";
	722	clocks = <&l4ls_gclk>;
	723	clock-names = "fck";
	724	status = "disabled";
	725	};
	726
	727	gpmc: gpmc@50000000 {
	728	compatible = "ti,am3352-gpmc";
	729	ti,hwmods = "gpmc";
	730	clocks = <&l3s_gclk>;
	731	clock-names = "fck";
	732	reg = <0x50000000 0x2000>;
	733	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	734	gpmc,num-cs = <7>;
	735	gpmc,num-waitpins = <2>;
	736	#address-cells = <2>;
	737	#size-cells = <1>;
	738	status = "disabled";
	739	};
6cfd8117 AM	740	};
6cfd8117 AM	741	};
6a679208 TK	742
6a679208 TK	743	/include/ "am43xx-clocks.dtsi"