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4730bcfb AM |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* AM43x EPOS EVM */ | |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | #include "am4372.dtsi" | |
e54686e4 M |
14 | #include <dt-bindings/pinctrl/am43xx.h> |
15 | #include <dt-bindings/gpio/gpio.h> | |
2e3a9385 | 16 | #include <dt-bindings/pwm/pwm.h> |
cbfc7e6f | 17 | #include <dt-bindings/sound/tlv320aic31xx-micbias.h> |
4730bcfb AM |
18 | |
19 | / { | |
20 | model = "TI AM43x EPOS EVM"; | |
21 | compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; | |
e54686e4 | 22 | |
999c3f1a TV |
23 | aliases { |
24 | display0 = &lcd0; | |
25 | }; | |
26 | ||
e54686e4 M |
27 | vmmcsd_fixed: fixedregulator-sd { |
28 | compatible = "regulator-fixed"; | |
29 | regulator-name = "vmmcsd_fixed"; | |
30 | regulator-min-microvolt = <3300000>; | |
31 | regulator-max-microvolt = <3300000>; | |
32 | enable-active-high; | |
33 | }; | |
34 | ||
7ec341d9 PU |
35 | vbat: fixedregulator@0 { |
36 | compatible = "regulator-fixed"; | |
37 | regulator-name = "vbat"; | |
38 | regulator-min-microvolt = <5000000>; | |
39 | regulator-max-microvolt = <5000000>; | |
40 | regulator-boot-on; | |
41 | }; | |
42 | ||
999c3f1a TV |
43 | lcd0: display { |
44 | compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; | |
45 | label = "lcd"; | |
46 | ||
999c3f1a TV |
47 | panel-timing { |
48 | clock-frequency = <33000000>; | |
49 | hactive = <800>; | |
50 | vactive = <480>; | |
51 | hfront-porch = <210>; | |
52 | hback-porch = <16>; | |
53 | hsync-len = <30>; | |
54 | vback-porch = <10>; | |
55 | vfront-porch = <22>; | |
56 | vsync-len = <13>; | |
57 | hsync-active = <0>; | |
58 | vsync-active = <0>; | |
59 | de-active = <1>; | |
60 | pixelclk-active = <1>; | |
61 | }; | |
62 | ||
63 | port { | |
64 | lcd_in: endpoint { | |
65 | remote-endpoint = <&dpi_out>; | |
66 | }; | |
67 | }; | |
68 | }; | |
69 | ||
d7eaf3c4 TK |
70 | matrix_keypad: matrix_keypad@0 { |
71 | compatible = "gpio-matrix-keypad"; | |
72 | debounce-delay-ms = <5>; | |
73 | col-scan-delay-us = <2>; | |
74 | ||
75 | row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ | |
76 | &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ | |
77 | &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ | |
78 | &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ | |
79 | ||
80 | col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ | |
81 | &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ | |
82 | &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ | |
83 | &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ | |
84 | ||
85 | linux,keymap = <0x00000201 /* P1 */ | |
86 | 0x01000204 /* P4 */ | |
87 | 0x02000207 /* P7 */ | |
88 | 0x0300020a /* NUMERIC_STAR */ | |
89 | 0x00010202 /* P2 */ | |
90 | 0x01010205 /* P5 */ | |
91 | 0x02010208 /* P8 */ | |
92 | 0x03010200 /* P0 */ | |
93 | 0x00020203 /* P3 */ | |
94 | 0x01020206 /* P6 */ | |
95 | 0x02020209 /* P9 */ | |
96 | 0x0302020b /* NUMERIC_POUND */ | |
97 | 0x00030067 /* UP */ | |
98 | 0x0103006a /* RIGHT */ | |
99 | 0x0203006c /* DOWN */ | |
100 | 0x03030069>; /* LEFT */ | |
101 | }; | |
102 | ||
103 | backlight { | |
104 | compatible = "pwm-backlight"; | |
105 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | |
106 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | |
107 | default-brightness-level = <8>; | |
108 | }; | |
22d7fb57 PU |
109 | |
110 | sound0: sound@0 { | |
111 | compatible = "simple-audio-card"; | |
112 | simple-audio-card,name = "AM43-EPOS-EVM"; | |
113 | simple-audio-card,widgets = | |
114 | "Microphone", "Microphone Jack", | |
115 | "Headphone", "Headphone Jack", | |
116 | "Speaker", "Speaker"; | |
117 | simple-audio-card,routing = | |
118 | "MIC1LP", "Microphone Jack", | |
119 | "MIC1RP", "Microphone Jack", | |
120 | "MIC1LP", "MICBIAS", | |
121 | "MIC1RP", "MICBIAS", | |
122 | "Headphone Jack", "HPL", | |
123 | "Headphone Jack", "HPR", | |
124 | "Speaker", "SPL", | |
125 | "Speaker", "SPR"; | |
126 | simple-audio-card,format = "dsp_b"; | |
127 | simple-audio-card,bitclock-master = <&sound0_master>; | |
128 | simple-audio-card,frame-master = <&sound0_master>; | |
129 | simple-audio-card,bitclock-inversion; | |
130 | ||
131 | simple-audio-card,cpu { | |
132 | sound-dai = <&mcasp1>; | |
133 | system-clock-frequency = <12000000>; | |
134 | }; | |
135 | ||
136 | sound0_master: simple-audio-card,codec { | |
137 | sound-dai = <&tlv320aic3111>; | |
138 | system-clock-frequency = <12000000>; | |
139 | }; | |
140 | }; | |
d7eaf3c4 TK |
141 | }; |
142 | ||
143 | &am43xx_pinmux { | |
e54686e4 M |
144 | cpsw_default: cpsw_default { |
145 | pinctrl-single,pins = < | |
146 | /* Slave 1 */ | |
147 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ | |
148 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ | |
149 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ | |
150 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ | |
151 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ | |
152 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ | |
153 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ | |
154 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ | |
155 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ | |
156 | >; | |
157 | }; | |
158 | ||
159 | cpsw_sleep: cpsw_sleep { | |
160 | pinctrl-single,pins = < | |
161 | /* Slave 1 reset value */ | |
162 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
163 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
164 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
165 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
166 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
167 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
168 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
169 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
170 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
171 | >; | |
172 | }; | |
173 | ||
174 | davinci_mdio_default: davinci_mdio_default { | |
175 | pinctrl-single,pins = < | |
176 | /* MDIO */ | |
177 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | |
178 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
179 | >; | |
180 | }; | |
181 | ||
182 | davinci_mdio_sleep: davinci_mdio_sleep { | |
183 | pinctrl-single,pins = < | |
184 | /* MDIO reset value */ | |
185 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
186 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
187 | >; | |
188 | }; | |
189 | ||
190 | i2c0_pins: pinmux_i2c0_pins { | |
191 | pinctrl-single,pins = < | |
192 | 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
193 | 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
194 | >; | |
195 | }; | |
f68e355c PG |
196 | |
197 | nand_flash_x8: nand_flash_x8 { | |
198 | pinctrl-single,pins = < | |
199 | 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ | |
200 | 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | |
201 | 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
202 | 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
203 | 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
204 | 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
205 | 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
206 | 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
207 | 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
208 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
209 | 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ | |
210 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
211 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
212 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
213 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
214 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | |
215 | >; | |
216 | }; | |
f777ba17 | 217 | |
2e3a9385 SP |
218 | ecap0_pins: backlight_pins { |
219 | pinctrl-single,pins = < | |
220 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | |
221 | >; | |
222 | }; | |
0aeaf1c6 SP |
223 | |
224 | i2c2_pins: pinmux_i2c2_pins { | |
225 | pinctrl-single,pins = < | |
226 | 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ | |
227 | 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ | |
228 | >; | |
229 | }; | |
416f3d50 SP |
230 | |
231 | spi0_pins: pinmux_spi0_pins { | |
232 | pinctrl-single,pins = < | |
233 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ | |
234 | 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ | |
235 | 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ | |
236 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | |
237 | >; | |
238 | }; | |
239 | ||
240 | spi1_pins: pinmux_spi1_pins { | |
241 | pinctrl-single,pins = < | |
242 | 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ | |
243 | 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ | |
244 | 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ | |
245 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ | |
246 | >; | |
247 | }; | |
d2885dbb B |
248 | |
249 | mmc1_pins: pinmux_mmc1_pins { | |
250 | pinctrl-single,pins = < | |
251 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | |
252 | >; | |
253 | }; | |
2a1a5043 SP |
254 | |
255 | qspi1_default: qspi1_default { | |
256 | pinctrl-single,pins = < | |
257 | 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) | |
258 | 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) | |
259 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) | |
260 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) | |
261 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) | |
262 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) | |
263 | >; | |
264 | }; | |
6cfcb5be RQ |
265 | |
266 | pixcir_ts_pins: pixcir_ts_pins { | |
267 | pinctrl-single,pins = < | |
268 | 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ | |
269 | >; | |
270 | }; | |
741cac5f SP |
271 | |
272 | hdq_pins: pinmux_hdq_pins { | |
273 | pinctrl-single,pins = < | |
274 | 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ | |
275 | >; | |
276 | }; | |
999c3f1a TV |
277 | |
278 | dss_pins: dss_pins { | |
279 | pinctrl-single,pins = < | |
280 | 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ | |
281 | 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
282 | 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
283 | 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
284 | 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
285 | 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
286 | 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
287 | 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ | |
288 | 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ | |
289 | 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
290 | 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
291 | 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
292 | 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
293 | 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
294 | 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
295 | 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
296 | 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
297 | 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
298 | 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
299 | 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
300 | 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
301 | 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
302 | 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
303 | 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ | |
304 | 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ | |
305 | 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ | |
306 | 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ | |
307 | 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ | |
308 | >; | |
309 | }; | |
310 | ||
56fd3dc7 | 311 | display_mux_pins: display_mux_pins { |
999c3f1a TV |
312 | pinctrl-single,pins = < |
313 | /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ | |
314 | 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) | |
315 | >; | |
316 | }; | |
d890edcd BP |
317 | |
318 | vpfe1_pins_default: vpfe1_pins_default { | |
319 | pinctrl-single,pins = < | |
320 | 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ | |
321 | 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ | |
322 | 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ | |
323 | 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ | |
324 | 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ | |
325 | 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ | |
326 | 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ | |
327 | 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ | |
328 | 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ | |
329 | 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ | |
330 | 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ | |
331 | 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ | |
332 | 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ | |
333 | >; | |
334 | }; | |
335 | ||
336 | vpfe1_pins_sleep: vpfe1_pins_sleep { | |
337 | pinctrl-single,pins = < | |
338 | 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
339 | 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
340 | 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
341 | 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
342 | 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
343 | 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
344 | 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
345 | 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
346 | 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
347 | 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
348 | 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
349 | 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
350 | 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
351 | >; | |
352 | }; | |
06e2bf6b PU |
353 | |
354 | mcasp1_pins: mcasp1_pins { | |
355 | pinctrl-single,pins = < | |
356 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ | |
357 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ | |
358 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ | |
359 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ | |
360 | >; | |
361 | }; | |
362 | ||
363 | mcasp1_sleep_pins: mcasp1_sleep_pins { | |
364 | pinctrl-single,pins = < | |
365 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
366 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
367 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
368 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
369 | >; | |
370 | }; | |
e54686e4 M |
371 | }; |
372 | ||
373 | &mmc1 { | |
374 | status = "okay"; | |
375 | vmmc-supply = <&vmmcsd_fixed>; | |
376 | bus-width = <4>; | |
d2885dbb B |
377 | pinctrl-names = "default"; |
378 | pinctrl-0 = <&mmc1_pins>; | |
0731cbdd | 379 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
e54686e4 M |
380 | }; |
381 | ||
382 | &mac { | |
383 | pinctrl-names = "default", "sleep"; | |
384 | pinctrl-0 = <&cpsw_default>; | |
385 | pinctrl-1 = <&cpsw_sleep>; | |
386 | status = "okay"; | |
387 | }; | |
388 | ||
389 | &davinci_mdio { | |
390 | pinctrl-names = "default", "sleep"; | |
391 | pinctrl-0 = <&davinci_mdio_default>; | |
392 | pinctrl-1 = <&davinci_mdio_sleep>; | |
393 | status = "okay"; | |
394 | }; | |
395 | ||
396 | &cpsw_emac0 { | |
397 | phy_id = <&davinci_mdio>, <16>; | |
398 | phy-mode = "rmii"; | |
399 | }; | |
400 | ||
401 | &cpsw_emac1 { | |
402 | phy_id = <&davinci_mdio>, <1>; | |
403 | phy-mode = "rmii"; | |
404 | }; | |
405 | ||
fe797553 GC |
406 | &phy_sel { |
407 | rmii-clock-ext; | |
408 | }; | |
409 | ||
e54686e4 M |
410 | &i2c0 { |
411 | status = "okay"; | |
412 | pinctrl-names = "default"; | |
413 | pinctrl-0 = <&i2c0_pins>; | |
497d64a3 K |
414 | clock-frequency = <400000>; |
415 | ||
416 | tps65218: tps65218@24 { | |
417 | reg = <0x24>; | |
418 | compatible = "ti,tps65218"; | |
419 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ | |
497d64a3 K |
420 | interrupt-controller; |
421 | #interrupt-cells = <2>; | |
422 | ||
423 | dcdc1: regulator-dcdc1 { | |
424 | compatible = "ti,tps65218-dcdc1"; | |
425 | regulator-name = "vdd_core"; | |
426 | regulator-min-microvolt = <912000>; | |
427 | regulator-max-microvolt = <1144000>; | |
428 | regulator-boot-on; | |
429 | regulator-always-on; | |
430 | }; | |
431 | ||
432 | dcdc2: regulator-dcdc2 { | |
433 | compatible = "ti,tps65218-dcdc2"; | |
434 | regulator-name = "vdd_mpu"; | |
435 | regulator-min-microvolt = <912000>; | |
436 | regulator-max-microvolt = <1378000>; | |
437 | regulator-boot-on; | |
438 | regulator-always-on; | |
439 | }; | |
440 | ||
441 | dcdc3: regulator-dcdc3 { | |
442 | compatible = "ti,tps65218-dcdc3"; | |
443 | regulator-name = "vdcdc3"; | |
fc2a602f K |
444 | regulator-min-microvolt = <1500000>; |
445 | regulator-max-microvolt = <1500000>; | |
497d64a3 K |
446 | regulator-boot-on; |
447 | regulator-always-on; | |
448 | }; | |
449 | ||
7ec341d9 PU |
450 | dcdc4: regulator-dcdc4 { |
451 | compatible = "ti,tps65218-dcdc4"; | |
452 | regulator-name = "vdcdc4"; | |
453 | regulator-min-microvolt = <3300000>; | |
454 | regulator-max-microvolt = <3300000>; | |
455 | regulator-boot-on; | |
456 | regulator-always-on; | |
457 | }; | |
458 | ||
497d64a3 K |
459 | dcdc5: regulator-dcdc5 { |
460 | compatible = "ti,tps65218-dcdc5"; | |
461 | regulator-name = "v1_0bat"; | |
462 | regulator-min-microvolt = <1000000>; | |
463 | regulator-max-microvolt = <1000000>; | |
464 | }; | |
465 | ||
466 | dcdc6: regulator-dcdc6 { | |
467 | compatible = "ti,tps65218-dcdc6"; | |
468 | regulator-name = "v1_8bat"; | |
469 | regulator-min-microvolt = <1800000>; | |
470 | regulator-max-microvolt = <1800000>; | |
471 | }; | |
472 | ||
473 | ldo1: regulator-ldo1 { | |
474 | compatible = "ti,tps65218-ldo1"; | |
475 | regulator-min-microvolt = <1800000>; | |
476 | regulator-max-microvolt = <1800000>; | |
477 | regulator-boot-on; | |
478 | regulator-always-on; | |
479 | }; | |
480 | }; | |
e54686e4 M |
481 | |
482 | at24@50 { | |
483 | compatible = "at24,24c256"; | |
484 | pagesize = <64>; | |
485 | reg = <0x50>; | |
486 | }; | |
487 | ||
488 | pixcir_ts@5c { | |
6cfcb5be RQ |
489 | compatible = "pixcir,pixcir_tangoc"; |
490 | pinctrl-names = "default"; | |
491 | pinctrl-0 = <&pixcir_ts_pins>; | |
e54686e4 M |
492 | reg = <0x5c>; |
493 | interrupt-parent = <&gpio1>; | |
494 | interrupts = <17 0>; | |
495 | ||
496 | attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; | |
497 | ||
342666ce RQ |
498 | touchscreen-size-x = <1024>; |
499 | touchscreen-size-y = <600>; | |
e54686e4 | 500 | }; |
cbfc7e6f PU |
501 | |
502 | tlv320aic3111: tlv320aic3111@18 { | |
22d7fb57 | 503 | #sound-dai-cells = <0>; |
cbfc7e6f PU |
504 | compatible = "ti,tlv320aic3111"; |
505 | reg = <0x18>; | |
506 | status = "okay"; | |
507 | ||
508 | ai31xx-micbias-vg = <MICBIAS_2_0V>; | |
509 | ||
510 | /* Regulators */ | |
511 | HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ | |
512 | SPRVDD-supply = <&vbat>; /* vbat */ | |
513 | SPLVDD-supply = <&vbat>; /* vbat */ | |
514 | AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ | |
515 | IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ | |
516 | DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ | |
517 | }; | |
e54686e4 M |
518 | }; |
519 | ||
0aeaf1c6 SP |
520 | &i2c2 { |
521 | pinctrl-names = "default"; | |
522 | pinctrl-0 = <&i2c2_pins>; | |
523 | status = "okay"; | |
524 | }; | |
525 | ||
e54686e4 M |
526 | &gpio0 { |
527 | status = "okay"; | |
528 | }; | |
529 | ||
530 | &gpio1 { | |
531 | status = "okay"; | |
532 | }; | |
533 | ||
534 | &gpio2 { | |
56fd3dc7 PU |
535 | pinctrl-names = "default"; |
536 | pinctrl-0 = <&display_mux_pins>; | |
e54686e4 | 537 | status = "okay"; |
56fd3dc7 PU |
538 | |
539 | p1 { | |
540 | /* | |
541 | * SelLCDorHDMI selects between display and audio paths: | |
542 | * Low: HDMI display with audio via HDMI | |
543 | * High: LCD display with analog audio via aic3111 codec | |
544 | */ | |
545 | gpio-hog; | |
546 | gpios = <1 GPIO_ACTIVE_HIGH>; | |
547 | output-high; | |
548 | line-name = "SelLCDorHDMI"; | |
549 | }; | |
e54686e4 M |
550 | }; |
551 | ||
552 | &gpio3 { | |
553 | status = "okay"; | |
4730bcfb | 554 | }; |
f68e355c PG |
555 | |
556 | &elm { | |
557 | status = "okay"; | |
558 | }; | |
559 | ||
560 | &gpmc { | |
331bbb59 | 561 | status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ |
f68e355c PG |
562 | pinctrl-names = "default"; |
563 | pinctrl-0 = <&nand_flash_x8>; | |
e2c5eb78 | 564 | ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ |
f68e355c | 565 | nand@0,0 { |
e2c5eb78 | 566 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
db01e6c7 | 567 | ti,nand-ecc-opt = "bch16"; |
f68e355c PG |
568 | ti,elm-id = <&elm>; |
569 | nand-bus-width = <8>; | |
570 | gpmc,device-width = <1>; | |
571 | gpmc,sync-clk-ps = <0>; | |
572 | gpmc,cs-on-ns = <0>; | |
573 | gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ | |
574 | gpmc,cs-wr-off-ns = <40>; | |
575 | gpmc,adv-on-ns = <0>; /* cs-on-ns */ | |
576 | gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ | |
577 | gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ | |
578 | gpmc,we-on-ns = <0>; /* cs-on-ns */ | |
579 | gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ | |
580 | gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ | |
581 | gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ | |
582 | gpmc,access-ns = <30>; /* tCEA + 4*/ | |
583 | gpmc,rd-cycle-ns = <40>; | |
584 | gpmc,wr-cycle-ns = <40>; | |
e47acd96 | 585 | gpmc,wait-pin = <0>; |
f68e355c PG |
586 | gpmc,bus-turnaround-ns = <0>; |
587 | gpmc,cycle2cycle-delay-ns = <0>; | |
588 | gpmc,clk-activation-ns = <0>; | |
589 | gpmc,wait-monitoring-ns = <0>; | |
590 | gpmc,wr-access-ns = <40>; | |
591 | gpmc,wr-data-mux-bus-ns = <0>; | |
592 | /* MTD partition table */ | |
593 | /* All SPL-* partitions are sized to minimal length | |
594 | * which can be independently programmable. For | |
595 | * NAND flash this is equal to size of erase-block */ | |
596 | #address-cells = <1>; | |
597 | #size-cells = <1>; | |
598 | partition@0 { | |
599 | label = "NAND.SPL"; | |
600 | reg = <0x00000000 0x00040000>; | |
601 | }; | |
602 | partition@1 { | |
603 | label = "NAND.SPL.backup1"; | |
604 | reg = <0x00040000 0x00040000>; | |
605 | }; | |
606 | partition@2 { | |
607 | label = "NAND.SPL.backup2"; | |
608 | reg = <0x00080000 0x00040000>; | |
609 | }; | |
610 | partition@3 { | |
611 | label = "NAND.SPL.backup3"; | |
612 | reg = <0x000C0000 0x00040000>; | |
613 | }; | |
614 | partition@4 { | |
615 | label = "NAND.u-boot-spl-os"; | |
616 | reg = <0x00100000 0x00080000>; | |
617 | }; | |
618 | partition@5 { | |
619 | label = "NAND.u-boot"; | |
620 | reg = <0x00180000 0x00100000>; | |
621 | }; | |
622 | partition@6 { | |
623 | label = "NAND.u-boot-env"; | |
624 | reg = <0x00280000 0x00040000>; | |
625 | }; | |
626 | partition@7 { | |
627 | label = "NAND.u-boot-env.backup1"; | |
628 | reg = <0x002C0000 0x00040000>; | |
629 | }; | |
630 | partition@8 { | |
631 | label = "NAND.kernel"; | |
632 | reg = <0x00300000 0x00700000>; | |
633 | }; | |
634 | partition@9 { | |
635 | label = "NAND.file-system"; | |
c4de4ecd | 636 | reg = <0x00a00000 0x1f600000>; |
f68e355c PG |
637 | }; |
638 | }; | |
639 | }; | |
f777ba17 | 640 | |
2e3a9385 SP |
641 | &epwmss0 { |
642 | status = "okay"; | |
643 | }; | |
644 | ||
0f39f7b9 V |
645 | &tscadc { |
646 | status = "okay"; | |
647 | ||
648 | adc { | |
649 | ti,adc-channels = <0 1 2 3 4 5 6 7>; | |
650 | }; | |
651 | }; | |
652 | ||
2e3a9385 SP |
653 | &ecap0 { |
654 | status = "okay"; | |
655 | pinctrl-names = "default"; | |
656 | pinctrl-0 = <&ecap0_pins>; | |
657 | }; | |
416f3d50 SP |
658 | |
659 | &spi0 { | |
660 | pinctrl-names = "default"; | |
661 | pinctrl-0 = <&spi0_pins>; | |
662 | status = "okay"; | |
663 | }; | |
664 | ||
665 | &spi1 { | |
666 | pinctrl-names = "default"; | |
667 | pinctrl-0 = <&spi1_pins>; | |
668 | status = "okay"; | |
669 | }; | |
61d5924f GC |
670 | |
671 | &usb2_phy1 { | |
672 | status = "okay"; | |
673 | }; | |
674 | ||
675 | &usb1 { | |
676 | dr_mode = "peripheral"; | |
677 | status = "okay"; | |
678 | }; | |
679 | ||
680 | &usb2_phy2 { | |
681 | status = "okay"; | |
682 | }; | |
683 | ||
684 | &usb2 { | |
685 | dr_mode = "host"; | |
686 | status = "okay"; | |
687 | }; | |
2a1a5043 SP |
688 | |
689 | &qspi { | |
331bbb59 | 690 | status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ |
2a1a5043 SP |
691 | pinctrl-names = "default"; |
692 | pinctrl-0 = <&qspi1_default>; | |
693 | ||
694 | spi-max-frequency = <48000000>; | |
695 | m25p80@0 { | |
696 | compatible = "mx66l51235l"; | |
697 | spi-max-frequency = <48000000>; | |
698 | reg = <0>; | |
699 | spi-cpol; | |
700 | spi-cpha; | |
701 | spi-tx-bus-width = <1>; | |
702 | spi-rx-bus-width = <4>; | |
703 | #address-cells = <1>; | |
704 | #size-cells = <1>; | |
705 | ||
706 | /* MTD partition table. | |
707 | * The ROM checks the first 512KiB | |
708 | * for a valid file to boot(XIP). | |
709 | */ | |
710 | partition@0 { | |
711 | label = "QSPI.U_BOOT"; | |
712 | reg = <0x00000000 0x000080000>; | |
713 | }; | |
714 | partition@1 { | |
715 | label = "QSPI.U_BOOT.backup"; | |
716 | reg = <0x00080000 0x00080000>; | |
717 | }; | |
718 | partition@2 { | |
719 | label = "QSPI.U-BOOT-SPL_OS"; | |
720 | reg = <0x00100000 0x00010000>; | |
721 | }; | |
722 | partition@3 { | |
723 | label = "QSPI.U_BOOT_ENV"; | |
724 | reg = <0x00110000 0x00010000>; | |
725 | }; | |
726 | partition@4 { | |
727 | label = "QSPI.U-BOOT-ENV.backup"; | |
728 | reg = <0x00120000 0x00010000>; | |
729 | }; | |
730 | partition@5 { | |
731 | label = "QSPI.KERNEL"; | |
732 | reg = <0x00130000 0x0800000>; | |
733 | }; | |
734 | partition@6 { | |
735 | label = "QSPI.FILESYSTEM"; | |
736 | reg = <0x00930000 0x36D0000>; | |
737 | }; | |
738 | }; | |
739 | }; | |
741cac5f SP |
740 | |
741 | &hdq { | |
742 | status = "okay"; | |
743 | pinctrl-names = "default"; | |
744 | pinctrl-0 = <&hdq_pins>; | |
745 | }; | |
999c3f1a TV |
746 | |
747 | &dss { | |
748 | status = "ok"; | |
749 | ||
750 | pinctrl-names = "default"; | |
751 | pinctrl-0 = <&dss_pins>; | |
752 | ||
753 | port { | |
754 | dpi_out: endpoint@0 { | |
755 | remote-endpoint = <&lcd_in>; | |
756 | data-lines = <24>; | |
757 | }; | |
758 | }; | |
759 | }; | |
d890edcd BP |
760 | |
761 | &vpfe1 { | |
762 | status = "okay"; | |
763 | pinctrl-names = "default", "sleep"; | |
764 | pinctrl-0 = <&vpfe1_pins_default>; | |
765 | pinctrl-1 = <&vpfe1_pins_sleep>; | |
766 | ||
767 | port { | |
768 | vpfe1_ep: endpoint { | |
769 | /* remote-endpoint = <&sensor>; add once we have it */ | |
770 | ti,am437x-vpfe-interface = <0>; | |
771 | bus-width = <8>; | |
772 | hsync-active = <0>; | |
773 | vsync-active = <0>; | |
774 | }; | |
775 | }; | |
776 | }; | |
06e2bf6b PU |
777 | |
778 | &mcasp1 { | |
22d7fb57 | 779 | #sound-dai-cells = <0>; |
06e2bf6b PU |
780 | pinctrl-names = "default", "sleep"; |
781 | pinctrl-0 = <&mcasp1_pins>; | |
782 | pinctrl-1 = <&mcasp1_sleep_pins>; | |
783 | ||
784 | status = "okay"; | |
785 | ||
786 | op-mode = <0>; /* MCASP_IIS_MODE */ | |
787 | tdm-slots = <2>; | |
788 | /* 4 serializer */ | |
789 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | |
790 | 1 2 0 0 | |
791 | >; | |
792 | tx-num-evt = <32>; | |
793 | rx-num-evt = <32>; | |
794 | }; |