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ARM: dts: am335x-igep0033: use phandles for USB and DMA refs
[deliverable/linux.git] / arch / arm / boot / dts / am43x-epos-evm.dts
CommitLineData
4730bcfb
AM		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM43x EPOS EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
e54686e4
M		 14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h>
2e3a9385 16#include <dt-bindings/pwm/pwm.h>
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AM		 17
18/ {
19 model = "TI AM43x EPOS EVM";
20 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
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M		 21
22 vmmcsd_fixed: fixedregulator-sd {
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 enable-active-high;
28 };
29
30 am43xx_pinmux: pinmux@44e10800 {
31 cpsw_default: cpsw_default {
32 pinctrl-single,pins = <
33 /* Slave 1 */
34 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
35 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
36 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
37 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
38 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
39 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
40 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
41 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
42 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
43 >;
44 };
45
46 cpsw_sleep: cpsw_sleep {
47 pinctrl-single,pins = <
48 /* Slave 1 reset value */
49 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
50 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
51 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
52 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
53 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
54 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
55 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
56 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
57 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
58 >;
59 };
60
61 davinci_mdio_default: davinci_mdio_default {
62 pinctrl-single,pins = <
63 /* MDIO */
64 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
65 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
66 >;
67 };
68
69 davinci_mdio_sleep: davinci_mdio_sleep {
70 pinctrl-single,pins = <
71 /* MDIO reset value */
72 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
73 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
74 >;
75 };
76
77 i2c0_pins: pinmux_i2c0_pins {
78 pinctrl-single,pins = <
79 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
80 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
81 >;
82 };
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PG		 83
84 nand_flash_x8: nand_flash_x8 {
85 pinctrl-single,pins = <
86 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
87 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
88 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
89 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
90 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
91 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
92 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
93 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
94 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
95 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
96 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
97 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
98 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
99 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
100 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
101 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
102 >;
103 };
f777ba17 104
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SP		 105 ecap0_pins: backlight_pins {
106 pinctrl-single,pins = <
107 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
108 >;
109 };
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SP		 110
111 i2c2_pins: pinmux_i2c2_pins {
112 pinctrl-single,pins = <
113 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
114 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
115 >;
116 };
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SP		 117
118 spi0_pins: pinmux_spi0_pins {
119 pinctrl-single,pins = <
120 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
121 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
122 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
123 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
124 >;
125 };
126
127 spi1_pins: pinmux_spi1_pins {
128 pinctrl-single,pins = <
129 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
130 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
131 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
132 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
133 >;
134 };
d2885dbb
B		 135
136 mmc1_pins: pinmux_mmc1_pins {
137 pinctrl-single,pins = <
138 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
139 >;
140 };
2a1a5043
SP		 141
142 qspi1_default: qspi1_default {
143 pinctrl-single,pins = <
144 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
145 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
146 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
147 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
148 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
149 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
150 >;
151 };
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M		 152 };
153
154 matrix_keypad: matrix_keypad@0 {
155 compatible = "gpio-matrix-keypad";
156 debounce-delay-ms = <5>;
157 col-scan-delay-us = <2>;
158
159 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
160 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
161 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
162 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
163
164 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
165 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
166 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
167 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
168
169 linux,keymap = <0x00000201 /* P1 */
170 0x01000204 /* P4 */
171 0x02000207 /* P7 */
172 0x0300020a /* NUMERIC_STAR */
173 0x00010202 /* P2 */
174 0x01010205 /* P5 */
175 0x02010208 /* P8 */
176 0x03010200 /* P0 */
177 0x00020203 /* P3 */
178 0x01020206 /* P6 */
179 0x02020209 /* P9 */
180 0x0302020b /* NUMERIC_POUND */
181 0x00030067 /* UP */
182 0x0103006a /* RIGHT */
183 0x0203006c /* DOWN */
184 0x03030069>; /* LEFT */
185 };
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SP		 186
187 backlight {
188 compatible = "pwm-backlight";
189 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
190 brightness-levels = <0 51 53 56 62 75 101 152 255>;
191 default-brightness-level = <8>;
192 };
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M		 193};
194
195&mmc1 {
196 status = "okay";
197 vmmc-supply = <&vmmcsd_fixed>;
198 bus-width = <4>;
d2885dbb
B		 199 pinctrl-names = "default";
200 pinctrl-0 = <&mmc1_pins>;
201 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
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M		 202};
203
204&mac {
205 pinctrl-names = "default", "sleep";
206 pinctrl-0 = <&cpsw_default>;
207 pinctrl-1 = <&cpsw_sleep>;
208 status = "okay";
209};
210
211&davinci_mdio {
212 pinctrl-names = "default", "sleep";
213 pinctrl-0 = <&davinci_mdio_default>;
214 pinctrl-1 = <&davinci_mdio_sleep>;
215 status = "okay";
216};
217
218&cpsw_emac0 {
219 phy_id = <&davinci_mdio>, <16>;
220 phy-mode = "rmii";
221};
222
223&cpsw_emac1 {
224 phy_id = <&davinci_mdio>, <1>;
225 phy-mode = "rmii";
226};
227
228&i2c0 {
229 status = "okay";
230 pinctrl-names = "default";
231 pinctrl-0 = <&i2c0_pins>;
232
233 at24@50 {
234 compatible = "at24,24c256";
235 pagesize = <64>;
236 reg = <0x50>;
237 };
238
239 pixcir_ts@5c {
240 compatible = "pixcir,pixcir_ts";
241 reg = <0x5c>;
242 interrupt-parent = <&gpio1>;
243 interrupts = <17 0>;
244
245 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
246
247 x-size = <1024>;
248 y-size = <768>;
249 };
250};
251
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SP		 252&i2c2 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&i2c2_pins>;
255 status = "okay";
256};
257
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M		 258&gpio0 {
259 status = "okay";
260};
261
262&gpio1 {
263 status = "okay";
264};
265
266&gpio2 {
267 status = "okay";
268};
269
270&gpio3 {
271 status = "okay";
4730bcfb 272};
f68e355c
PG		 273
274&elm {
275 status = "okay";
276};
277
278&gpmc {
279 status = "okay";
280 pinctrl-names = "default";
281 pinctrl-0 = <&nand_flash_x8>;
282 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
283 nand@0,0 {
284 reg = <0 0 0>; /* CS0, offset 0 */
285 ti,nand-ecc-opt = "bch8";
286 ti,elm-id = <&elm>;
287 nand-bus-width = <8>;
288 gpmc,device-width = <1>;
289 gpmc,sync-clk-ps = <0>;
290 gpmc,cs-on-ns = <0>;
291 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
292 gpmc,cs-wr-off-ns = <40>;
293 gpmc,adv-on-ns = <0>; /* cs-on-ns */
294 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
295 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
296 gpmc,we-on-ns = <0>; /* cs-on-ns */
297 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
298 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
299 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
300 gpmc,access-ns = <30>; /* tCEA + 4*/
301 gpmc,rd-cycle-ns = <40>;
302 gpmc,wr-cycle-ns = <40>;
303 gpmc,wait-on-read = "true";
304 gpmc,wait-on-write = "true";
305 gpmc,bus-turnaround-ns = <0>;
306 gpmc,cycle2cycle-delay-ns = <0>;
307 gpmc,clk-activation-ns = <0>;
308 gpmc,wait-monitoring-ns = <0>;
309 gpmc,wr-access-ns = <40>;
310 gpmc,wr-data-mux-bus-ns = <0>;
311 /* MTD partition table */
312 /* All SPL-* partitions are sized to minimal length
313 * which can be independently programmable. For
314 * NAND flash this is equal to size of erase-block */
315 #address-cells = <1>;
316 #size-cells = <1>;
317 partition@0 {
318 label = "NAND.SPL";
319 reg = <0x00000000 0x00040000>;
320 };
321 partition@1 {
322 label = "NAND.SPL.backup1";
323 reg = <0x00040000 0x00040000>;
324 };
325 partition@2 {
326 label = "NAND.SPL.backup2";
327 reg = <0x00080000 0x00040000>;
328 };
329 partition@3 {
330 label = "NAND.SPL.backup3";
331 reg = <0x000C0000 0x00040000>;
332 };
333 partition@4 {
334 label = "NAND.u-boot-spl-os";
335 reg = <0x00100000 0x00080000>;
336 };
337 partition@5 {
338 label = "NAND.u-boot";
339 reg = <0x00180000 0x00100000>;
340 };
341 partition@6 {
342 label = "NAND.u-boot-env";
343 reg = <0x00280000 0x00040000>;
344 };
345 partition@7 {
346 label = "NAND.u-boot-env.backup1";
347 reg = <0x002C0000 0x00040000>;
348 };
349 partition@8 {
350 label = "NAND.kernel";
351 reg = <0x00300000 0x00700000>;
352 };
353 partition@9 {
354 label = "NAND.file-system";
355 reg = <0x00800000 0x1F600000>;
356 };
357 };
358};
f777ba17 359
2e3a9385
SP		 360&epwmss0 {
361 status = "okay";
362};
363
364&ecap0 {
365 status = "okay";
366 pinctrl-names = "default";
367 pinctrl-0 = <&ecap0_pins>;
368};
416f3d50
SP		 369
370&spi0 {
371 pinctrl-names = "default";
372 pinctrl-0 = <&spi0_pins>;
373 status = "okay";
374};
375
376&spi1 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&spi1_pins>;
379 status = "okay";
380};
61d5924f
GC		 381
382&usb2_phy1 {
383 status = "okay";
384};
385
386&usb1 {
387 dr_mode = "peripheral";
388 status = "okay";
389};
390
391&usb2_phy2 {
392 status = "okay";
393};
394
395&usb2 {
396 dr_mode = "host";
397 status = "okay";
398};
2a1a5043
SP		 399
400&qspi {
401 status = "okay";
402 pinctrl-names = "default";
403 pinctrl-0 = <&qspi1_default>;
404
405 spi-max-frequency = <48000000>;
406 m25p80@0 {
407 compatible = "mx66l51235l";
408 spi-max-frequency = <48000000>;
409 reg = <0>;
410 spi-cpol;
411 spi-cpha;
412 spi-tx-bus-width = <1>;
413 spi-rx-bus-width = <4>;
414 #address-cells = <1>;
415 #size-cells = <1>;
416
417 /* MTD partition table.
418 * The ROM checks the first 512KiB
419 * for a valid file to boot(XIP).
420 */
421 partition@0 {
422 label = "QSPI.U_BOOT";
423 reg = <0x00000000 0x000080000>;
424 };
425 partition@1 {
426 label = "QSPI.U_BOOT.backup";
427 reg = <0x00080000 0x00080000>;
428 };
429 partition@2 {
430 label = "QSPI.U-BOOT-SPL_OS";
431 reg = <0x00100000 0x00010000>;
432 };
433 partition@3 {
434 label = "QSPI.U_BOOT_ENV";
435 reg = <0x00110000 0x00010000>;
436 };
437 partition@4 {
438 label = "QSPI.U-BOOT-ENV.backup";
439 reg = <0x00120000 0x00010000>;
440 };
441 partition@5 {
442 label = "QSPI.KERNEL";
443 reg = <0x00130000 0x0800000>;
444 };
445 partition@6 {
446 label = "QSPI.FILESYSTEM";
447 reg = <0x00930000 0x36D0000>;
448 };
449 };
450};
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