Commit | Line | Data |
---|---|---|
9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
8a88daf8 GC |
11 | * This file is dual-licensed: you can use it either under the terms |
12 | * of the GPL or the X11 license, at your option. Note that this dual | |
13 | * licensing only applies to this file, and not this project as a | |
14 | * whole. | |
15 | * | |
16 | * a) This file is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of the | |
19 | * License, or (at your option) any later version. | |
20 | * | |
21 | * This file is distributed in the hope that it will be useful | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * Or, alternatively | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
9ae6f740 TP |
48 | * |
49 | * This file contains the definitions that are common to the Armada | |
50 | * 370 and Armada XP SoC. | |
51 | */ | |
52 | ||
74898364 | 53 | /include/ "skeleton64.dtsi" |
9ae6f740 | 54 | |
5e12a613 EG |
55 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
56 | ||
9ae6f740 TP |
57 | / { |
58 | model = "Marvell Armada 370 and XP SoC"; | |
92ece1cd | 59 | compatible = "marvell,armada-370-xp"; |
9ae6f740 | 60 | |
be5a9389 | 61 | aliases { |
bf6acf16 TP |
62 | serial0 = &uart0; |
63 | serial1 = &uart1; | |
be5a9389 WT |
64 | }; |
65 | ||
9ae6f740 | 66 | cpus { |
7a7ed290 LP |
67 | #address-cells = <1>; |
68 | #size-cells = <0>; | |
9ae6f740 TP |
69 | cpu@0 { |
70 | compatible = "marvell,sheeva-v7"; | |
7a7ed290 LP |
71 | device_type = "cpu"; |
72 | reg = <0>; | |
9ae6f740 TP |
73 | }; |
74 | }; | |
75 | ||
a87cd07b MR |
76 | pmu { |
77 | compatible = "arm,cortex-a9-pmu"; | |
78 | interrupts-extended = <&mpic 3>; | |
79 | }; | |
80 | ||
9ae6f740 | 81 | soc { |
5e12a613 | 82 | #address-cells = <2>; |
9ae6f740 | 83 | #size-cells = <1>; |
5e12a613 | 84 | controller = <&mbusc>; |
9ae6f740 | 85 | interrupt-parent = <&mpic>; |
46febc63 TP |
86 | pcie-mem-aperture = <0xf8000000 0x7e00000>; |
87 | pcie-io-aperture = <0xffe00000 0x100000>; | |
9ae6f740 | 88 | |
de1af8d4 EG |
89 | devbus-bootcs { |
90 | compatible = "marvell,mvebu-devbus"; | |
91 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | |
92 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | |
93 | #address-cells = <1>; | |
94 | #size-cells = <1>; | |
95 | clocks = <&coreclk 0>; | |
96 | status = "disabled"; | |
97 | }; | |
98 | ||
99 | devbus-cs0 { | |
100 | compatible = "marvell,mvebu-devbus"; | |
101 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | |
102 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | |
103 | #address-cells = <1>; | |
104 | #size-cells = <1>; | |
105 | clocks = <&coreclk 0>; | |
106 | status = "disabled"; | |
107 | }; | |
108 | ||
109 | devbus-cs1 { | |
110 | compatible = "marvell,mvebu-devbus"; | |
111 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | |
112 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | clocks = <&coreclk 0>; | |
116 | status = "disabled"; | |
117 | }; | |
118 | ||
119 | devbus-cs2 { | |
120 | compatible = "marvell,mvebu-devbus"; | |
121 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | |
122 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | |
123 | #address-cells = <1>; | |
124 | #size-cells = <1>; | |
125 | clocks = <&coreclk 0>; | |
126 | status = "disabled"; | |
127 | }; | |
128 | ||
129 | devbus-cs3 { | |
130 | compatible = "marvell,mvebu-devbus"; | |
131 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | |
132 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | |
133 | #address-cells = <1>; | |
134 | #size-cells = <1>; | |
135 | clocks = <&coreclk 0>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | ||
467f54b2 GC |
139 | internal-regs { |
140 | compatible = "simple-bus"; | |
141 | #address-cells = <1>; | |
142 | #size-cells = <1>; | |
5e12a613 EG |
143 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
144 | ||
a095b1c7 JC |
145 | rtc@10300 { |
146 | compatible = "marvell,orion-rtc"; | |
147 | reg = <0x10300 0x20>; | |
148 | interrupts = <50>; | |
5e12a613 | 149 | }; |
467f54b2 | 150 | |
a095b1c7 JC |
151 | i2c0: i2c@11000 { |
152 | compatible = "marvell,mv64xxx-i2c"; | |
153 | #address-cells = <1>; | |
154 | #size-cells = <0>; | |
155 | interrupts = <31>; | |
156 | timeout-ms = <1000>; | |
157 | clocks = <&coreclk 0>; | |
158 | status = "disabled"; | |
159 | }; | |
160 | ||
161 | i2c1: i2c@11100 { | |
162 | compatible = "marvell,mv64xxx-i2c"; | |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
165 | interrupts = <32>; | |
166 | timeout-ms = <1000>; | |
167 | clocks = <&coreclk 0>; | |
168 | status = "disabled"; | |
467f54b2 | 169 | }; |
b18ea4dc | 170 | |
181d9b28 | 171 | uart0: serial@12000 { |
b24212fb | 172 | compatible = "snps,dw-apb-uart"; |
82a68267 | 173 | reg = <0x12000 0x100>; |
9ae6f740 TP |
174 | reg-shift = <2>; |
175 | interrupts = <41>; | |
e366154f | 176 | reg-io-width = <1>; |
64939dc5 | 177 | clocks = <&coreclk 0>; |
9ae6f740 | 178 | status = "disabled"; |
467f54b2 | 179 | }; |
181d9b28 AE |
180 | |
181 | uart1: serial@12100 { | |
b24212fb | 182 | compatible = "snps,dw-apb-uart"; |
82a68267 | 183 | reg = <0x12100 0x100>; |
9ae6f740 TP |
184 | reg-shift = <2>; |
185 | interrupts = <42>; | |
e366154f | 186 | reg-io-width = <1>; |
64939dc5 | 187 | clocks = <&coreclk 0>; |
9ae6f740 | 188 | status = "disabled"; |
467f54b2 GC |
189 | }; |
190 | ||
4904a82a AE |
191 | pinctrl: pin-ctrl@18000 { |
192 | reg = <0x18000 0x38>; | |
193 | }; | |
194 | ||
f039dfb5 EG |
195 | coredivclk: corediv-clock@18740 { |
196 | compatible = "marvell,armada-370-corediv-clock"; | |
197 | reg = <0x18740 0xc>; | |
198 | #clock-cells = <1>; | |
199 | clocks = <&mainpll>; | |
200 | clock-output-names = "nand"; | |
201 | }; | |
202 | ||
a095b1c7 JC |
203 | mbusc: mbus-controller@20000 { |
204 | compatible = "marvell,mbus-controller"; | |
8b7dc9d3 TP |
205 | reg = <0x20000 0x100>, <0x20180 0x20>, |
206 | <0x20250 0x8>; | |
a095b1c7 JC |
207 | }; |
208 | ||
24c2573b | 209 | mpic: interrupt-controller@20a00 { |
a095b1c7 JC |
210 | compatible = "marvell,mpic"; |
211 | #interrupt-cells = <1>; | |
212 | #size-cells = <1>; | |
213 | interrupt-controller; | |
214 | msi-controller; | |
215 | }; | |
216 | ||
217 | coherency-fabric@20200 { | |
218 | compatible = "marvell,coherency-fabric"; | |
939ac3cd | 219 | reg = <0x20200 0xb0>, <0x21010 0x1c>; |
a095b1c7 JC |
220 | }; |
221 | ||
467f54b2 | 222 | timer@20300 { |
467f54b2 GC |
223 | reg = <0x20300 0x30>, <0x21040 0x30>; |
224 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | |
467f54b2 GC |
225 | }; |
226 | ||
05afeeb9 EG |
227 | watchdog@20300 { |
228 | reg = <0x20300 0x34>, <0x20704 0x4>; | |
229 | }; | |
230 | ||
b6249d4b GC |
231 | pmsu@22000 { |
232 | compatible = "marvell,armada-370-pmsu"; | |
233 | reg = <0x22000 0x1000>; | |
234 | }; | |
235 | ||
a095b1c7 JC |
236 | usb@50000 { |
237 | compatible = "marvell,orion-ehci"; | |
238 | reg = <0x50000 0x500>; | |
239 | interrupts = <45>; | |
467f54b2 GC |
240 | status = "disabled"; |
241 | }; | |
a6a6de1a | 242 | |
a095b1c7 JC |
243 | usb@51000 { |
244 | compatible = "marvell,orion-ehci"; | |
245 | reg = <0x51000 0x500>; | |
246 | interrupts = <46>; | |
247 | status = "disabled"; | |
467f54b2 | 248 | }; |
323c1010 | 249 | |
be5a9389 | 250 | eth0: ethernet@70000 { |
cf8088c5 | 251 | reg = <0x70000 0x4000>; |
323c1010 | 252 | interrupts = <8>; |
4aa935a2 | 253 | clocks = <&gateclk 4>; |
323c1010 | 254 | status = "disabled"; |
467f54b2 | 255 | }; |
323c1010 | 256 | |
9ef90cbb | 257 | mdio: mdio { |
a095b1c7 JC |
258 | #address-cells = <1>; |
259 | #size-cells = <0>; | |
260 | compatible = "marvell,orion-mdio"; | |
261 | reg = <0x72004 0x4>; | |
a6e03dd4 | 262 | clocks = <&gateclk 4>; |
a095b1c7 JC |
263 | }; |
264 | ||
be5a9389 | 265 | eth1: ethernet@74000 { |
cf8088c5 | 266 | reg = <0x74000 0x4000>; |
323c1010 | 267 | interrupts = <10>; |
4aa935a2 | 268 | clocks = <&gateclk 3>; |
323c1010 | 269 | status = "disabled"; |
467f54b2 GC |
270 | }; |
271 | ||
a095b1c7 | 272 | sata@a0000 { |
9b6d351a | 273 | compatible = "marvell,armada-370-sata"; |
a095b1c7 JC |
274 | reg = <0xa0000 0x5000>; |
275 | interrupts = <55>; | |
276 | clocks = <&gateclk 15>, <&gateclk 30>; | |
277 | clock-names = "0", "1"; | |
467f54b2 GC |
278 | status = "disabled"; |
279 | }; | |
280 | ||
a095b1c7 JC |
281 | nand@d0000 { |
282 | compatible = "marvell,armada370-nand"; | |
283 | reg = <0xd0000 0x54>; | |
467f54b2 | 284 | #address-cells = <1>; |
a095b1c7 JC |
285 | #size-cells = <1>; |
286 | interrupts = <113>; | |
287 | clocks = <&coredivclk 0>; | |
467f54b2 GC |
288 | status = "disabled"; |
289 | }; | |
290 | ||
467f54b2 GC |
291 | mvsdio@d4000 { |
292 | compatible = "marvell,orion-sdio"; | |
293 | reg = <0xd4000 0x200>; | |
294 | interrupts = <54>; | |
295 | clocks = <&gateclk 17>; | |
d87b5fbb SB |
296 | bus-width = <4>; |
297 | cap-sdio-irq; | |
298 | cap-sd-highspeed; | |
299 | cap-mmc-highspeed; | |
467f54b2 GC |
300 | status = "disabled"; |
301 | }; | |
3d76e1f3 | 302 | }; |
0160a4b6 SR |
303 | |
304 | spi0: spi@10600 { | |
55877f58 SR |
305 | reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */ |
306 | <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */ | |
307 | <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */ | |
308 | <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */ | |
309 | <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */ | |
310 | <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */ | |
311 | <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */ | |
312 | <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */ | |
313 | <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */ | |
0160a4b6 SR |
314 | #address-cells = <1>; |
315 | #size-cells = <0>; | |
316 | cell-index = <0>; | |
317 | interrupts = <30>; | |
318 | clocks = <&coreclk 0>; | |
319 | status = "disabled"; | |
320 | }; | |
321 | ||
322 | spi1: spi@10680 { | |
55877f58 SR |
323 | reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */ |
324 | <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */ | |
325 | <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */ | |
326 | <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */ | |
327 | <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */ | |
328 | <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */ | |
329 | <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */ | |
330 | <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */ | |
331 | <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */ | |
0160a4b6 SR |
332 | #address-cells = <1>; |
333 | #size-cells = <0>; | |
334 | cell-index = <1>; | |
335 | interrupts = <92>; | |
336 | clocks = <&coreclk 0>; | |
337 | status = "disabled"; | |
338 | }; | |
9ae6f740 | 339 | }; |
4675cf57 EG |
340 | |
341 | clocks { | |
342 | /* 2 GHz fixed main PLL */ | |
343 | mainpll: mainpll { | |
344 | compatible = "fixed-clock"; | |
345 | #clock-cells = <0>; | |
346 | clock-frequency = <2000000000>; | |
347 | }; | |
348 | }; | |
467f54b2 | 349 | }; |