[deliverable/linux.git] / arch / arm / boot / dts / armada-370-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

/include/ "skeleton64.dtsi"

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		eth0 = &eth0;
		eth1 = &eth1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	soc {
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&mpic>;
		pcie-mem-aperture = <0xf8000000 0x7e00000>;
		pcie-io-aperture  = <0xffe00000 0x100000>;

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-370-spi", "marvell,orion-spi";
				reg = <0x10600 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <30>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,armada-370-spi", "marvell,orion-spi";
				reg = <0x10680 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <92>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pin-ctrl@18000 {
				reg = <0x18000 0x38>;
			};

			coredivclk: corediv-clock@18740 {
				compatible = "marvell,armada-370-corediv-clock";
				reg = <0x18740 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21010 0x1c>;
			};

			timer@20300 {
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
			};

			watchdog@20300 {
				reg = <0x20300 0x34>, <0x20704 0x4>;
			};

			pmsu@22000 {
				compatible = "marvell,armada-370-pmsu";
				reg = <0x22000 0x1000>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			eth1: ethernet@74000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			sata@a0000 {
				compatible = "marvell,armada-370-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <113>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};
 };
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
8a88daf8 GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
	21	* This file is distributed in the hope that it will be useful
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* Or, alternatively
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740 TP	48	*
	49	* This file contains the definitions that are common to the Armada
	50	* 370 and Armada XP SoC.
	51	*/
	52
74898364	53	/include/ "skeleton64.dtsi"
9ae6f740	54
5e12a613 EG	55	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
5e12a613 EG	56
9ae6f740 TP	57	/ {
9ae6f740 TP	58	model = "Marvell Armada 370 and XP SoC";
92ece1cd	59	compatible = "marvell,armada-370-xp";
9ae6f740	60
be5a9389 WT	61	aliases {
	62	eth0 = &eth0;
	63	eth1 = &eth1;
	64	};
	65
9ae6f740	66	cpus {
7a7ed290 LP	67	#address-cells = <1>;
7a7ed290 LP	68	#size-cells = <0>;
9ae6f740 TP	69	cpu@0 {
9ae6f740 TP	70	compatible = "marvell,sheeva-v7";
7a7ed290 LP	71	device_type = "cpu";
7a7ed290 LP	72	reg = <0>;
9ae6f740 TP	73	};
	74	};
	75
9ae6f740	76	soc {
5e12a613	77	#address-cells = <2>;
9ae6f740	78	#size-cells = <1>;
5e12a613	79	controller = <&mbusc>;
9ae6f740	80	interrupt-parent = <&mpic>;
46febc63 TP	81	pcie-mem-aperture = <0xf8000000 0x7e00000>;
46febc63 TP	82	pcie-io-aperture = <0xffe00000 0x100000>;
9ae6f740	83
de1af8d4 EG	84	devbus-bootcs {
	85	compatible = "marvell,mvebu-devbus";
	86	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	87	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	88	#address-cells = <1>;
	89	#size-cells = <1>;
	90	clocks = <&coreclk 0>;
	91	status = "disabled";
	92	};
	93
	94	devbus-cs0 {
	95	compatible = "marvell,mvebu-devbus";
	96	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	97	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	clocks = <&coreclk 0>;
	101	status = "disabled";
	102	};
	103
	104	devbus-cs1 {
	105	compatible = "marvell,mvebu-devbus";
	106	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	107	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	108	#address-cells = <1>;
	109	#size-cells = <1>;
	110	clocks = <&coreclk 0>;
	111	status = "disabled";
	112	};
	113
	114	devbus-cs2 {
	115	compatible = "marvell,mvebu-devbus";
	116	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	117	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	118	#address-cells = <1>;
	119	#size-cells = <1>;
	120	clocks = <&coreclk 0>;
	121	status = "disabled";
	122	};
	123
	124	devbus-cs3 {
	125	compatible = "marvell,mvebu-devbus";
	126	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	127	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	128	#address-cells = <1>;
	129	#size-cells = <1>;
	130	clocks = <&coreclk 0>;
	131	status = "disabled";
	132	};
	133
467f54b2 GC	134	internal-regs {
	135	compatible = "simple-bus";
	136	#address-cells = <1>;
	137	#size-cells = <1>;
5e12a613 EG	138	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
5e12a613 EG	139
a095b1c7 JC	140	rtc@10300 {
	141	compatible = "marvell,orion-rtc";
	142	reg = <0x10300 0x20>;
	143	interrupts = <50>;
5e12a613	144	};
467f54b2	145
a095b1c7	146	spi0: spi@10600 {
ccf8ca4b	147	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
a095b1c7 JC	148	reg = <0x10600 0x28>;
	149	#address-cells = <1>;
	150	#size-cells = <0>;
	151	cell-index = <0>;
	152	interrupts = <30>;
	153	clocks = <&coreclk 0>;
	154	status = "disabled";
467f54b2	155	};
b18ea4dc	156
a095b1c7	157	spi1: spi@10680 {
ccf8ca4b	158	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
a095b1c7 JC	159	reg = <0x10680 0x28>;
	160	#address-cells = <1>;
	161	#size-cells = <0>;
	162	cell-index = <1>;
	163	interrupts = <92>;
	164	clocks = <&coreclk 0>;
	165	status = "disabled";
	166	};
	167
	168	i2c0: i2c@11000 {
	169	compatible = "marvell,mv64xxx-i2c";
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172	interrupts = <31>;
	173	timeout-ms = <1000>;
	174	clocks = <&coreclk 0>;
	175	status = "disabled";
	176	};
	177
	178	i2c1: i2c@11100 {
	179	compatible = "marvell,mv64xxx-i2c";
	180	#address-cells = <1>;
	181	#size-cells = <0>;
	182	interrupts = <32>;
	183	timeout-ms = <1000>;
	184	clocks = <&coreclk 0>;
	185	status = "disabled";
467f54b2	186	};
b18ea4dc	187
181d9b28	188	uart0: serial@12000 {
b24212fb	189	compatible = "snps,dw-apb-uart";
82a68267	190	reg = <0x12000 0x100>;
9ae6f740 TP	191	reg-shift = <2>;
9ae6f740 TP	192	interrupts = <41>;
e366154f	193	reg-io-width = <1>;
64939dc5	194	clocks = <&coreclk 0>;
9ae6f740	195	status = "disabled";
467f54b2	196	};
181d9b28 AE	197
181d9b28 AE	198	uart1: serial@12100 {
b24212fb	199	compatible = "snps,dw-apb-uart";
82a68267	200	reg = <0x12100 0x100>;
9ae6f740 TP	201	reg-shift = <2>;
9ae6f740 TP	202	interrupts = <42>;
e366154f	203	reg-io-width = <1>;
64939dc5	204	clocks = <&coreclk 0>;
9ae6f740	205	status = "disabled";
467f54b2 GC	206	};
467f54b2 GC	207
4904a82a AE	208	pinctrl: pin-ctrl@18000 {
	209	reg = <0x18000 0x38>;
	210	};
	211
f039dfb5 EG	212	coredivclk: corediv-clock@18740 {
	213	compatible = "marvell,armada-370-corediv-clock";
	214	reg = <0x18740 0xc>;
	215	#clock-cells = <1>;
	216	clocks = <&mainpll>;
	217	clock-output-names = "nand";
	218	};
	219
a095b1c7 JC	220	mbusc: mbus-controller@20000 {
a095b1c7 JC	221	compatible = "marvell,mbus-controller";
8b7dc9d3 TP	222	reg = <0x20000 0x100>, <0x20180 0x20>,
8b7dc9d3 TP	223	<0x20250 0x8>;
a095b1c7 JC	224	};
	225
	226	mpic: interrupt-controller@20000 {
	227	compatible = "marvell,mpic";
	228	#interrupt-cells = <1>;
	229	#size-cells = <1>;
	230	interrupt-controller;
	231	msi-controller;
	232	};
	233
	234	coherency-fabric@20200 {
	235	compatible = "marvell,coherency-fabric";
939ac3cd	236	reg = <0x20200 0xb0>, <0x21010 0x1c>;
a095b1c7 JC	237	};
a095b1c7 JC	238
467f54b2	239	timer@20300 {
467f54b2 GC	240	reg = <0x20300 0x30>, <0x21040 0x30>;
467f54b2 GC	241	interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
467f54b2 GC	242	};
467f54b2 GC	243
05afeeb9 EG	244	watchdog@20300 {
	245	reg = <0x20300 0x34>, <0x20704 0x4>;
	246	};
	247
b6249d4b GC	248	pmsu@22000 {
	249	compatible = "marvell,armada-370-pmsu";
	250	reg = <0x22000 0x1000>;
	251	};
	252
a095b1c7 JC	253	usb@50000 {
	254	compatible = "marvell,orion-ehci";
	255	reg = <0x50000 0x500>;
	256	interrupts = <45>;
467f54b2 GC	257	status = "disabled";
467f54b2 GC	258	};
a6a6de1a	259
a095b1c7 JC	260	usb@51000 {
	261	compatible = "marvell,orion-ehci";
	262	reg = <0x51000 0x500>;
	263	interrupts = <46>;
	264	status = "disabled";
467f54b2	265	};
323c1010	266
be5a9389	267	eth0: ethernet@70000 {
323c1010	268	compatible = "marvell,armada-370-neta";
cf8088c5	269	reg = <0x70000 0x4000>;
323c1010	270	interrupts = <8>;
4aa935a2	271	clocks = <&gateclk 4>;
323c1010	272	status = "disabled";
467f54b2	273	};
323c1010	274
9ef90cbb	275	mdio: mdio {
a095b1c7 JC	276	#address-cells = <1>;
	277	#size-cells = <0>;
	278	compatible = "marvell,orion-mdio";
	279	reg = <0x72004 0x4>;
a6e03dd4	280	clocks = <&gateclk 4>;
a095b1c7 JC	281	};
a095b1c7 JC	282
be5a9389	283	eth1: ethernet@74000 {
323c1010	284	compatible = "marvell,armada-370-neta";
cf8088c5	285	reg = <0x74000 0x4000>;
323c1010	286	interrupts = <10>;
4aa935a2	287	clocks = <&gateclk 3>;
323c1010	288	status = "disabled";
467f54b2 GC	289	};
467f54b2 GC	290
a095b1c7	291	sata@a0000 {
9b6d351a	292	compatible = "marvell,armada-370-sata";
a095b1c7 JC	293	reg = <0xa0000 0x5000>;
	294	interrupts = <55>;
	295	clocks = <&gateclk 15>, <&gateclk 30>;
	296	clock-names = "0", "1";
467f54b2 GC	297	status = "disabled";
	298	};
	299
a095b1c7 JC	300	nand@d0000 {
	301	compatible = "marvell,armada370-nand";
	302	reg = <0xd0000 0x54>;
467f54b2	303	#address-cells = <1>;
a095b1c7 JC	304	#size-cells = <1>;
	305	interrupts = <113>;
	306	clocks = <&coredivclk 0>;
467f54b2 GC	307	status = "disabled";
	308	};
	309
467f54b2 GC	310	mvsdio@d4000 {
	311	compatible = "marvell,orion-sdio";
	312	reg = <0xd4000 0x200>;
	313	interrupts = <54>;
	314	clocks = <&gateclk 17>;
d87b5fbb SB	315	bus-width = <4>;
	316	cap-sdio-irq;
	317	cap-sd-highspeed;
	318	cap-mmc-highspeed;
467f54b2 GC	319	status = "disabled";
467f54b2 GC	320	};
3d76e1f3	321	};
9ae6f740	322	};
4675cf57 EG	323
	324	clocks {
	325	/* 2 GHz fixed main PLL */
	326	mainpll: mainpll {
	327	compatible = "fixed-clock";
	328	#clock-cells = <0>;
	329	clock-frequency = <2000000000>;
	330	};
	331	};
467f54b2	332	};