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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
15 | * This file contains the definitions that are common to the Armada | |
16 | * 370 and Armada XP SoC. | |
17 | */ | |
18 | ||
74898364 | 19 | /include/ "skeleton64.dtsi" |
9ae6f740 | 20 | |
5e12a613 EG |
21 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
22 | ||
9ae6f740 TP |
23 | / { |
24 | model = "Marvell Armada 370 and XP SoC"; | |
92ece1cd | 25 | compatible = "marvell,armada-370-xp"; |
9ae6f740 | 26 | |
be5a9389 WT |
27 | aliases { |
28 | eth0 = ð0; | |
29 | eth1 = ð1; | |
30 | }; | |
31 | ||
9ae6f740 | 32 | cpus { |
7a7ed290 LP |
33 | #address-cells = <1>; |
34 | #size-cells = <0>; | |
9ae6f740 TP |
35 | cpu@0 { |
36 | compatible = "marvell,sheeva-v7"; | |
7a7ed290 LP |
37 | device_type = "cpu"; |
38 | reg = <0>; | |
9ae6f740 TP |
39 | }; |
40 | }; | |
41 | ||
9ae6f740 | 42 | soc { |
5e12a613 | 43 | #address-cells = <2>; |
9ae6f740 | 44 | #size-cells = <1>; |
5e12a613 | 45 | controller = <&mbusc>; |
9ae6f740 | 46 | interrupt-parent = <&mpic>; |
9ae6f740 | 47 | |
467f54b2 GC |
48 | internal-regs { |
49 | compatible = "simple-bus"; | |
50 | #address-cells = <1>; | |
51 | #size-cells = <1>; | |
5e12a613 EG |
52 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
53 | ||
54 | mbusc: mbus-controller@20000 { | |
55 | compatible = "marvell,mbus-controller"; | |
56 | reg = <0x20000 0x100>, <0x20180 0x20>; | |
57 | }; | |
467f54b2 GC |
58 | |
59 | mpic: interrupt-controller@20000 { | |
82a68267 GC |
60 | compatible = "marvell,mpic"; |
61 | #interrupt-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | interrupt-controller; | |
467f54b2 | 64 | }; |
b18ea4dc | 65 | |
467f54b2 | 66 | coherency-fabric@20200 { |
82a68267 | 67 | compatible = "marvell,coherency-fabric"; |
467f54b2 GC |
68 | reg = <0x20200 0xb0>, <0x21810 0x1c>; |
69 | }; | |
b18ea4dc | 70 | |
467f54b2 | 71 | serial@12000 { |
b24212fb | 72 | compatible = "snps,dw-apb-uart"; |
82a68267 | 73 | reg = <0x12000 0x100>; |
9ae6f740 TP |
74 | reg-shift = <2>; |
75 | interrupts = <41>; | |
e366154f | 76 | reg-io-width = <1>; |
9ae6f740 | 77 | status = "disabled"; |
467f54b2 GC |
78 | }; |
79 | serial@12100 { | |
b24212fb | 80 | compatible = "snps,dw-apb-uart"; |
82a68267 | 81 | reg = <0x12100 0x100>; |
9ae6f740 TP |
82 | reg-shift = <2>; |
83 | interrupts = <42>; | |
e366154f | 84 | reg-io-width = <1>; |
9ae6f740 | 85 | status = "disabled"; |
467f54b2 GC |
86 | }; |
87 | ||
88 | timer@20300 { | |
89 | compatible = "marvell,armada-370-xp-timer"; | |
90 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
91 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | |
92 | clocks = <&coreclk 2>; | |
93 | }; | |
94 | ||
95 | sata@a0000 { | |
96 | compatible = "marvell,orion-sata"; | |
911492de | 97 | reg = <0xa0000 0x5000>; |
467f54b2 GC |
98 | interrupts = <55>; |
99 | clocks = <&gateclk 15>, <&gateclk 30>; | |
100 | clock-names = "0", "1"; | |
101 | status = "disabled"; | |
102 | }; | |
a6a6de1a | 103 | |
467f54b2 GC |
104 | mdio { |
105 | #address-cells = <1>; | |
106 | #size-cells = <0>; | |
107 | compatible = "marvell,orion-mdio"; | |
108 | reg = <0x72004 0x4>; | |
109 | }; | |
323c1010 | 110 | |
be5a9389 | 111 | eth0: ethernet@70000 { |
323c1010 | 112 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 113 | reg = <0x70000 0x4000>; |
323c1010 | 114 | interrupts = <8>; |
4aa935a2 | 115 | clocks = <&gateclk 4>; |
323c1010 | 116 | status = "disabled"; |
467f54b2 | 117 | }; |
323c1010 | 118 | |
be5a9389 | 119 | eth1: ethernet@74000 { |
323c1010 | 120 | compatible = "marvell,armada-370-neta"; |
cf8088c5 | 121 | reg = <0x74000 0x4000>; |
323c1010 | 122 | interrupts = <10>; |
4aa935a2 | 123 | clocks = <&gateclk 3>; |
323c1010 | 124 | status = "disabled"; |
467f54b2 GC |
125 | }; |
126 | ||
127 | i2c0: i2c@11000 { | |
128 | compatible = "marvell,mv64xxx-i2c"; | |
129 | reg = <0x11000 0x20>; | |
130 | #address-cells = <1>; | |
131 | #size-cells = <0>; | |
132 | interrupts = <31>; | |
133 | timeout-ms = <1000>; | |
134 | clocks = <&coreclk 0>; | |
135 | status = "disabled"; | |
136 | }; | |
137 | ||
138 | i2c1: i2c@11100 { | |
139 | compatible = "marvell,mv64xxx-i2c"; | |
140 | reg = <0x11100 0x20>; | |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | interrupts = <32>; | |
144 | timeout-ms = <1000>; | |
145 | clocks = <&coreclk 0>; | |
146 | status = "disabled"; | |
147 | }; | |
148 | ||
149 | rtc@10300 { | |
150 | compatible = "marvell,orion-rtc"; | |
151 | reg = <0x10300 0x20>; | |
152 | interrupts = <50>; | |
153 | }; | |
154 | ||
155 | mvsdio@d4000 { | |
156 | compatible = "marvell,orion-sdio"; | |
157 | reg = <0xd4000 0x200>; | |
158 | interrupts = <54>; | |
159 | clocks = <&gateclk 17>; | |
d87b5fbb SB |
160 | bus-width = <4>; |
161 | cap-sdio-irq; | |
162 | cap-sd-highspeed; | |
163 | cap-mmc-highspeed; | |
467f54b2 GC |
164 | status = "disabled"; |
165 | }; | |
b2bb806f | 166 | |
467f54b2 GC |
167 | usb@50000 { |
168 | compatible = "marvell,orion-ehci"; | |
169 | reg = <0x50000 0x500>; | |
170 | interrupts = <45>; | |
171 | status = "disabled"; | |
172 | }; | |
d5dc035e | 173 | |
467f54b2 GC |
174 | usb@51000 { |
175 | compatible = "marvell,orion-ehci"; | |
176 | reg = <0x51000 0x500>; | |
177 | interrupts = <46>; | |
178 | status = "disabled"; | |
179 | }; | |
180 | ||
181 | spi0: spi@10600 { | |
182 | compatible = "marvell,orion-spi"; | |
183 | reg = <0x10600 0x28>; | |
184 | #address-cells = <1>; | |
185 | #size-cells = <0>; | |
186 | cell-index = <0>; | |
187 | interrupts = <30>; | |
188 | clocks = <&coreclk 0>; | |
189 | status = "disabled"; | |
190 | }; | |
191 | ||
192 | spi1: spi@10680 { | |
193 | compatible = "marvell,orion-spi"; | |
194 | reg = <0x10680 0x28>; | |
195 | #address-cells = <1>; | |
196 | #size-cells = <0>; | |
197 | cell-index = <1>; | |
198 | interrupts = <92>; | |
199 | clocks = <&coreclk 0>; | |
200 | status = "disabled"; | |
201 | }; | |
3d76e1f3 | 202 | |
467f54b2 GC |
203 | devbus-bootcs@10400 { |
204 | compatible = "marvell,mvebu-devbus"; | |
205 | reg = <0x10400 0x8>; | |
206 | #address-cells = <1>; | |
207 | #size-cells = <1>; | |
208 | clocks = <&coreclk 0>; | |
209 | status = "disabled"; | |
210 | }; | |
3d76e1f3 | 211 | |
467f54b2 GC |
212 | devbus-cs0@10408 { |
213 | compatible = "marvell,mvebu-devbus"; | |
214 | reg = <0x10408 0x8>; | |
215 | #address-cells = <1>; | |
216 | #size-cells = <1>; | |
217 | clocks = <&coreclk 0>; | |
218 | status = "disabled"; | |
219 | }; | |
3d76e1f3 | 220 | |
467f54b2 GC |
221 | devbus-cs1@10410 { |
222 | compatible = "marvell,mvebu-devbus"; | |
223 | reg = <0x10410 0x8>; | |
224 | #address-cells = <1>; | |
225 | #size-cells = <1>; | |
226 | clocks = <&coreclk 0>; | |
227 | status = "disabled"; | |
228 | }; | |
3d76e1f3 | 229 | |
467f54b2 GC |
230 | devbus-cs2@10418 { |
231 | compatible = "marvell,mvebu-devbus"; | |
232 | reg = <0x10418 0x8>; | |
233 | #address-cells = <1>; | |
234 | #size-cells = <1>; | |
235 | clocks = <&coreclk 0>; | |
236 | status = "disabled"; | |
237 | }; | |
3d76e1f3 | 238 | |
467f54b2 GC |
239 | devbus-cs3@10420 { |
240 | compatible = "marvell,mvebu-devbus"; | |
241 | reg = <0x10420 0x8>; | |
242 | #address-cells = <1>; | |
243 | #size-cells = <1>; | |
244 | clocks = <&coreclk 0>; | |
245 | status = "disabled"; | |
246 | }; | |
3d76e1f3 | 247 | }; |
9ae6f740 | 248 | }; |
467f54b2 | 249 | }; |