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0d3d96ab TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 380 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
a2be1561 | 15 | #include "armada-38x.dtsi" |
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16 | |
17 | / { | |
18 | model = "Marvell Armada 380 family SoC"; | |
8dbdb8e7 | 19 | compatible = "marvell,armada380"; |
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20 | |
21 | cpus { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
19b06d7f TP |
24 | enable-method = "marvell,armada-380-smp"; |
25 | ||
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26 | cpu@0 { |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a9"; | |
29 | reg = <0>; | |
30 | }; | |
31 | }; | |
32 | ||
33 | soc { | |
34 | internal-regs { | |
35 | pinctrl { | |
36 | compatible = "marvell,mv88f6810-pinctrl"; | |
37 | reg = <0x18000 0x20>; | |
38 | }; | |
39 | }; | |
40 | ||
41 | pcie-controller { | |
42 | compatible = "marvell,armada-370-pcie"; | |
43 | status = "disabled"; | |
44 | device_type = "pci"; | |
45 | ||
46 | #address-cells = <3>; | |
47 | #size-cells = <2>; | |
48 | ||
49 | msi-parent = <&mpic>; | |
50 | bus-range = <0x00 0xff>; | |
51 | ||
52 | ranges = | |
53 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
54 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
55 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
56 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | |
57 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | |
58 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | |
59 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | |
60 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | |
61 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | |
62 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; | |
63 | ||
64 | /* x1 port */ | |
65 | pcie@1,0 { | |
66 | device_type = "pci"; | |
67 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | |
68 | reg = <0x0800 0 0 0 0>; | |
69 | #address-cells = <3>; | |
70 | #size-cells = <2>; | |
71 | #interrupt-cells = <1>; | |
72 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
73 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
74 | interrupt-map-mask = <0 0 0 0>; | |
d11548e3 | 75 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
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76 | marvell,pcie-port = <0>; |
77 | marvell,pcie-lane = <0>; | |
78 | clocks = <&gateclk 8>; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | /* x1 port */ | |
83 | pcie@2,0 { | |
84 | device_type = "pci"; | |
85 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
86 | reg = <0x1000 0 0 0 0>; | |
87 | #address-cells = <3>; | |
88 | #size-cells = <2>; | |
89 | #interrupt-cells = <1>; | |
90 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
91 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
92 | interrupt-map-mask = <0 0 0 0>; | |
d11548e3 | 93 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
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94 | marvell,pcie-port = <1>; |
95 | marvell,pcie-lane = <0>; | |
96 | clocks = <&gateclk 5>; | |
97 | status = "disabled"; | |
98 | }; | |
99 | ||
100 | /* x1 port */ | |
101 | pcie@3,0 { | |
102 | device_type = "pci"; | |
103 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
c2a3dd9d | 104 | reg = <0x1800 0 0 0 0>; |
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105 | #address-cells = <3>; |
106 | #size-cells = <2>; | |
107 | #interrupt-cells = <1>; | |
108 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
109 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
110 | interrupt-map-mask = <0 0 0 0>; | |
d11548e3 | 111 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
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112 | marvell,pcie-port = <2>; |
113 | marvell,pcie-lane = <0>; | |
114 | clocks = <&gateclk 6>; | |
115 | status = "disabled"; | |
116 | }; | |
117 | }; | |
118 | }; | |
119 | }; |