[deliverable/linux.git] / arch / arm / boot / dts / armada-xp-mv78460.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78460 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78460 SoC";
	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		eth3 = &eth3;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <2>;
			clocks = <&cpuclk 2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <3>;
			clocks = <&cpuclk 3>;
		};
	};

	soc {
		/*
		 * MV78460 has 4 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. Two units are
		 * x4/x1.
		 */
		pcie-controller {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */

				0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
				0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 59>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 60>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};

			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 61>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 63>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};

			pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 64>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 65>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";
			};

			pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 99>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			pcie@10,0 {
				device_type = "pci";
				assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
				reg = <0x5000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
					  0x81000000 0 0 0x81000000 0xa 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 103>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 27>;
				status = "disabled";
			};
		};

		internal-regs {
			pinctrl {
				compatible = "marvell,mv78460-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins: sdio-pins {
					marvell,pins = "mpp30", "mpp31", "mpp32",
						       "mpp33", "mpp34", "mpp35";
					marvell,function = "sd0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			eth3: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78460 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
38149887	16	#include "armada-xp.dtsi"
f3b42b7c TP	17
	18	/ {
	19	model = "Marvell Armada XP MV78460 SoC";
	20	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	gpio2 = &gpio2;
be5a9389	26	eth3 = &eth3;
397d59f3 TP	27	};
397d59f3 TP	28
9d202783 GC	29
9d202783 GC	30	cpus {
1b2529d0 TP	31	#address-cells = <1>;
1b2529d0 TP	32	#size-cells = <0>;
9d202783	33
1b2529d0 TP	34	cpu@0 {
	35	device_type = "cpu";
	36	compatible = "marvell,sheeva-v7";
	37	reg = <0>;
	38	clocks = <&cpuclk 0>;
	39	};
9d202783	40
1b2529d0 TP	41	cpu@1 {
	42	device_type = "cpu";
	43	compatible = "marvell,sheeva-v7";
	44	reg = <1>;
	45	clocks = <&cpuclk 1>;
	46	};
9d202783	47
1b2529d0 TP	48	cpu@2 {
	49	device_type = "cpu";
	50	compatible = "marvell,sheeva-v7";
	51	reg = <2>;
	52	clocks = <&cpuclk 2>;
	53	};
9d202783	54
1b2529d0 TP	55	cpu@3 {
	56	device_type = "cpu";
	57	compatible = "marvell,sheeva-v7";
	58	reg = <3>;
	59	clocks = <&cpuclk 3>;
	60	};
9d202783 GC	61	};
9d202783 GC	62
f3b42b7c	63	soc {
14fd8ed0 EG	64	/*
	65	* MV78460 has 4 PCIe units Gen2.0: Two units can be
	66	* configured as x4 or quad x1 lanes. Two units are
	67	* x4/x1.
	68	*/
	69	pcie-controller {
	70	compatible = "marvell,armada-xp-pcie";
	71	status = "disabled";
	72	device_type = "pci";
	73
	74	#address-cells = <3>;
	75	#size-cells = <2>;
	76
d4fa9941	77	msi-parent = <&mpic>;
14fd8ed0 EG	78	bus-range = <0x00 0xff>;
	79
	80	ranges =
	81	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	82	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	83	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	84	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	85	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	86	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
	87	0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
	88	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	89	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	90	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
	91	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	92	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	93	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	94	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	95	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	96	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	97	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	98	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
	99
	100	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	101	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	102	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	103	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	104	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	105	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	106	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	107	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
	108
	109	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	110	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
	111
	112	0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
	113	0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
	114
	115	pcie@1,0 {
	116	device_type = "pci";
	117	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	118	reg = <0x0800 0 0 0 0>;
	119	#address-cells = <3>;
	120	#size-cells = <2>;
	121	#interrupt-cells = <1>;
	122	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	123	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	124	interrupt-map-mask = <0 0 0 0>;
	125	interrupt-map = <0 0 0 0 &mpic 58>;
	126	marvell,pcie-port = <0>;
	127	marvell,pcie-lane = <0>;
	128	clocks = <&gateclk 5>;
	129	status = "disabled";
	130	};
	131
	132	pcie@2,0 {
	133	device_type = "pci";
	134	assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
	135	reg = <0x1000 0 0 0 0>;
	136	#address-cells = <3>;
	137	#size-cells = <2>;
	138	#interrupt-cells = <1>;
	139	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	140	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	141	interrupt-map-mask = <0 0 0 0>;
142	interrupt-map = <0 0 0 0 &mpic 59>;
143	marvell,pcie-port = <0>;
144	marvell,pcie-lane = <1>;
145	clocks = <&gateclk 6>;
146	status = "disabled";
147	};
148
149	pcie@3,0 {
150	device_type = "pci";
151	assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
152	reg = <0x1800 0 0 0 0>;
153	#address-cells = <3>;
154	#size-cells = <2>;
155	#interrupt-cells = <1>;
156	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
157	0x81000000 0 0 0x81000000 0x3 0 1 0>;
158	interrupt-map-mask = <0 0 0 0>;
159	interrupt-map = <0 0 0 0 &mpic 60>;
160	marvell,pcie-port = <0>;
161	marvell,pcie-lane = <2>;
162	clocks = <&gateclk 7>;
163	status = "disabled";
164	};
165
166	pcie@4,0 {
167	device_type = "pci";
168	assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
169	reg = <0x2000 0 0 0 0>;
170	#address-cells = <3>;
171	#size-cells = <2>;
172	#interrupt-cells = <1>;
173	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
174	0x81000000 0 0 0x81000000 0x4 0 1 0>;
175	interrupt-map-mask = <0 0 0 0>;
176	interrupt-map = <0 0 0 0 &mpic 61>;
177	marvell,pcie-port = <0>;
178	marvell,pcie-lane = <3>;
179	clocks = <&gateclk 8>;
180	status = "disabled";
181	};
182
183	pcie@5,0 {
184	device_type = "pci";
185	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
186	reg = <0x2800 0 0 0 0>;
187	#address-cells = <3>;
188	#size-cells = <2>;
189	#interrupt-cells = <1>;
190	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
191	0x81000000 0 0 0x81000000 0x5 0 1 0>;
192	interrupt-map-mask = <0 0 0 0>;
193	interrupt-map = <0 0 0 0 &mpic 62>;
194	marvell,pcie-port = <1>;
195	marvell,pcie-lane = <0>;
196	clocks = <&gateclk 9>;
197	status = "disabled";
198	};
199
200	pcie@6,0 {
201	device_type = "pci";
202	assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
203	reg = <0x3000 0 0 0 0>;
204	#address-cells = <3>;
205	#size-cells = <2>;
206	#interrupt-cells = <1>;
207	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
208	0x81000000 0 0 0x81000000 0x6 0 1 0>;
209	interrupt-map-mask = <0 0 0 0>;
210	interrupt-map = <0 0 0 0 &mpic 63>;
211	marvell,pcie-port = <1>;
212	marvell,pcie-lane = <1>;
213	clocks = <&gateclk 10>;
214	status = "disabled";
215	};
216
217	pcie@7,0 {
218	device_type = "pci";
219	assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
220	reg = <0x3800 0 0 0 0>;
221	#address-cells = <3>;
222	#size-cells = <2>;
223	#interrupt-cells = <1>;
224	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
225	0x81000000 0 0 0x81000000 0x7 0 1 0>;
226	interrupt-map-mask = <0 0 0 0>;
227	interrupt-map = <0 0 0 0 &mpic 64>;
228	marvell,pcie-port = <1>;
229	marvell,pcie-lane = <2>;
230	clocks = <&gateclk 11>;
231	status = "disabled";
232	};
233
234	pcie@8,0 {
235	device_type = "pci";
236	assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
237	reg = <0x4000 0 0 0 0>;
238	#address-cells = <3>;
239	#size-cells = <2>;
240	#interrupt-cells = <1>;
241	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
242	0x81000000 0 0 0x81000000 0x8 0 1 0>;
243	interrupt-map-mask = <0 0 0 0>;
244	interrupt-map = <0 0 0 0 &mpic 65>;
245	marvell,pcie-port = <1>;
246	marvell,pcie-lane = <3>;
247	clocks = <&gateclk 12>;
248	status = "disabled";
249	};
250
251	pcie@9,0 {
252	device_type = "pci";
253	assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
254	reg = <0x4800 0 0 0 0>;
255	#address-cells = <3>;
256	#size-cells = <2>;
257	#interrupt-cells = <1>;
258	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
259	0x81000000 0 0 0x81000000 0x9 0 1 0>;
260	interrupt-map-mask = <0 0 0 0>;
261	interrupt-map = <0 0 0 0 &mpic 99>;
262	marvell,pcie-port = <2>;
263	marvell,pcie-lane = <0>;
264	clocks = <&gateclk 26>;
265	status = "disabled";
266	};
267
268	pcie@10,0 {
269	device_type = "pci";
270	assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
271	reg = <0x5000 0 0 0 0>;
272	#address-cells = <3>;
273	#size-cells = <2>;
274	#interrupt-cells = <1>;
275	ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
276	0x81000000 0 0 0x81000000 0xa 0 1 0>;
277	interrupt-map-mask = <0 0 0 0>;
278	interrupt-map = <0 0 0 0 &mpic 103>;
279	marvell,pcie-port = <3>;
280	marvell,pcie-lane = <0>;
281	clocks = <&gateclk 27>;
282	status = "disabled";
283	};
284	};
285
467f54b2 GC	286	internal-regs {
	287	pinctrl {
	288	compatible = "marvell,mv78460-pinctrl";
	289	reg = <0x18000 0x38>;
6d36e8e0	290
467f54b2 GC	291	sdio_pins: sdio-pins {
	292	marvell,pins = "mpp30", "mpp31", "mpp32",
	293	"mpp33", "mpp34", "mpp35";
	294	marvell,function = "sd0";
	295	};
6d36e8e0	296	};
397d59f3	297
467f54b2 GC	298	gpio0: gpio@18100 {
	299	compatible = "marvell,orion-gpio";
	300	reg = <0x18100 0x40>;
	301	ngpios = <32>;
	302	gpio-controller;
	303	#gpio-cells = <2>;
	304	interrupt-controller;
ca60985c	305	#interrupt-cells = <2>;
467f54b2 GC	306	interrupts = <82>, <83>, <84>, <85>;
467f54b2 GC	307	};
397d59f3	308
467f54b2 GC	309	gpio1: gpio@18140 {
	310	compatible = "marvell,orion-gpio";
	311	reg = <0x18140 0x40>;
	312	ngpios = <32>;
	313	gpio-controller;
	314	#gpio-cells = <2>;
	315	interrupt-controller;
ca60985c	316	#interrupt-cells = <2>;
467f54b2 GC	317	interrupts = <87>, <88>, <89>, <90>;
467f54b2 GC	318	};
397d59f3	319
467f54b2 GC	320	gpio2: gpio@18180 {
	321	compatible = "marvell,orion-gpio";
	322	reg = <0x18180 0x40>;
	323	ngpios = <3>;
	324	gpio-controller;
	325	#gpio-cells = <2>;
	326	interrupt-controller;
ca60985c	327	#interrupt-cells = <2>;
467f54b2 GC	328	interrupts = <91>;
467f54b2 GC	329	};
77916519	330
be5a9389	331	eth3: ethernet@34000 {
77916519	332	compatible = "marvell,armada-370-neta";
cf8088c5	333	reg = <0x34000 0x4000>;
77916519 TP	334	interrupts = <14>;
	335	clocks = <&gateclk 1>;
	336	status = "disabled";
467f54b2	337	};
9d8f44f0	338	};
f3b42b7c	339	};
1b2529d0	340	};