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49fe2ba3 NF |
1 | /* |
2 | * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC | |
3 | * applies to AT91SAM9G45, AT91SAM9M10, | |
4 | * AT91SAM9G46, AT91SAM9M11 SoC | |
5 | * | |
6 | * Copyright (C) 2011 Atmel, | |
7 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> | |
8 | * | |
9 | * Licensed under GPLv2 or later. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Atmel AT91SAM9G45 family SoC"; | |
16 | compatible = "atmel,at91sam9g45"; | |
17 | interrupt-parent = <&aic>; | |
18 | ||
19 | aliases { | |
20 | serial0 = &dbgu; | |
21 | serial1 = &usart0; | |
22 | serial2 = &usart1; | |
23 | serial3 = &usart2; | |
24 | serial4 = &usart3; | |
21f81872 NF |
25 | gpio0 = &pioA; |
26 | gpio1 = &pioB; | |
27 | gpio2 = &pioC; | |
28 | gpio3 = &pioD; | |
29 | gpio4 = &pioE; | |
3a61a5da NF |
30 | tcb0 = &tcb0; |
31 | tcb1 = &tcb1; | |
05dcd361 LD |
32 | i2c0 = &i2c0; |
33 | i2c1 = &i2c1; | |
49fe2ba3 NF |
34 | }; |
35 | cpus { | |
36 | cpu@0 { | |
37 | compatible = "arm,arm926ejs"; | |
38 | }; | |
39 | }; | |
40 | ||
dcce6ce8 | 41 | memory { |
49fe2ba3 NF |
42 | reg = <0x70000000 0x10000000>; |
43 | }; | |
44 | ||
45 | ahb { | |
46 | compatible = "simple-bus"; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | ranges; | |
50 | ||
51 | apb { | |
52 | compatible = "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
55 | ranges; | |
56 | ||
57 | aic: interrupt-controller@fffff000 { | |
f8a073ee | 58 | #interrupt-cells = <3>; |
49fe2ba3 NF |
59 | compatible = "atmel,at91rm9200-aic"; |
60 | interrupt-controller; | |
49fe2ba3 | 61 | reg = <0xfffff000 0x200>; |
c6573943 | 62 | atmel,external-irqs = <31>; |
49fe2ba3 NF |
63 | }; |
64 | ||
a7776ec6 JCPV |
65 | ramc0: ramc@ffffe400 { |
66 | compatible = "atmel,at91sam9g45-ddramc"; | |
67 | reg = <0xffffe400 0x200 | |
68 | 0xffffe600 0x200>; | |
69 | }; | |
70 | ||
eb5e76ff JCPV |
71 | pmc: pmc@fffffc00 { |
72 | compatible = "atmel,at91rm9200-pmc"; | |
73 | reg = <0xfffffc00 0x100>; | |
74 | }; | |
75 | ||
c8082d34 JCPV |
76 | rstc@fffffd00 { |
77 | compatible = "atmel,at91sam9g45-rstc"; | |
78 | reg = <0xfffffd00 0x10>; | |
79 | }; | |
80 | ||
23fa648f JCPV |
81 | pit: timer@fffffd30 { |
82 | compatible = "atmel,at91sam9260-pit"; | |
83 | reg = <0xfffffd30 0xf>; | |
f8a073ee | 84 | interrupts = <1 4 7>; |
23fa648f JCPV |
85 | }; |
86 | ||
3a61a5da | 87 | |
82015c4e JCPV |
88 | shdwc@fffffd10 { |
89 | compatible = "atmel,at91sam9rl-shdwc"; | |
90 | reg = <0xfffffd10 0x10>; | |
91 | }; | |
92 | ||
3a61a5da NF |
93 | tcb0: timer@fff7c000 { |
94 | compatible = "atmel,at91rm9200-tcb"; | |
95 | reg = <0xfff7c000 0x100>; | |
f8a073ee | 96 | interrupts = <18 4 0>; |
3a61a5da NF |
97 | }; |
98 | ||
99 | tcb1: timer@fffd4000 { | |
100 | compatible = "atmel,at91rm9200-tcb"; | |
101 | reg = <0xfffd4000 0x100>; | |
f8a073ee | 102 | interrupts = <18 4 0>; |
3a61a5da NF |
103 | }; |
104 | ||
49fe2ba3 NF |
105 | dma: dma-controller@ffffec00 { |
106 | compatible = "atmel,at91sam9g45-dma"; | |
107 | reg = <0xffffec00 0x200>; | |
f8a073ee | 108 | interrupts = <21 4 0>; |
49fe2ba3 NF |
109 | }; |
110 | ||
e4541ff2 JCPV |
111 | pinctrl@fffff200 { |
112 | #address-cells = <1>; | |
113 | #size-cells = <1>; | |
114 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; | |
115 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
116 | ||
5314ec8e JCPV |
117 | atmel,mux-mask = < |
118 | /* A B */ | |
119 | 0xffffffff 0xffc003ff /* pioA */ | |
120 | 0xffffffff 0x800f8f00 /* pioB */ | |
121 | 0xffffffff 0x00000e00 /* pioC */ | |
122 | 0xffffffff 0xff0c1381 /* pioD */ | |
123 | 0xffffffff 0x81ffff81 /* pioE */ | |
124 | >; | |
125 | ||
126 | /* shared pinctrl settings */ | |
ec6754a7 JCPV |
127 | dbgu { |
128 | pinctrl_dbgu: dbgu-0 { | |
129 | atmel,pins = | |
130 | <1 12 0x1 0x0 /* PB12 periph A */ | |
131 | 1 13 0x1 0x0>; /* PB13 periph A */ | |
132 | }; | |
133 | }; | |
134 | ||
135 | uart0 { | |
136 | pinctrl_uart0: uart0-0 { | |
137 | atmel,pins = | |
138 | <1 19 0x1 0x1 /* PB19 periph A with pullup */ | |
139 | 1 18 0x1 0x0>; /* PB18 periph A */ | |
140 | }; | |
141 | ||
142 | pinctrl_uart0_rts_cts: uart0_rts_cts-0 { | |
143 | atmel,pins = | |
144 | <1 17 0x2 0x0 /* PB17 periph B */ | |
145 | 1 15 0x2 0x0>; /* PB15 periph B */ | |
146 | }; | |
147 | }; | |
148 | ||
149 | uart1 { | |
150 | pinctrl_uart1: uart1-0 { | |
151 | atmel,pins = | |
152 | <1 4 0x1 0x1 /* PB4 periph A with pullup */ | |
153 | 1 5 0x1 0x0>; /* PB5 periph A */ | |
154 | }; | |
155 | ||
156 | pinctrl_uart1_rts_cts: uart1_rts_cts-0 { | |
157 | atmel,pins = | |
158 | <3 16 0x1 0x0 /* PD16 periph A */ | |
159 | 3 17 0x1 0x0>; /* PD17 periph A */ | |
160 | }; | |
161 | }; | |
162 | ||
163 | uart2 { | |
164 | pinctrl_uart2: uart2-0 { | |
165 | atmel,pins = | |
166 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ | |
167 | 1 7 0x1 0x0>; /* PB7 periph A */ | |
168 | }; | |
169 | ||
170 | pinctrl_uart2_rts_cts: uart2_rts_cts-0 { | |
171 | atmel,pins = | |
172 | <2 9 0x2 0x0 /* PC9 periph B */ | |
173 | 2 11 0x2 0x0>; /* PC11 periph B */ | |
174 | }; | |
175 | }; | |
176 | ||
177 | uart3 { | |
178 | pinctrl_uart3: uart3-0 { | |
179 | atmel,pins = | |
180 | <1 8 0x1 0x1 /* PB9 periph A with pullup */ | |
181 | 1 9 0x1 0x0>; /* PB8 periph A */ | |
182 | }; | |
183 | ||
184 | pinctrl_uart3_rts_cts: uart3_rts_cts-0 { | |
185 | atmel,pins = | |
186 | <0 23 0x2 0x0 /* PA23 periph B */ | |
187 | 0 24 0x2 0x0>; /* PA24 periph B */ | |
188 | }; | |
189 | }; | |
5314ec8e | 190 | |
e4541ff2 JCPV |
191 | pioA: gpio@fffff200 { |
192 | compatible = "atmel,at91rm9200-gpio"; | |
193 | reg = <0xfffff200 0x200>; | |
194 | interrupts = <2 4 1>; | |
195 | #gpio-cells = <2>; | |
196 | gpio-controller; | |
197 | interrupt-controller; | |
198 | #interrupt-cells = <2>; | |
199 | }; | |
200 | ||
201 | pioB: gpio@fffff400 { | |
202 | compatible = "atmel,at91rm9200-gpio"; | |
203 | reg = <0xfffff400 0x200>; | |
204 | interrupts = <3 4 1>; | |
205 | #gpio-cells = <2>; | |
206 | gpio-controller; | |
207 | interrupt-controller; | |
208 | #interrupt-cells = <2>; | |
209 | }; | |
210 | ||
211 | pioC: gpio@fffff600 { | |
212 | compatible = "atmel,at91rm9200-gpio"; | |
213 | reg = <0xfffff600 0x200>; | |
214 | interrupts = <4 4 1>; | |
215 | #gpio-cells = <2>; | |
216 | gpio-controller; | |
217 | interrupt-controller; | |
218 | #interrupt-cells = <2>; | |
219 | }; | |
220 | ||
221 | pioD: gpio@fffff800 { | |
222 | compatible = "atmel,at91rm9200-gpio"; | |
223 | reg = <0xfffff800 0x200>; | |
224 | interrupts = <5 4 1>; | |
225 | #gpio-cells = <2>; | |
226 | gpio-controller; | |
227 | interrupt-controller; | |
228 | #interrupt-cells = <2>; | |
229 | }; | |
230 | ||
231 | pioE: gpio@fffffa00 { | |
232 | compatible = "atmel,at91rm9200-gpio"; | |
233 | reg = <0xfffffa00 0x200>; | |
234 | interrupts = <5 4 1>; | |
235 | #gpio-cells = <2>; | |
236 | gpio-controller; | |
237 | interrupt-controller; | |
238 | #interrupt-cells = <2>; | |
239 | }; | |
21f81872 NF |
240 | }; |
241 | ||
49fe2ba3 NF |
242 | dbgu: serial@ffffee00 { |
243 | compatible = "atmel,at91sam9260-usart"; | |
244 | reg = <0xffffee00 0x200>; | |
f8a073ee | 245 | interrupts = <1 4 7>; |
ec6754a7 JCPV |
246 | pinctrl-names = "default"; |
247 | pinctrl-0 = <&pinctrl_dbgu>; | |
49fe2ba3 NF |
248 | status = "disabled"; |
249 | }; | |
250 | ||
251 | usart0: serial@fff8c000 { | |
252 | compatible = "atmel,at91sam9260-usart"; | |
253 | reg = <0xfff8c000 0x200>; | |
f8a073ee | 254 | interrupts = <7 4 5>; |
49fe2ba3 NF |
255 | atmel,use-dma-rx; |
256 | atmel,use-dma-tx; | |
ec6754a7 JCPV |
257 | pinctrl-names = "default"; |
258 | pinctrl-0 = <&pinctrl_uart0>; | |
49fe2ba3 NF |
259 | status = "disabled"; |
260 | }; | |
261 | ||
262 | usart1: serial@fff90000 { | |
263 | compatible = "atmel,at91sam9260-usart"; | |
264 | reg = <0xfff90000 0x200>; | |
f8a073ee | 265 | interrupts = <8 4 5>; |
49fe2ba3 NF |
266 | atmel,use-dma-rx; |
267 | atmel,use-dma-tx; | |
ec6754a7 JCPV |
268 | pinctrl-names = "default"; |
269 | pinctrl-0 = <&pinctrl_uart1>; | |
49fe2ba3 NF |
270 | status = "disabled"; |
271 | }; | |
272 | ||
273 | usart2: serial@fff94000 { | |
274 | compatible = "atmel,at91sam9260-usart"; | |
275 | reg = <0xfff94000 0x200>; | |
f8a073ee | 276 | interrupts = <9 4 5>; |
49fe2ba3 NF |
277 | atmel,use-dma-rx; |
278 | atmel,use-dma-tx; | |
ec6754a7 JCPV |
279 | pinctrl-names = "default"; |
280 | pinctrl-0 = <&pinctrl_uart2>; | |
49fe2ba3 NF |
281 | status = "disabled"; |
282 | }; | |
283 | ||
284 | usart3: serial@fff98000 { | |
285 | compatible = "atmel,at91sam9260-usart"; | |
286 | reg = <0xfff98000 0x200>; | |
f8a073ee | 287 | interrupts = <10 4 5>; |
49fe2ba3 NF |
288 | atmel,use-dma-rx; |
289 | atmel,use-dma-tx; | |
ec6754a7 JCPV |
290 | pinctrl-names = "default"; |
291 | pinctrl-0 = <&pinctrl_uart3>; | |
49fe2ba3 NF |
292 | status = "disabled"; |
293 | }; | |
0d4f99d8 NF |
294 | |
295 | macb0: ethernet@fffbc000 { | |
296 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
297 | reg = <0xfffbc000 0x100>; | |
f8a073ee | 298 | interrupts = <25 4 3>; |
0d4f99d8 NF |
299 | status = "disabled"; |
300 | }; | |
93b298ba | 301 | |
05dcd361 LD |
302 | i2c0: i2c@fff84000 { |
303 | compatible = "atmel,at91sam9g10-i2c"; | |
304 | reg = <0xfff84000 0x100>; | |
305 | interrupts = <12 4 6>; | |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | i2c1: i2c@fff88000 { | |
312 | compatible = "atmel,at91sam9g10-i2c"; | |
313 | reg = <0xfff88000 0x100>; | |
314 | interrupts = <13 4 6>; | |
315 | #address-cells = <1>; | |
316 | #size-cells = <0>; | |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
93b298ba MR |
320 | adc0: adc@fffb0000 { |
321 | compatible = "atmel,at91sam9260-adc"; | |
322 | reg = <0xfffb0000 0x100>; | |
f8a073ee | 323 | interrupts = <20 4 0>; |
93b298ba MR |
324 | atmel,adc-use-external-triggers; |
325 | atmel,adc-channels-used = <0xff>; | |
326 | atmel,adc-vref = <3300>; | |
327 | atmel,adc-num-channels = <8>; | |
328 | atmel,adc-startup-time = <40>; | |
329 | atmel,adc-channel-base = <0x30>; | |
330 | atmel,adc-drdy-mask = <0x10000>; | |
331 | atmel,adc-status-register = <0x1c>; | |
332 | atmel,adc-trigger-register = <0x08>; | |
333 | ||
334 | trigger@0 { | |
335 | trigger-name = "external-rising"; | |
336 | trigger-value = <0x1>; | |
337 | trigger-external; | |
338 | }; | |
339 | trigger@1 { | |
340 | trigger-name = "external-falling"; | |
341 | trigger-value = <0x2>; | |
342 | trigger-external; | |
343 | }; | |
344 | ||
345 | trigger@2 { | |
346 | trigger-name = "external-any"; | |
347 | trigger-value = <0x3>; | |
348 | trigger-external; | |
349 | }; | |
350 | ||
351 | trigger@3 { | |
352 | trigger-name = "continuous"; | |
353 | trigger-value = <0x6>; | |
354 | }; | |
355 | }; | |
49fe2ba3 | 356 | }; |
d6a01661 JCPV |
357 | |
358 | nand0: nand@40000000 { | |
359 | compatible = "atmel,at91rm9200-nand"; | |
360 | #address-cells = <1>; | |
361 | #size-cells = <1>; | |
362 | reg = <0x40000000 0x10000000 | |
363 | 0xffffe200 0x200 | |
364 | >; | |
365 | atmel,nand-addr-offset = <21>; | |
366 | atmel,nand-cmd-offset = <22>; | |
367 | gpios = <&pioC 8 0 | |
368 | &pioC 14 0 | |
369 | 0 | |
370 | >; | |
371 | status = "disabled"; | |
372 | }; | |
6a062459 JCPV |
373 | |
374 | usb0: ohci@00700000 { | |
375 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
376 | reg = <0x00700000 0x100000>; | |
f8a073ee | 377 | interrupts = <22 4 2>; |
6a062459 JCPV |
378 | status = "disabled"; |
379 | }; | |
62c5553a JCPV |
380 | |
381 | usb1: ehci@00800000 { | |
382 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
383 | reg = <0x00800000 0x100000>; | |
f8a073ee | 384 | interrupts = <22 4 2>; |
62c5553a JCPV |
385 | status = "disabled"; |
386 | }; | |
49fe2ba3 | 387 | }; |
8f24bdaa JCPV |
388 | |
389 | i2c@0 { | |
390 | compatible = "i2c-gpio"; | |
391 | gpios = <&pioA 20 0 /* sda */ | |
392 | &pioA 21 0 /* scl */ | |
393 | >; | |
394 | i2c-gpio,sda-open-drain; | |
395 | i2c-gpio,scl-open-drain; | |
396 | i2c-gpio,delay-us = <5>; /* ~100 kHz */ | |
397 | #address-cells = <1>; | |
398 | #size-cells = <0>; | |
399 | status = "disabled"; | |
400 | }; | |
49fe2ba3 | 401 | }; |