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467f1cf5 NF |
1 | /* |
2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC | |
3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, | |
4 | * AT91SAM9X25, AT91SAM9X35 SoC | |
5 | * | |
6 | * Copyright (C) 2012 Atmel, | |
7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | |
8 | * | |
9 | * Licensed under GPLv2 or later. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Atmel AT91SAM9x5 family SoC"; | |
16 | compatible = "atmel,at91sam9x5"; | |
17 | interrupt-parent = <&aic>; | |
18 | ||
19 | aliases { | |
20 | serial0 = &dbgu; | |
21 | serial1 = &usart0; | |
22 | serial2 = &usart1; | |
23 | serial3 = &usart2; | |
24 | gpio0 = &pioA; | |
25 | gpio1 = &pioB; | |
26 | gpio2 = &pioC; | |
27 | gpio3 = &pioD; | |
28 | tcb0 = &tcb0; | |
29 | tcb1 = &tcb1; | |
05dcd361 LD |
30 | i2c0 = &i2c0; |
31 | i2c1 = &i2c1; | |
32 | i2c2 = &i2c2; | |
099343c6 | 33 | ssc0 = &ssc0; |
467f1cf5 NF |
34 | }; |
35 | cpus { | |
36 | cpu@0 { | |
37 | compatible = "arm,arm926ejs"; | |
38 | }; | |
39 | }; | |
40 | ||
dcce6ce8 | 41 | memory { |
467f1cf5 NF |
42 | reg = <0x20000000 0x10000000>; |
43 | }; | |
44 | ||
45 | ahb { | |
46 | compatible = "simple-bus"; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | ranges; | |
50 | ||
51 | apb { | |
52 | compatible = "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
55 | ranges; | |
56 | ||
57 | aic: interrupt-controller@fffff000 { | |
f8a073ee | 58 | #interrupt-cells = <3>; |
467f1cf5 NF |
59 | compatible = "atmel,at91rm9200-aic"; |
60 | interrupt-controller; | |
467f1cf5 | 61 | reg = <0xfffff000 0x200>; |
c6573943 | 62 | atmel,external-irqs = <31>; |
467f1cf5 NF |
63 | }; |
64 | ||
a7776ec6 JCPV |
65 | ramc0: ramc@ffffe800 { |
66 | compatible = "atmel,at91sam9g45-ddramc"; | |
67 | reg = <0xffffe800 0x200>; | |
68 | }; | |
69 | ||
eb5e76ff JCPV |
70 | pmc: pmc@fffffc00 { |
71 | compatible = "atmel,at91rm9200-pmc"; | |
72 | reg = <0xfffffc00 0x100>; | |
73 | }; | |
74 | ||
c8082d34 JCPV |
75 | rstc@fffffe00 { |
76 | compatible = "atmel,at91sam9g45-rstc"; | |
77 | reg = <0xfffffe00 0x10>; | |
78 | }; | |
79 | ||
82015c4e JCPV |
80 | shdwc@fffffe10 { |
81 | compatible = "atmel,at91sam9x5-shdwc"; | |
82 | reg = <0xfffffe10 0x10>; | |
83 | }; | |
84 | ||
467f1cf5 NF |
85 | pit: timer@fffffe30 { |
86 | compatible = "atmel,at91sam9260-pit"; | |
87 | reg = <0xfffffe30 0xf>; | |
f8a073ee | 88 | interrupts = <1 4 7>; |
467f1cf5 NF |
89 | }; |
90 | ||
91 | tcb0: timer@f8008000 { | |
92 | compatible = "atmel,at91sam9x5-tcb"; | |
93 | reg = <0xf8008000 0x100>; | |
f8a073ee | 94 | interrupts = <17 4 0>; |
467f1cf5 NF |
95 | }; |
96 | ||
97 | tcb1: timer@f800c000 { | |
98 | compatible = "atmel,at91sam9x5-tcb"; | |
99 | reg = <0xf800c000 0x100>; | |
f8a073ee | 100 | interrupts = <17 4 0>; |
467f1cf5 NF |
101 | }; |
102 | ||
103 | dma0: dma-controller@ffffec00 { | |
104 | compatible = "atmel,at91sam9g45-dma"; | |
105 | reg = <0xffffec00 0x200>; | |
f8a073ee | 106 | interrupts = <20 4 0>; |
980ce7d9 | 107 | #dma-cells = <2>; |
467f1cf5 NF |
108 | }; |
109 | ||
110 | dma1: dma-controller@ffffee00 { | |
111 | compatible = "atmel,at91sam9g45-dma"; | |
112 | reg = <0xffffee00 0x200>; | |
f8a073ee | 113 | interrupts = <21 4 0>; |
980ce7d9 | 114 | #dma-cells = <2>; |
467f1cf5 NF |
115 | }; |
116 | ||
ec6754a7 | 117 | pinctrl@fffff400 { |
e4541ff2 JCPV |
118 | #address-cells = <1>; |
119 | #size-cells = <1>; | |
5314ec8e | 120 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
e4541ff2 JCPV |
121 | ranges = <0xfffff400 0xfffff400 0x800>; |
122 | ||
5314ec8e | 123 | /* shared pinctrl settings */ |
ec6754a7 JCPV |
124 | dbgu { |
125 | pinctrl_dbgu: dbgu-0 { | |
126 | atmel,pins = | |
127 | <0 9 0x1 0x0 /* PA9 periph A */ | |
128 | 0 10 0x1 0x1>; /* PA10 periph A with pullup */ | |
129 | }; | |
130 | }; | |
131 | ||
9e3129e9 JCPV |
132 | usart0 { |
133 | pinctrl_usart0: usart0-0 { | |
ec6754a7 JCPV |
134 | atmel,pins = |
135 | <0 0 0x1 0x1 /* PA0 periph A with pullup */ | |
136 | 0 1 0x1 0x0>; /* PA1 periph A */ | |
137 | }; | |
138 | ||
c58c0c5a | 139 | pinctrl_usart0_rts: usart0_rts-0 { |
ec6754a7 | 140 | atmel,pins = |
c58c0c5a JCPV |
141 | <0 2 0x1 0x0>; /* PA2 periph A */ |
142 | }; | |
143 | ||
144 | pinctrl_usart0_cts: usart0_cts-0 { | |
145 | atmel,pins = | |
146 | <0 3 0x1 0x0>; /* PA3 periph A */ | |
ec6754a7 | 147 | }; |
1bab02ec RG |
148 | |
149 | pinctrl_usart0_sck: usart0_sck-0 { | |
150 | atmel,pins = | |
151 | <0 4 0x1 0x0>; /* PA4 periph A */ | |
152 | }; | |
ec6754a7 JCPV |
153 | }; |
154 | ||
9e3129e9 JCPV |
155 | usart1 { |
156 | pinctrl_usart1: usart1-0 { | |
ec6754a7 JCPV |
157 | atmel,pins = |
158 | <0 5 0x1 0x1 /* PA5 periph A with pullup */ | |
159 | 0 6 0x1 0x0>; /* PA6 periph A */ | |
160 | }; | |
161 | ||
c58c0c5a JCPV |
162 | pinctrl_usart1_rts: usart1_rts-0 { |
163 | atmel,pins = | |
c89cec3a | 164 | <2 27 0x3 0x0>; /* PC27 periph C */ |
c58c0c5a JCPV |
165 | }; |
166 | ||
167 | pinctrl_usart1_cts: usart1_cts-0 { | |
ec6754a7 | 168 | atmel,pins = |
c89cec3a | 169 | <2 28 0x3 0x0>; /* PC28 periph C */ |
ec6754a7 | 170 | }; |
1bab02ec RG |
171 | |
172 | pinctrl_usart1_sck: usart1_sck-0 { | |
173 | atmel,pins = | |
174 | <2 28 0x3 0x0>; /* PC29 periph C */ | |
175 | }; | |
ec6754a7 JCPV |
176 | }; |
177 | ||
9e3129e9 JCPV |
178 | usart2 { |
179 | pinctrl_usart2: usart2-0 { | |
ec6754a7 JCPV |
180 | atmel,pins = |
181 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | |
182 | 0 8 0x1 0x0>; /* PA8 periph A */ | |
183 | }; | |
184 | ||
c58c0c5a | 185 | pinctrl_uart2_rts: uart2_rts-0 { |
ec6754a7 | 186 | atmel,pins = |
c89cec3a | 187 | <1 0 0x2 0x0>; /* PB0 periph B */ |
c58c0c5a JCPV |
188 | }; |
189 | ||
190 | pinctrl_uart2_cts: uart2_cts-0 { | |
191 | atmel,pins = | |
c89cec3a | 192 | <1 1 0x2 0x0>; /* PB1 periph B */ |
ec6754a7 | 193 | }; |
1bab02ec RG |
194 | |
195 | pinctrl_usart2_sck: usart2_sck-0 { | |
196 | atmel,pins = | |
197 | <1 2 0x2 0x0>; /* PB2 periph B */ | |
198 | }; | |
ec6754a7 JCPV |
199 | }; |
200 | ||
9e3129e9 | 201 | usart3 { |
65a0fe04 | 202 | pinctrl_usart3: usart3-0 { |
ec6754a7 | 203 | atmel,pins = |
7d4cfece | 204 | <2 22 0x2 0x1 /* PC22 periph B with pullup */ |
c89cec3a | 205 | 2 23 0x2 0x0>; /* PC23 periph B */ |
ec6754a7 JCPV |
206 | }; |
207 | ||
c58c0c5a JCPV |
208 | pinctrl_usart3_rts: usart3_rts-0 { |
209 | atmel,pins = | |
c89cec3a | 210 | <2 24 0x2 0x0>; /* PC24 periph B */ |
c58c0c5a JCPV |
211 | }; |
212 | ||
213 | pinctrl_usart3_cts: usart3_cts-0 { | |
ec6754a7 | 214 | atmel,pins = |
c89cec3a | 215 | <2 25 0x2 0x0>; /* PC25 periph B */ |
ec6754a7 | 216 | }; |
1bab02ec RG |
217 | |
218 | pinctrl_usart3_sck: usart3_sck-0 { | |
219 | atmel,pins = | |
220 | <2 26 0x2 0x0>; /* PC26 periph B */ | |
221 | }; | |
ec6754a7 JCPV |
222 | }; |
223 | ||
9e3129e9 JCPV |
224 | uart0 { |
225 | pinctrl_uart0: uart0-0 { | |
ec6754a7 | 226 | atmel,pins = |
c89cec3a RG |
227 | <2 8 0x3 0x0 /* PC8 periph C */ |
228 | 2 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
ec6754a7 JCPV |
229 | }; |
230 | }; | |
231 | ||
9e3129e9 JCPV |
232 | uart1 { |
233 | pinctrl_uart1: uart1-0 { | |
ec6754a7 | 234 | atmel,pins = |
c89cec3a RG |
235 | <2 16 0x3 0x0 /* PC16 periph C */ |
236 | 2 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
ec6754a7 JCPV |
237 | }; |
238 | }; | |
5314ec8e | 239 | |
7a38d450 JCPV |
240 | nand { |
241 | pinctrl_nand: nand-0 { | |
242 | atmel,pins = | |
243 | <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */ | |
244 | 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */ | |
245 | }; | |
246 | }; | |
247 | ||
d9b4fe83 JCPV |
248 | macb0 { |
249 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
250 | atmel,pins = | |
251 | <1 0 0x1 0x0 /* PB0 periph A */ | |
252 | 1 1 0x1 0x0 /* PB1 periph A */ | |
253 | 1 2 0x1 0x0 /* PB2 periph A */ | |
254 | 1 3 0x1 0x0 /* PB3 periph A */ | |
255 | 1 4 0x1 0x0 /* PB4 periph A */ | |
256 | 1 5 0x1 0x0 /* PB5 periph A */ | |
257 | 1 6 0x1 0x0 /* PB6 periph A */ | |
258 | 1 7 0x1 0x0 /* PB7 periph A */ | |
259 | 1 9 0x1 0x0 /* PB9 periph A */ | |
260 | 1 10 0x1 0x0>; /* PB10 periph A */ | |
261 | }; | |
262 | ||
263 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { | |
264 | atmel,pins = | |
8461c2f6 DG |
265 | <1 8 0x1 0x0 /* PB8 periph A */ |
266 | 1 11 0x1 0x0 /* PB11 periph A */ | |
267 | 1 12 0x1 0x0 /* PB12 periph A */ | |
268 | 1 13 0x1 0x0 /* PB13 periph A */ | |
269 | 1 14 0x1 0x0 /* PB14 periph A */ | |
270 | 1 15 0x1 0x0 /* PB15 periph A */ | |
271 | 1 16 0x1 0x0 /* PB16 periph A */ | |
272 | 1 17 0x1 0x0>; /* PB17 periph A */ | |
d9b4fe83 JCPV |
273 | }; |
274 | }; | |
275 | ||
d4fe9ac7 JCPV |
276 | mmc0 { |
277 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
278 | atmel,pins = | |
279 | <0 17 0x1 0x0 /* PA17 periph A */ | |
280 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | |
281 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | |
282 | }; | |
283 | ||
284 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
285 | atmel,pins = | |
286 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | |
287 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | |
288 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | |
289 | }; | |
290 | }; | |
291 | ||
292 | mmc1 { | |
293 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | |
294 | atmel,pins = | |
295 | <0 13 0x2 0x0 /* PA13 periph B */ | |
296 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | |
297 | 0 11 0x2 0x1>; /* PA11 periph B with pullup */ | |
298 | }; | |
299 | ||
300 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | |
301 | atmel,pins = | |
302 | <0 2 0x2 0x1 /* PA2 periph B with pullup */ | |
303 | 0 3 0x2 0x1 /* PA3 periph B with pullup */ | |
304 | 0 4 0x2 0x1>; /* PA4 periph B with pullup */ | |
305 | }; | |
306 | }; | |
307 | ||
544ae6b2 BS |
308 | ssc0 { |
309 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
310 | atmel,pins = | |
311 | <0 24 0x2 0x0 /* PA24 periph B */ | |
312 | 0 25 0x2 0x0 /* PA25 periph B */ | |
313 | 0 26 0x2 0x0>; /* PA26 periph B */ | |
314 | }; | |
315 | ||
316 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
317 | atmel,pins = | |
318 | <0 27 0x2 0x0 /* PA27 periph B */ | |
319 | 0 28 0x2 0x0 /* PA28 periph B */ | |
320 | 0 29 0x2 0x0>; /* PA29 periph B */ | |
321 | }; | |
322 | }; | |
323 | ||
e4541ff2 JCPV |
324 | pioA: gpio@fffff400 { |
325 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
326 | reg = <0xfffff400 0x200>; | |
327 | interrupts = <2 4 1>; | |
328 | #gpio-cells = <2>; | |
329 | gpio-controller; | |
330 | interrupt-controller; | |
331 | #interrupt-cells = <2>; | |
332 | }; | |
333 | ||
334 | pioB: gpio@fffff600 { | |
335 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
336 | reg = <0xfffff600 0x200>; | |
337 | interrupts = <2 4 1>; | |
338 | #gpio-cells = <2>; | |
339 | gpio-controller; | |
fc33ff43 | 340 | #gpio-lines = <19>; |
e4541ff2 JCPV |
341 | interrupt-controller; |
342 | #interrupt-cells = <2>; | |
343 | }; | |
344 | ||
345 | pioC: gpio@fffff800 { | |
346 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
347 | reg = <0xfffff800 0x200>; | |
348 | interrupts = <3 4 1>; | |
349 | #gpio-cells = <2>; | |
350 | gpio-controller; | |
351 | interrupt-controller; | |
352 | #interrupt-cells = <2>; | |
353 | }; | |
354 | ||
355 | pioD: gpio@fffffa00 { | |
356 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
357 | reg = <0xfffffa00 0x200>; | |
358 | interrupts = <3 4 1>; | |
359 | #gpio-cells = <2>; | |
360 | gpio-controller; | |
fc33ff43 | 361 | #gpio-lines = <22>; |
e4541ff2 JCPV |
362 | interrupt-controller; |
363 | #interrupt-cells = <2>; | |
364 | }; | |
467f1cf5 NF |
365 | }; |
366 | ||
544ae6b2 BS |
367 | ssc0: ssc@f0010000 { |
368 | compatible = "atmel,at91sam9g45-ssc"; | |
369 | reg = <0xf0010000 0x4000>; | |
370 | interrupts = <28 4 5>; | |
371 | pinctrl-names = "default"; | |
372 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
373 | status = "disabled"; | |
374 | }; | |
375 | ||
9873137a LD |
376 | mmc0: mmc@f0008000 { |
377 | compatible = "atmel,hsmci"; | |
378 | reg = <0xf0008000 0x600>; | |
379 | interrupts = <12 4 0>; | |
380 | #address-cells = <1>; | |
381 | #size-cells = <0>; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
385 | mmc1: mmc@f000c000 { | |
386 | compatible = "atmel,hsmci"; | |
387 | reg = <0xf000c000 0x600>; | |
388 | interrupts = <26 4 0>; | |
389 | #address-cells = <1>; | |
390 | #size-cells = <0>; | |
391 | status = "disabled"; | |
392 | }; | |
393 | ||
467f1cf5 NF |
394 | dbgu: serial@fffff200 { |
395 | compatible = "atmel,at91sam9260-usart"; | |
396 | reg = <0xfffff200 0x200>; | |
f8a073ee | 397 | interrupts = <1 4 7>; |
ec6754a7 JCPV |
398 | pinctrl-names = "default"; |
399 | pinctrl-0 = <&pinctrl_dbgu>; | |
467f1cf5 NF |
400 | status = "disabled"; |
401 | }; | |
402 | ||
403 | usart0: serial@f801c000 { | |
404 | compatible = "atmel,at91sam9260-usart"; | |
405 | reg = <0xf801c000 0x200>; | |
f8a073ee | 406 | interrupts = <5 4 5>; |
ec6754a7 | 407 | pinctrl-names = "default"; |
9e3129e9 | 408 | pinctrl-0 = <&pinctrl_usart0>; |
467f1cf5 NF |
409 | status = "disabled"; |
410 | }; | |
411 | ||
412 | usart1: serial@f8020000 { | |
413 | compatible = "atmel,at91sam9260-usart"; | |
414 | reg = <0xf8020000 0x200>; | |
f8a073ee | 415 | interrupts = <6 4 5>; |
ec6754a7 | 416 | pinctrl-names = "default"; |
9e3129e9 | 417 | pinctrl-0 = <&pinctrl_usart1>; |
467f1cf5 NF |
418 | status = "disabled"; |
419 | }; | |
420 | ||
421 | usart2: serial@f8024000 { | |
422 | compatible = "atmel,at91sam9260-usart"; | |
423 | reg = <0xf8024000 0x200>; | |
f8a073ee | 424 | interrupts = <7 4 5>; |
ec6754a7 | 425 | pinctrl-names = "default"; |
9e3129e9 | 426 | pinctrl-0 = <&pinctrl_usart2>; |
467f1cf5 NF |
427 | status = "disabled"; |
428 | }; | |
429 | ||
430 | macb0: ethernet@f802c000 { | |
431 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
432 | reg = <0xf802c000 0x100>; | |
f8a073ee | 433 | interrupts = <24 4 3>; |
d9b4fe83 JCPV |
434 | pinctrl-names = "default"; |
435 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
467f1cf5 NF |
436 | status = "disabled"; |
437 | }; | |
438 | ||
439 | macb1: ethernet@f8030000 { | |
440 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
441 | reg = <0xf8030000 0x100>; | |
f8a073ee | 442 | interrupts = <27 4 3>; |
467f1cf5 NF |
443 | status = "disabled"; |
444 | }; | |
d029f371 | 445 | |
05dcd361 LD |
446 | i2c0: i2c@f8010000 { |
447 | compatible = "atmel,at91sam9x5-i2c"; | |
448 | reg = <0xf8010000 0x100>; | |
449 | interrupts = <9 4 6>; | |
d9a63a45 LD |
450 | dmas = <&dma0 1 7>, |
451 | <&dma0 1 8>; | |
452 | dma-names = "tx", "rx"; | |
05dcd361 LD |
453 | #address-cells = <1>; |
454 | #size-cells = <0>; | |
455 | status = "disabled"; | |
456 | }; | |
457 | ||
458 | i2c1: i2c@f8014000 { | |
459 | compatible = "atmel,at91sam9x5-i2c"; | |
460 | reg = <0xf8014000 0x100>; | |
461 | interrupts = <10 4 6>; | |
d9a63a45 LD |
462 | dmas = <&dma1 1 5>, |
463 | <&dma1 1 6>; | |
464 | dma-names = "tx", "rx"; | |
05dcd361 LD |
465 | #address-cells = <1>; |
466 | #size-cells = <0>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | i2c2: i2c@f8018000 { | |
471 | compatible = "atmel,at91sam9x5-i2c"; | |
472 | reg = <0xf8018000 0x100>; | |
473 | interrupts = <11 4 6>; | |
d9a63a45 LD |
474 | dmas = <&dma0 1 9>, |
475 | <&dma0 1 10>; | |
476 | dma-names = "tx", "rx"; | |
05dcd361 LD |
477 | #address-cells = <1>; |
478 | #size-cells = <0>; | |
479 | status = "disabled"; | |
480 | }; | |
481 | ||
d029f371 MR |
482 | adc0: adc@f804c000 { |
483 | compatible = "atmel,at91sam9260-adc"; | |
484 | reg = <0xf804c000 0x100>; | |
f8a073ee | 485 | interrupts = <19 4 0>; |
d029f371 MR |
486 | atmel,adc-use-external; |
487 | atmel,adc-channels-used = <0xffff>; | |
488 | atmel,adc-vref = <3300>; | |
489 | atmel,adc-num-channels = <12>; | |
490 | atmel,adc-startup-time = <40>; | |
491 | atmel,adc-channel-base = <0x50>; | |
492 | atmel,adc-drdy-mask = <0x1000000>; | |
493 | atmel,adc-status-register = <0x30>; | |
494 | atmel,adc-trigger-register = <0xc0>; | |
495 | ||
496 | trigger@0 { | |
497 | trigger-name = "external-rising"; | |
498 | trigger-value = <0x1>; | |
499 | trigger-external; | |
500 | }; | |
501 | ||
502 | trigger@1 { | |
503 | trigger-name = "external-falling"; | |
504 | trigger-value = <0x2>; | |
505 | trigger-external; | |
506 | }; | |
507 | ||
508 | trigger@2 { | |
509 | trigger-name = "external-any"; | |
510 | trigger-value = <0x3>; | |
511 | trigger-external; | |
512 | }; | |
513 | ||
514 | trigger@3 { | |
515 | trigger-name = "continuous"; | |
516 | trigger-value = <0x6>; | |
517 | }; | |
518 | }; | |
467f1cf5 | 519 | }; |
86a89f4f JCPV |
520 | |
521 | nand0: nand@40000000 { | |
522 | compatible = "atmel,at91rm9200-nand"; | |
523 | #address-cells = <1>; | |
524 | #size-cells = <1>; | |
525 | reg = <0x40000000 0x10000000 | |
5314bc2d JW |
526 | 0xffffe000 0x600 /* PMECC Registers */ |
527 | 0xffffe600 0x200 /* PMECC Error Location Registers */ | |
528 | 0x00108000 0x18000 /* PMECC looup table in ROM code */ | |
86a89f4f | 529 | >; |
5314bc2d | 530 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
86a89f4f JCPV |
531 | atmel,nand-addr-offset = <21>; |
532 | atmel,nand-cmd-offset = <22>; | |
7a38d450 JCPV |
533 | pinctrl-names = "default"; |
534 | pinctrl-0 = <&pinctrl_nand>; | |
4352808c NF |
535 | gpios = <&pioD 5 0 |
536 | &pioD 4 0 | |
86a89f4f JCPV |
537 | 0 |
538 | >; | |
539 | status = "disabled"; | |
540 | }; | |
6a062459 JCPV |
541 | |
542 | usb0: ohci@00600000 { | |
543 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
544 | reg = <0x00600000 0x100000>; | |
f8a073ee | 545 | interrupts = <22 4 2>; |
6a062459 JCPV |
546 | status = "disabled"; |
547 | }; | |
62c5553a JCPV |
548 | |
549 | usb1: ehci@00700000 { | |
550 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
551 | reg = <0x00700000 0x100000>; | |
f8a073ee | 552 | interrupts = <22 4 2>; |
62c5553a JCPV |
553 | status = "disabled"; |
554 | }; | |
467f1cf5 | 555 | }; |
10f71c28 JCPV |
556 | |
557 | i2c@0 { | |
558 | compatible = "i2c-gpio"; | |
559 | gpios = <&pioA 30 0 /* sda */ | |
560 | &pioA 31 0 /* scl */ | |
561 | >; | |
562 | i2c-gpio,sda-open-drain; | |
563 | i2c-gpio,scl-open-drain; | |
564 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
565 | #address-cells = <1>; | |
566 | #size-cells = <0>; | |
567 | status = "disabled"; | |
568 | }; | |
569 | ||
570 | i2c@1 { | |
571 | compatible = "i2c-gpio"; | |
572 | gpios = <&pioC 0 0 /* sda */ | |
573 | &pioC 1 0 /* scl */ | |
574 | >; | |
575 | i2c-gpio,sda-open-drain; | |
576 | i2c-gpio,scl-open-drain; | |
577 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
578 | #address-cells = <1>; | |
579 | #size-cells = <0>; | |
580 | status = "disabled"; | |
581 | }; | |
582 | ||
583 | i2c@2 { | |
584 | compatible = "i2c-gpio"; | |
585 | gpios = <&pioB 4 0 /* sda */ | |
586 | &pioB 5 0 /* scl */ | |
587 | >; | |
588 | i2c-gpio,sda-open-drain; | |
589 | i2c-gpio,scl-open-drain; | |
590 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
591 | #address-cells = <1>; | |
592 | #size-cells = <0>; | |
593 | status = "disabled"; | |
594 | }; | |
467f1cf5 | 595 | }; |