projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fa2f9af BS |
1 | /* |
| 2 | * DTS file for CSR SiRFatlas6 Evaluation Board | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | /dts-v1/; | |
| 10 | ||
| 11 | /include/ "atlas6.dtsi" | |
| 12 | ||
| 13 | / { | |
| 14 | model = "CSR SiRFatlas6 Evaluation Board"; | |
| 15 | compatible = "sirf,atlas6-cb", "sirf,atlas6"; | |
| 16 | ||
| 17 | memory { | |
| 18 | reg = <0x00000000 0x20000000>; | |
| 19 | }; | |
| 20 | ||
| 21 | axi { | |
| 22 | peri-iobg { | |
| 23 | uart@b0060000 { | |
| 24 | pinctrl-names = "default"; | |
| 25 | pinctrl-0 = <&uart1_pins_a>; | |
| 26 | }; | |
| 27 | spi@b00d0000 { | |
| 28 | status = "okay"; | |
| 29 | pinctrl-names = "default"; | |
| 30 | pinctrl-0 = <&spi0_pins_a>; | |
| 31 | spi@0 { | |
| 32 | compatible = "spidev"; | |
| 33 | reg = <0>; | |
| 34 | spi-max-frequency = <1000000>; | |
| 35 | }; | |
| 36 | }; | |
| 37 | spi@b0170000 { | |
| 38 | pinctrl-names = "default"; | |
| 39 | pinctrl-0 = <&spi1_pins_a>; | |
| 40 | }; | |
| 41 | i2c0: i2c@b00e0000 { | |
| 42 | status = "okay"; | |
| 43 | pinctrl-names = "default"; | |
| 44 | pinctrl-0 = <&i2c0_pins_a>; | |
| 45 | lcd@40 { | |
| 46 | compatible = "sirf,lcd"; | |
| 47 | reg = <0x40>; | |
| 48 | }; | |
| 49 | }; | |
| 50 | ||
| 51 | }; | |
| 52 | disp-iobg { | |
| 53 | lcd@90010000 { | |
| 54 | status = "okay"; | |
| 55 | pinctrl-names = "default"; | |
| 56 | pinctrl-0 = <&lcd_24pins_a>; | |
| 57 | }; | |
| 58 | }; | |
| 59 | }; | |
| 60 | display: display@0 { | |
| 61 | panels { | |
| 62 | panel0: panel@0 { | |
| 63 | panel-name = "Innolux TFT"; | |
| 64 | hactive = <800>; | |
| 65 | vactive = <480>; | |
| 66 | left_margin = <20>; | |
| 67 | right_margin = <234>; | |
| 68 | upper_margin = <3>; | |
| 69 | lower_margin = <41>; | |
| 70 | hsync_len = <3>; | |
| 71 | vsync_len = <2>; | |
| 72 | pixclock = <33264000>; | |
| 73 | sync = <3>; | |
| 74 | timing = <0x88>; | |
| 75 | }; | |
| 76 | }; | |
| 77 | }; | |
| 78 | }; |