[deliverable/linux.git] / arch / arm / boot / dts / bcm5301x.dtsi

/*
 * Broadcom BCM470X / BCM5301X ARM platform code.
 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
 *
 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	chipcommonA {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x00001000>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@0300 {
			compatible = "ns16550";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000000>;
			status = "disabled";
		};

		uart1: serial@0400 {
			compatible = "ns16550";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000000>;
			status = "disabled";
		};
	};

	mpcore {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19020000 0x00003000>;
		#address-cells = <1>;
		#size-cells = <1>;

		scu@0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x0000 0x100>;
		};

		timer@0200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x0200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_periph>;
		};

		local-timer@0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x0600 0x100>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_periph>;
		};

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
			      <0x0100 0x100>;
		};

		L2: cache-controller@2000 {
			compatible = "arm,pl310-cache";
			reg = <0x2000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		/* As long as we do not have a real clock driver us this
		 * fixed clock */
		clk_periph: periph {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000000>;
		};
	};

	axi@18000000 {
		compatible = "brcm,bus-axi";
		reg = <0x18000000 0x1000>;
		ranges = <0x00000000 0x18000000 0x00100000>;
		#address-cells = <1>;
		#size-cells = <1>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0x000fffff 0xffff>;
		interrupt-map = 
			/* ChipCommon */
			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 2.0 Controller */
			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 3.0 Controller */
			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 0 */
			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 1 */
			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 2 */
			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 3 */
			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

			/* NAND Controller */
			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

		chipcommon: chipcommon@0 {
			reg = <0x00000000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
		};
	};
};
Commit	Line	Data
d27509f1 HM	1	/*
	2	* Broadcom BCM470X / BCM5301X ARM platform code.
	3	* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
	4	* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
	5	*
	6	* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
fb026d3d	11	#include <dt-bindings/gpio/gpio.h>
f6f82344	12	#include <dt-bindings/input/input.h>
d27509f1 HM	13	#include <dt-bindings/interrupt-controller/irq.h>
	14	#include <dt-bindings/interrupt-controller/arm-gic.h>
	15	#include "skeleton.dtsi"
	16
	17	/ {
	18	interrupt-parent = <&gic>;
	19
	20	chipcommonA {
	21	compatible = "simple-bus";
	22	ranges = <0x00000000 0x18000000 0x00001000>;
	23	#address-cells = <1>;
	24	#size-cells = <1>;
	25
	26	uart0: serial@0300 {
	27	compatible = "ns16550";
	28	reg = <0x0300 0x100>;
	29	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	30	clock-frequency = <100000000>;
	31	status = "disabled";
	32	};
	33
	34	uart1: serial@0400 {
	35	compatible = "ns16550";
	36	reg = <0x0400 0x100>;
	37	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	38	clock-frequency = <100000000>;
	39	status = "disabled";
	40	};
	41	};
	42
	43	mpcore {
	44	compatible = "simple-bus";
	45	ranges = <0x00000000 0x19020000 0x00003000>;
	46	#address-cells = <1>;
	47	#size-cells = <1>;
	48
	49	scu@0000 {
	50	compatible = "arm,cortex-a9-scu";
	51	reg = <0x0000 0x100>;
	52	};
	53
	54	timer@0200 {
	55	compatible = "arm,cortex-a9-global-timer";
	56	reg = <0x0200 0x100>;
	57	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	58	clocks = <&clk_periph>;
	59	};
	60
	61	local-timer@0600 {
	62	compatible = "arm,cortex-a9-twd-timer";
	63	reg = <0x0600 0x100>;
	64	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	65	clocks = <&clk_periph>;
	66	};
	67
	68	gic: interrupt-controller@1000 {
	69	compatible = "arm,cortex-a9-gic";
	70	#interrupt-cells = <3>;
	71	#address-cells = <0>;
	72	interrupt-controller;
	73	reg = <0x1000 0x1000>,
	74	<0x0100 0x100>;
	75	};
	76
77	L2: cache-controller@2000 {
78	compatible = "arm,pl310-cache";
79	reg = <0x2000 0x1000>;
80	cache-unified;
81	cache-level = <2>;
82	};
83	};
84
85	clocks {
86	#address-cells = <1>;
87	#size-cells = <0>;
88
89	/* As long as we do not have a real clock driver us this
90	* fixed clock */
91	clk_periph: periph {
92	compatible = "fixed-clock";
93	#clock-cells = <0>;
94	clock-frequency = <400000000>;
95	};
96	};
fb026d3d RM	97
	98	axi@18000000 {
	99	compatible = "brcm,bus-axi";
	100	reg = <0x18000000 0x1000>;
	101	ranges = <0x00000000 0x18000000 0x00100000>;
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104
dec37882 HM	105	#interrupt-cells = <1>;
	106	interrupt-map-mask = <0x000fffff 0xffff>;
	107	interrupt-map =
	108	/* ChipCommon */
	109	<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	110
	111	/* USB 2.0 Controller */
	112	<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
	113
	114	/* USB 3.0 Controller */
	115	<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	116
	117	/* Ethernet Controller 0 */
	118	<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	119
	120	/* Ethernet Controller 1 */
	121	<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	122
	123	/* Ethernet Controller 2 */
	124	<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	125
	126	/* Ethernet Controller 3 */
	127	<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
	128
	129	/* NAND Controller */
	130	<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
	131	<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	132	<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
	133	<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	134	<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	135	<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	136	<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	137	<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	138
fb026d3d RM	139	chipcommon: chipcommon@0 {
	140	reg = <0x00000000 0x1000>;
	141
	142	gpio-controller;
	143	#gpio-cells = <2>;
	144	};
	145	};
d27509f1	146	};