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a9092118 SH |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC | |
3 | * | |
4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
5 | * | |
6 | * based on GPL'ed 2.6 kernel sources | |
7 | * (c) Marvell International Ltd. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include "skeleton.dtsi" | |
556f4a33 | 15 | #include <dt-bindings/clock/berlin2.h> |
a9092118 SH |
16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
17 | ||
18 | / { | |
19 | model = "Marvell Armada 1500-mini (BG2CD) SoC"; | |
20 | compatible = "marvell,berlin2cd", "marvell,berlin"; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu@0 { | |
27 | compatible = "arm,cortex-a9"; | |
28 | device_type = "cpu"; | |
29 | next-level-cache = <&l2>; | |
30 | reg = <0>; | |
31 | }; | |
32 | }; | |
33 | ||
556f4a33 SH |
34 | refclk: oscillator { |
35 | compatible = "fixed-clock"; | |
36 | #clock-cells = <0>; | |
37 | clock-frequency = <25000000>; | |
a9092118 SH |
38 | }; |
39 | ||
40 | soc { | |
41 | compatible = "simple-bus"; | |
42 | #address-cells = <1>; | |
43 | #size-cells = <1>; | |
44 | interrupt-parent = <&gic>; | |
45 | ||
46 | ranges = <0 0xf7000000 0x1000000>; | |
47 | ||
652538c4 SH |
48 | sdhci0: sdhci@ab0000 { |
49 | compatible = "mrvl,pxav3-mmc"; | |
50 | reg = <0xab0000 0x200>; | |
51 | clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; | |
52 | clock-names = "io", "core"; | |
53 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
54 | status = "disabled"; | |
55 | }; | |
56 | ||
a9092118 SH |
57 | l2: l2-cache-controller@ac0000 { |
58 | compatible = "arm,pl310-cache"; | |
59 | reg = <0xac0000 0x1000>; | |
60 | cache-unified; | |
61 | cache-level = <2>; | |
62 | }; | |
63 | ||
64 | gic: interrupt-controller@ad1000 { | |
65 | compatible = "arm,cortex-a9-gic"; | |
66 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; | |
67 | interrupt-controller; | |
68 | #interrupt-cells = <3>; | |
69 | }; | |
70 | ||
71 | local-timer@ad0600 { | |
72 | compatible = "arm,cortex-a9-twd-timer"; | |
73 | reg = <0xad0600 0x20>; | |
74 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
556f4a33 | 75 | clocks = <&chip CLKID_TWD>; |
a9092118 SH |
76 | }; |
77 | ||
e802b3a2 SH |
78 | usb_phy0: usb-phy@b74000 { |
79 | compatible = "marvell,berlin2cd-usb-phy"; | |
80 | reg = <0xb74000 0x128>; | |
81 | #phy-cells = <0>; | |
82 | resets = <&chip 0x178 23>; | |
83 | status = "disabled"; | |
84 | }; | |
85 | ||
86 | usb_phy1: usb-phy@b78000 { | |
87 | compatible = "marvell,berlin2cd-usb-phy"; | |
88 | reg = <0xb78000 0x128>; | |
89 | #phy-cells = <0>; | |
90 | resets = <&chip 0x178 24>; | |
91 | status = "disabled"; | |
92 | }; | |
93 | ||
631338af SH |
94 | eth1: ethernet@b90000 { |
95 | compatible = "marvell,pxa168-eth"; | |
96 | reg = <0xb90000 0x10000>; | |
97 | clocks = <&chip CLKID_GETH1>; | |
98 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
99 | /* set by bootloader */ | |
100 | local-mac-address = [00 00 00 00 00 00]; | |
101 | #address-cells = <1>; | |
102 | #size-cells = <0>; | |
103 | phy-connection-type = "mii"; | |
104 | phy-handle = <ðphy1>; | |
105 | status = "disabled"; | |
106 | ||
107 | ethphy1: ethernet-phy@0 { | |
108 | reg = <0>; | |
109 | }; | |
110 | }; | |
111 | ||
112 | eth0: ethernet@e50000 { | |
113 | compatible = "marvell,pxa168-eth"; | |
114 | reg = <0xe50000 0x10000>; | |
115 | clocks = <&chip CLKID_GETH0>; | |
116 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
117 | /* set by bootloader */ | |
118 | local-mac-address = [00 00 00 00 00 00]; | |
119 | #address-cells = <1>; | |
120 | #size-cells = <0>; | |
121 | phy-connection-type = "mii"; | |
122 | phy-handle = <ðphy0>; | |
123 | status = "disabled"; | |
124 | ||
125 | ethphy0: ethernet-phy@0 { | |
126 | reg = <0>; | |
127 | }; | |
128 | }; | |
129 | ||
a9092118 SH |
130 | apb@e80000 { |
131 | compatible = "simple-bus"; | |
132 | #address-cells = <1>; | |
133 | #size-cells = <1>; | |
134 | ||
135 | ranges = <0 0xe80000 0x10000>; | |
136 | interrupt-parent = <&aic>; | |
137 | ||
c920a669 AT |
138 | gpio0: gpio@0400 { |
139 | compatible = "snps,dw-apb-gpio"; | |
140 | reg = <0x0400 0x400>; | |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | ||
144 | porta: gpio-port@0 { | |
145 | compatible = "snps,dw-apb-gpio-port"; | |
146 | gpio-controller; | |
147 | #gpio-cells = <2>; | |
148 | snps,nr-gpios = <8>; | |
149 | reg = <0>; | |
150 | interrupt-controller; | |
151 | #interrupt-cells = <2>; | |
152 | interrupts = <0>; | |
153 | }; | |
154 | }; | |
155 | ||
156 | gpio1: gpio@0800 { | |
157 | compatible = "snps,dw-apb-gpio"; | |
158 | reg = <0x0800 0x400>; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | ||
162 | portb: gpio-port@1 { | |
163 | compatible = "snps,dw-apb-gpio-port"; | |
164 | gpio-controller; | |
165 | #gpio-cells = <2>; | |
166 | snps,nr-gpios = <8>; | |
167 | reg = <0>; | |
168 | interrupt-controller; | |
169 | #interrupt-cells = <2>; | |
170 | interrupts = <1>; | |
171 | }; | |
172 | }; | |
173 | ||
174 | gpio2: gpio@0c00 { | |
175 | compatible = "snps,dw-apb-gpio"; | |
176 | reg = <0x0c00 0x400>; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | ||
180 | portc: gpio-port@2 { | |
181 | compatible = "snps,dw-apb-gpio-port"; | |
182 | gpio-controller; | |
183 | #gpio-cells = <2>; | |
184 | snps,nr-gpios = <8>; | |
185 | reg = <0>; | |
186 | interrupt-controller; | |
187 | #interrupt-cells = <2>; | |
188 | interrupts = <2>; | |
189 | }; | |
190 | }; | |
191 | ||
192 | gpio3: gpio@1000 { | |
193 | compatible = "snps,dw-apb-gpio"; | |
194 | reg = <0x1000 0x400>; | |
195 | #address-cells = <1>; | |
196 | #size-cells = <0>; | |
197 | ||
198 | portd: gpio-port@3 { | |
199 | compatible = "snps,dw-apb-gpio-port"; | |
200 | gpio-controller; | |
201 | #gpio-cells = <2>; | |
202 | snps,nr-gpios = <8>; | |
203 | reg = <0>; | |
204 | interrupt-controller; | |
205 | #interrupt-cells = <2>; | |
206 | interrupts = <3>; | |
207 | }; | |
208 | }; | |
209 | ||
a9092118 SH |
210 | timer0: timer@2c00 { |
211 | compatible = "snps,dw-apb-timer"; | |
212 | reg = <0x2c00 0x14>; | |
213 | interrupts = <8>; | |
556f4a33 | 214 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
215 | clock-names = "timer"; |
216 | status = "okay"; | |
217 | }; | |
218 | ||
219 | timer1: timer@2c14 { | |
220 | compatible = "snps,dw-apb-timer"; | |
221 | reg = <0x2c14 0x14>; | |
222 | interrupts = <9>; | |
556f4a33 | 223 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
224 | clock-names = "timer"; |
225 | status = "okay"; | |
226 | }; | |
227 | ||
228 | timer2: timer@2c28 { | |
229 | compatible = "snps,dw-apb-timer"; | |
230 | reg = <0x2c28 0x14>; | |
231 | interrupts = <10>; | |
556f4a33 | 232 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
233 | clock-names = "timer"; |
234 | status = "disabled"; | |
235 | }; | |
236 | ||
237 | timer3: timer@2c3c { | |
238 | compatible = "snps,dw-apb-timer"; | |
239 | reg = <0x2c3c 0x14>; | |
240 | interrupts = <11>; | |
556f4a33 | 241 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
242 | clock-names = "timer"; |
243 | status = "disabled"; | |
244 | }; | |
245 | ||
246 | timer4: timer@2c50 { | |
247 | compatible = "snps,dw-apb-timer"; | |
248 | reg = <0x2c50 0x14>; | |
249 | interrupts = <12>; | |
556f4a33 | 250 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
251 | clock-names = "timer"; |
252 | status = "disabled"; | |
253 | }; | |
254 | ||
255 | timer5: timer@2c64 { | |
256 | compatible = "snps,dw-apb-timer"; | |
257 | reg = <0x2c64 0x14>; | |
258 | interrupts = <13>; | |
556f4a33 | 259 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
260 | clock-names = "timer"; |
261 | status = "disabled"; | |
262 | }; | |
263 | ||
264 | timer6: timer@2c78 { | |
265 | compatible = "snps,dw-apb-timer"; | |
266 | reg = <0x2c78 0x14>; | |
267 | interrupts = <14>; | |
556f4a33 | 268 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
269 | clock-names = "timer"; |
270 | status = "disabled"; | |
271 | }; | |
272 | ||
273 | timer7: timer@2c8c { | |
274 | compatible = "snps,dw-apb-timer"; | |
275 | reg = <0x2c8c 0x14>; | |
276 | interrupts = <15>; | |
556f4a33 | 277 | clocks = <&chip CLKID_CFG>; |
a9092118 SH |
278 | clock-names = "timer"; |
279 | status = "disabled"; | |
280 | }; | |
281 | ||
282 | aic: interrupt-controller@3000 { | |
283 | compatible = "snps,dw-apb-ictl"; | |
284 | reg = <0x3000 0xc00>; | |
285 | interrupt-controller; | |
286 | #interrupt-cells = <1>; | |
287 | interrupt-parent = <&gic>; | |
288 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
289 | }; | |
290 | }; | |
291 | ||
556f4a33 SH |
292 | chip: chip-control@ea0000 { |
293 | compatible = "marvell,berlin2cd-chip-ctrl"; | |
294 | #clock-cells = <1>; | |
1e27a261 | 295 | #reset-cells = <2>; |
556f4a33 SH |
296 | reg = <0xea0000 0x400>; |
297 | clocks = <&refclk>; | |
298 | clock-names = "refclk"; | |
50cc24ff AT |
299 | |
300 | uart0_pmux: uart0-pmux { | |
301 | groups = "G6"; | |
302 | function = "uart0"; | |
303 | }; | |
556f4a33 SH |
304 | }; |
305 | ||
e802b3a2 SH |
306 | usb0: usb@ed0000 { |
307 | compatible = "chipidea,usb2"; | |
308 | reg = <0xed0000 0x200>; | |
309 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
310 | clocks = <&chip CLKID_USB0>; | |
311 | phys = <&usb_phy0>; | |
312 | phy-names = "usb-phy"; | |
313 | status = "disabled"; | |
314 | }; | |
315 | ||
316 | usb1: usb@ee0000 { | |
317 | compatible = "chipidea,usb2"; | |
318 | reg = <0xee0000 0x200>; | |
319 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
320 | clocks = <&chip CLKID_USB1>; | |
321 | phys = <&usb_phy1>; | |
322 | phy-names = "usb-phy"; | |
323 | status = "disabled"; | |
324 | }; | |
325 | ||
a9092118 SH |
326 | apb@fc0000 { |
327 | compatible = "simple-bus"; | |
328 | #address-cells = <1>; | |
329 | #size-cells = <1>; | |
330 | ||
331 | ranges = <0 0xfc0000 0x10000>; | |
332 | interrupt-parent = <&sic>; | |
333 | ||
c920a669 AT |
334 | sm_gpio1: gpio@5000 { |
335 | compatible = "snps,dw-apb-gpio"; | |
336 | reg = <0x5000 0x400>; | |
337 | #address-cells = <1>; | |
338 | #size-cells = <0>; | |
339 | ||
340 | portf: gpio-port@5 { | |
341 | compatible = "snps,dw-apb-gpio-port"; | |
342 | gpio-controller; | |
343 | #gpio-cells = <2>; | |
344 | snps,nr-gpios = <8>; | |
345 | reg = <0>; | |
346 | }; | |
347 | }; | |
348 | ||
349 | sm_gpio0: gpio@c000 { | |
350 | compatible = "snps,dw-apb-gpio"; | |
351 | reg = <0xc000 0x400>; | |
352 | #address-cells = <1>; | |
353 | #size-cells = <0>; | |
354 | ||
355 | porte: gpio-port@4 { | |
356 | compatible = "snps,dw-apb-gpio-port"; | |
357 | gpio-controller; | |
358 | #gpio-cells = <2>; | |
359 | snps,nr-gpios = <8>; | |
360 | reg = <0>; | |
361 | }; | |
362 | }; | |
363 | ||
a9092118 SH |
364 | uart0: serial@9000 { |
365 | compatible = "snps,dw-apb-uart"; | |
366 | reg = <0x9000 0x100>; | |
367 | reg-shift = <2>; | |
368 | reg-io-width = <1>; | |
369 | interrupts = <8>; | |
556f4a33 | 370 | clocks = <&refclk>; |
50cc24ff AT |
371 | pinctrl-0 = <&uart0_pmux>; |
372 | pinctrl-names = "default"; | |
a9092118 SH |
373 | status = "disabled"; |
374 | }; | |
375 | ||
376 | uart1: serial@a000 { | |
377 | compatible = "snps,dw-apb-uart"; | |
378 | reg = <0xa000 0x100>; | |
379 | reg-shift = <2>; | |
380 | reg-io-width = <1>; | |
381 | interrupts = <9>; | |
556f4a33 | 382 | clocks = <&refclk>; |
a9092118 SH |
383 | status = "disabled"; |
384 | }; | |
385 | ||
50cc24ff AT |
386 | sysctrl: system-controller@d000 { |
387 | compatible = "marvell,berlin2cd-system-ctrl"; | |
388 | reg = <0xd000 0x100>; | |
389 | }; | |
390 | ||
a9092118 SH |
391 | sic: interrupt-controller@e000 { |
392 | compatible = "snps,dw-apb-ictl"; | |
393 | reg = <0xe000 0x400>; | |
394 | interrupt-controller; | |
395 | #interrupt-cells = <1>; | |
396 | interrupt-parent = <&gic>; | |
397 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
398 | }; | |
399 | }; | |
400 | }; | |
401 | }; |