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374ddcbf AT |
1 | /* |
2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> | |
3 | * | |
af98945e AT |
4 | * This file is dual-licensed: you can use it either under the terms |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | * | |
13 | * Or, alternatively, | |
14 | * | |
15 | * b) Permission is hereby granted, free of charge, to any person | |
16 | * obtaining a copy of this software and associated documentation | |
17 | * files (the "Software"), to deal in the Software without | |
18 | * restriction, including without limitation the rights to use, | |
19 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
20 | * sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following | |
22 | * conditions: | |
23 | * | |
24 | * The above copyright notice and this permission notice shall be | |
25 | * included in all copies or substantial portions of the Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
28 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
29 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
30 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
31 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
32 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
33 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
34 | * OTHER DEALINGS IN THE SOFTWARE. | |
374ddcbf AT |
35 | */ |
36 | ||
414dcf8f | 37 | #include <dt-bindings/clock/berlin2q.h> |
374ddcbf AT |
38 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
39 | ||
40 | #include "skeleton.dtsi" | |
41 | ||
42 | / { | |
43 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; | |
44 | compatible = "marvell,berlin2q", "marvell,berlin"; | |
45 | ||
487eacb9 JZ |
46 | aliases { |
47 | serial0 = &uart0; | |
48 | serial1 = &uart1; | |
49 | }; | |
50 | ||
374ddcbf AT |
51 | cpus { |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
d19c9367 | 54 | enable-method = "marvell,berlin-smp"; |
374ddcbf AT |
55 | |
56 | cpu@0 { | |
57 | compatible = "arm,cortex-a9"; | |
58 | device_type = "cpu"; | |
59 | next-level-cache = <&l2>; | |
60 | reg = <0>; | |
23998645 AT |
61 | |
62 | clocks = <&chip_clk CLKID_CPU>; | |
63 | clock-latency = <100000>; | |
64 | /* Can be modified by the bootloader */ | |
65 | operating-points = < | |
66 | /* kHz uV */ | |
67 | 1200000 1200000 | |
68 | 1000000 1200000 | |
69 | 800000 1200000 | |
70 | 600000 1200000 | |
71 | >; | |
374ddcbf AT |
72 | }; |
73 | ||
74 | cpu@1 { | |
75 | compatible = "arm,cortex-a9"; | |
76 | device_type = "cpu"; | |
77 | next-level-cache = <&l2>; | |
78 | reg = <1>; | |
79 | }; | |
80 | ||
81 | cpu@2 { | |
82 | compatible = "arm,cortex-a9"; | |
83 | device_type = "cpu"; | |
84 | next-level-cache = <&l2>; | |
85 | reg = <2>; | |
86 | }; | |
87 | ||
88 | cpu@3 { | |
89 | compatible = "arm,cortex-a9"; | |
90 | device_type = "cpu"; | |
91 | next-level-cache = <&l2>; | |
92 | reg = <3>; | |
93 | }; | |
94 | }; | |
95 | ||
414dcf8f | 96 | refclk: oscillator { |
374ddcbf AT |
97 | compatible = "fixed-clock"; |
98 | #clock-cells = <0>; | |
99 | clock-frequency = <25000000>; | |
100 | }; | |
101 | ||
374ddcbf AT |
102 | soc { |
103 | compatible = "simple-bus"; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | ||
107 | ranges = <0 0xf7000000 0x1000000>; | |
108 | interrupt-parent = <&gic>; | |
109 | ||
d4ce8042 JZ |
110 | pmu { |
111 | compatible = "arm,cortex-a9-pmu"; | |
112 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, | |
113 | <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
114 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
115 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
116 | }; | |
117 | ||
0d859a6a AT |
118 | sdhci0: sdhci@ab0000 { |
119 | compatible = "mrvl,pxav3-mmc"; | |
120 | reg = <0xab0000 0x200>; | |
a457b86c | 121 | clocks = <&chip_clk CLKID_SDIO1XIN>; |
0d859a6a AT |
122 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | sdhci1: sdhci@ab0800 { | |
127 | compatible = "mrvl,pxav3-mmc"; | |
128 | reg = <0xab0800 0x200>; | |
a457b86c | 129 | clocks = <&chip_clk CLKID_SDIO1XIN>; |
0d859a6a AT |
130 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
131 | status = "disabled"; | |
132 | }; | |
133 | ||
134 | sdhci2: sdhci@ab1000 { | |
135 | compatible = "mrvl,pxav3-mmc"; | |
136 | reg = <0xab1000 0x200>; | |
137 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
a457b86c | 138 | clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; |
96ed6046 | 139 | clock-names = "io", "core"; |
0d859a6a AT |
140 | status = "disabled"; |
141 | }; | |
142 | ||
374ddcbf AT |
143 | l2: l2-cache-controller@ac0000 { |
144 | compatible = "arm,pl310-cache"; | |
145 | reg = <0xac0000 0x1000>; | |
146 | cache-level = <2>; | |
44991eb4 JZ |
147 | arm,data-latency = <2 2 2>; |
148 | arm,tag-latency = <2 2 2>; | |
374ddcbf AT |
149 | }; |
150 | ||
0bd4b346 SH |
151 | scu: snoop-control-unit@ad0000 { |
152 | compatible = "arm,cortex-a9-scu"; | |
153 | reg = <0xad0000 0x58>; | |
154 | }; | |
155 | ||
374ddcbf AT |
156 | local-timer@ad0600 { |
157 | compatible = "arm,cortex-a9-twd-timer"; | |
158 | reg = <0xad0600 0x20>; | |
a457b86c | 159 | clocks = <&chip_clk CLKID_TWD>; |
2356d2f3 | 160 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
374ddcbf AT |
161 | }; |
162 | ||
163 | gic: interrupt-controller@ad1000 { | |
164 | compatible = "arm,cortex-a9-gic"; | |
165 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; | |
166 | interrupt-controller; | |
167 | #interrupt-cells = <3>; | |
168 | }; | |
169 | ||
c539711e | 170 | usb_phy2: phy@a2f400 { |
1f744fd3 | 171 | compatible = "marvell,berlin2cd-usb-phy"; |
c539711e AT |
172 | reg = <0xa2f400 0x128>; |
173 | #phy-cells = <0>; | |
43225728 | 174 | resets = <&chip_rst 0x104 14>; |
c539711e AT |
175 | status = "disabled"; |
176 | }; | |
177 | ||
178 | usb2: usb@a30000 { | |
179 | compatible = "chipidea,usb2"; | |
180 | reg = <0xa30000 0x10000>; | |
181 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
a457b86c | 182 | clocks = <&chip_clk CLKID_USB2>; |
c539711e AT |
183 | phys = <&usb_phy2>; |
184 | phy-names = "usb-phy"; | |
185 | status = "disabled"; | |
186 | }; | |
187 | ||
188 | usb_phy0: phy@b74000 { | |
1f744fd3 | 189 | compatible = "marvell,berlin2cd-usb-phy"; |
c539711e AT |
190 | reg = <0xb74000 0x128>; |
191 | #phy-cells = <0>; | |
43225728 | 192 | resets = <&chip_rst 0x104 12>; |
c539711e AT |
193 | status = "disabled"; |
194 | }; | |
195 | ||
196 | usb_phy1: phy@b78000 { | |
1f744fd3 | 197 | compatible = "marvell,berlin2cd-usb-phy"; |
c539711e AT |
198 | reg = <0xb78000 0x128>; |
199 | #phy-cells = <0>; | |
43225728 | 200 | resets = <&chip_rst 0x104 13>; |
c539711e AT |
201 | status = "disabled"; |
202 | }; | |
203 | ||
bdc06cd7 AT |
204 | eth0: ethernet@b90000 { |
205 | compatible = "marvell,pxa168-eth"; | |
206 | reg = <0xb90000 0x10000>; | |
a457b86c | 207 | clocks = <&chip_clk CLKID_GETH0>; |
bdc06cd7 AT |
208 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
209 | /* set by bootloader */ | |
210 | local-mac-address = [00 00 00 00 00 00]; | |
211 | #address-cells = <1>; | |
212 | #size-cells = <0>; | |
f5799dcf | 213 | phy-connection-type = "mii"; |
bdc06cd7 AT |
214 | phy-handle = <ðphy0>; |
215 | status = "disabled"; | |
216 | ||
217 | ethphy0: ethernet-phy@0 { | |
218 | reg = <0>; | |
219 | }; | |
220 | }; | |
221 | ||
d19c9367 AT |
222 | cpu-ctrl@dd0000 { |
223 | compatible = "marvell,berlin-cpu-ctrl"; | |
224 | reg = <0xdd0000 0x10000>; | |
225 | }; | |
226 | ||
374ddcbf AT |
227 | apb@e80000 { |
228 | compatible = "simple-bus"; | |
229 | #address-cells = <1>; | |
230 | #size-cells = <1>; | |
231 | ||
232 | ranges = <0 0xe80000 0x10000>; | |
233 | interrupt-parent = <&aic>; | |
234 | ||
cedf57fc AT |
235 | gpio0: gpio@0400 { |
236 | compatible = "snps,dw-apb-gpio"; | |
237 | reg = <0x0400 0x400>; | |
238 | #address-cells = <1>; | |
239 | #size-cells = <0>; | |
240 | ||
241 | porta: gpio-port@0 { | |
242 | compatible = "snps,dw-apb-gpio-port"; | |
243 | gpio-controller; | |
244 | #gpio-cells = <2>; | |
245 | snps,nr-gpios = <32>; | |
246 | reg = <0>; | |
247 | interrupt-controller; | |
248 | #interrupt-cells = <2>; | |
249 | interrupts = <0>; | |
250 | }; | |
251 | }; | |
252 | ||
253 | gpio1: gpio@0800 { | |
254 | compatible = "snps,dw-apb-gpio"; | |
255 | reg = <0x0800 0x400>; | |
256 | #address-cells = <1>; | |
257 | #size-cells = <0>; | |
258 | ||
259 | portb: gpio-port@1 { | |
260 | compatible = "snps,dw-apb-gpio-port"; | |
261 | gpio-controller; | |
262 | #gpio-cells = <2>; | |
263 | snps,nr-gpios = <32>; | |
264 | reg = <0>; | |
265 | interrupt-controller; | |
266 | #interrupt-cells = <2>; | |
267 | interrupts = <1>; | |
268 | }; | |
269 | }; | |
270 | ||
271 | gpio2: gpio@0c00 { | |
272 | compatible = "snps,dw-apb-gpio"; | |
273 | reg = <0x0c00 0x400>; | |
274 | #address-cells = <1>; | |
275 | #size-cells = <0>; | |
276 | ||
277 | portc: gpio-port@2 { | |
278 | compatible = "snps,dw-apb-gpio-port"; | |
279 | gpio-controller; | |
280 | #gpio-cells = <2>; | |
281 | snps,nr-gpios = <32>; | |
282 | reg = <0>; | |
283 | interrupt-controller; | |
284 | #interrupt-cells = <2>; | |
285 | interrupts = <2>; | |
286 | }; | |
287 | }; | |
288 | ||
289 | gpio3: gpio@1000 { | |
290 | compatible = "snps,dw-apb-gpio"; | |
291 | reg = <0x1000 0x400>; | |
292 | #address-cells = <1>; | |
293 | #size-cells = <0>; | |
294 | ||
295 | portd: gpio-port@3 { | |
296 | compatible = "snps,dw-apb-gpio-port"; | |
297 | gpio-controller; | |
298 | #gpio-cells = <2>; | |
299 | snps,nr-gpios = <32>; | |
300 | reg = <0>; | |
301 | interrupt-controller; | |
302 | #interrupt-cells = <2>; | |
303 | interrupts = <3>; | |
304 | }; | |
305 | }; | |
306 | ||
99f3deb8 AT |
307 | i2c0: i2c@1400 { |
308 | compatible = "snps,designware-i2c"; | |
309 | #address-cells = <1>; | |
310 | #size-cells = <0>; | |
311 | reg = <0x1400 0x100>; | |
312 | interrupt-parent = <&aic>; | |
313 | interrupts = <4>; | |
a457b86c | 314 | clocks = <&chip_clk CLKID_CFG>; |
99f3deb8 AT |
315 | pinctrl-0 = <&twsi0_pmux>; |
316 | pinctrl-names = "default"; | |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
320 | i2c1: i2c@1800 { | |
321 | compatible = "snps,designware-i2c"; | |
322 | #address-cells = <1>; | |
323 | #size-cells = <0>; | |
324 | reg = <0x1800 0x100>; | |
325 | interrupt-parent = <&aic>; | |
326 | interrupts = <5>; | |
a457b86c | 327 | clocks = <&chip_clk CLKID_CFG>; |
99f3deb8 AT |
328 | pinctrl-0 = <&twsi1_pmux>; |
329 | pinctrl-names = "default"; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
374ddcbf AT |
333 | timer0: timer@2c00 { |
334 | compatible = "snps,dw-apb-timer"; | |
335 | reg = <0x2c00 0x14>; | |
a457b86c | 336 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
337 | clock-names = "timer"; |
338 | interrupts = <8>; | |
339 | }; | |
340 | ||
341 | timer1: timer@2c14 { | |
342 | compatible = "snps,dw-apb-timer"; | |
343 | reg = <0x2c14 0x14>; | |
a457b86c | 344 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf | 345 | clock-names = "timer"; |
374ddcbf AT |
346 | }; |
347 | ||
348 | timer2: timer@2c28 { | |
349 | compatible = "snps,dw-apb-timer"; | |
350 | reg = <0x2c28 0x14>; | |
a457b86c | 351 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
352 | clock-names = "timer"; |
353 | status = "disabled"; | |
354 | }; | |
355 | ||
356 | timer3: timer@2c3c { | |
357 | compatible = "snps,dw-apb-timer"; | |
358 | reg = <0x2c3c 0x14>; | |
a457b86c | 359 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
360 | clock-names = "timer"; |
361 | status = "disabled"; | |
362 | }; | |
363 | ||
364 | timer4: timer@2c50 { | |
365 | compatible = "snps,dw-apb-timer"; | |
366 | reg = <0x2c50 0x14>; | |
a457b86c | 367 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
368 | clock-names = "timer"; |
369 | status = "disabled"; | |
370 | }; | |
371 | ||
372 | timer5: timer@2c64 { | |
373 | compatible = "snps,dw-apb-timer"; | |
374 | reg = <0x2c64 0x14>; | |
a457b86c | 375 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
376 | clock-names = "timer"; |
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | timer6: timer@2c78 { | |
381 | compatible = "snps,dw-apb-timer"; | |
382 | reg = <0x2c78 0x14>; | |
a457b86c | 383 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
384 | clock-names = "timer"; |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | timer7: timer@2c8c { | |
389 | compatible = "snps,dw-apb-timer"; | |
390 | reg = <0x2c8c 0x14>; | |
a457b86c | 391 | clocks = <&chip_clk CLKID_CFG>; |
374ddcbf AT |
392 | clock-names = "timer"; |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
396 | aic: interrupt-controller@3800 { | |
397 | compatible = "snps,dw-apb-ictl"; | |
398 | reg = <0x3800 0x30>; | |
399 | interrupt-controller; | |
400 | #interrupt-cells = <1>; | |
401 | interrupt-parent = <&gic>; | |
402 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
403 | }; | |
404 | }; | |
405 | ||
414dcf8f | 406 | chip: chip-control@ea0000 { |
f3f94f71 | 407 | compatible = "simple-mfd", "syscon"; |
414dcf8f | 408 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
99f3deb8 | 409 | |
a457b86c AT |
410 | chip_clk: clock { |
411 | compatible = "marvell,berlin2q-clk"; | |
412 | #clock-cells = <1>; | |
413 | clocks = <&refclk>; | |
414 | clock-names = "refclk"; | |
99f3deb8 AT |
415 | }; |
416 | ||
630c986b AT |
417 | soc_pinctrl: pin-controller { |
418 | compatible = "marvell,berlin2q-soc-pinctrl"; | |
419 | ||
420 | twsi0_pmux: twsi0-pmux { | |
421 | groups = "G6"; | |
422 | function = "twsi0"; | |
423 | }; | |
99f3deb8 | 424 | |
630c986b AT |
425 | twsi1_pmux: twsi1-pmux { |
426 | groups = "G7"; | |
427 | function = "twsi1"; | |
428 | }; | |
99f3deb8 | 429 | }; |
43225728 AT |
430 | |
431 | chip_rst: reset { | |
432 | compatible = "marvell,berlin2-reset"; | |
433 | #reset-cells = <2>; | |
99f3deb8 | 434 | }; |
0bd4b346 SH |
435 | }; |
436 | ||
70a2b717 AT |
437 | ahci: sata@e90000 { |
438 | compatible = "marvell,berlin2q-ahci", "generic-ahci"; | |
439 | reg = <0xe90000 0x1000>; | |
440 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
a457b86c | 441 | clocks = <&chip_clk CLKID_SATA>; |
70a2b717 AT |
442 | #address-cells = <1>; |
443 | #size-cells = <0>; | |
444 | ||
445 | sata0: sata-port@0 { | |
446 | reg = <0>; | |
447 | phys = <&sata_phy 0>; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
451 | sata1: sata-port@1 { | |
452 | reg = <1>; | |
453 | phys = <&sata_phy 1>; | |
454 | status = "disabled"; | |
455 | }; | |
456 | }; | |
457 | ||
458 | sata_phy: phy@e900a0 { | |
459 | compatible = "marvell,berlin2q-sata-phy"; | |
460 | reg = <0xe900a0 0x200>; | |
a457b86c | 461 | clocks = <&chip_clk CLKID_SATA>; |
70a2b717 AT |
462 | #address-cells = <1>; |
463 | #size-cells = <0>; | |
464 | #phy-cells = <1>; | |
465 | status = "disabled"; | |
466 | ||
467 | sata-phy@0 { | |
468 | reg = <0>; | |
469 | }; | |
470 | ||
471 | sata-phy@1 { | |
472 | reg = <1>; | |
473 | }; | |
474 | }; | |
475 | ||
c539711e AT |
476 | usb0: usb@ed0000 { |
477 | compatible = "chipidea,usb2"; | |
478 | reg = <0xed0000 0x10000>; | |
479 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
a457b86c | 480 | clocks = <&chip_clk CLKID_USB0>; |
c539711e AT |
481 | phys = <&usb_phy0>; |
482 | phy-names = "usb-phy"; | |
483 | status = "disabled"; | |
484 | }; | |
485 | ||
486 | usb1: usb@ee0000 { | |
487 | compatible = "chipidea,usb2"; | |
488 | reg = <0xee0000 0x10000>; | |
489 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
a457b86c | 490 | clocks = <&chip_clk CLKID_USB1>; |
c539711e AT |
491 | phys = <&usb_phy1>; |
492 | phy-names = "usb-phy"; | |
493 | status = "disabled"; | |
494 | }; | |
495 | ||
956d8217 AT |
496 | pwm: pwm@f20000 { |
497 | compatible = "marvell,berlin-pwm"; | |
498 | reg = <0xf20000 0x40>; | |
499 | clocks = <&chip_clk CLKID_CFG>; | |
500 | #pwm-cells = <3>; | |
501 | }; | |
502 | ||
374ddcbf AT |
503 | apb@fc0000 { |
504 | compatible = "simple-bus"; | |
505 | #address-cells = <1>; | |
506 | #size-cells = <1>; | |
507 | ||
508 | ranges = <0 0xfc0000 0x10000>; | |
509 | interrupt-parent = <&sic>; | |
510 | ||
5138d5c5 JZ |
511 | sm_gpio1: gpio@5000 { |
512 | compatible = "snps,dw-apb-gpio"; | |
513 | reg = <0x5000 0x400>; | |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
516 | ||
517 | portf: gpio-port@5 { | |
518 | compatible = "snps,dw-apb-gpio-port"; | |
519 | gpio-controller; | |
520 | #gpio-cells = <2>; | |
521 | snps,nr-gpios = <32>; | |
522 | reg = <0>; | |
523 | }; | |
524 | }; | |
525 | ||
99f3deb8 AT |
526 | i2c2: i2c@7000 { |
527 | compatible = "snps,designware-i2c"; | |
528 | #address-cells = <1>; | |
529 | #size-cells = <0>; | |
530 | reg = <0x7000 0x100>; | |
531 | interrupt-parent = <&sic>; | |
532 | interrupts = <6>; | |
533 | clocks = <&refclk>; | |
534 | pinctrl-0 = <&twsi2_pmux>; | |
535 | pinctrl-names = "default"; | |
536 | status = "disabled"; | |
537 | }; | |
538 | ||
539 | i2c3: i2c@8000 { | |
540 | compatible = "snps,designware-i2c"; | |
541 | #address-cells = <1>; | |
542 | #size-cells = <0>; | |
543 | reg = <0x8000 0x100>; | |
544 | interrupt-parent = <&sic>; | |
545 | interrupts = <7>; | |
546 | clocks = <&refclk>; | |
547 | pinctrl-0 = <&twsi3_pmux>; | |
548 | pinctrl-names = "default"; | |
549 | status = "disabled"; | |
550 | }; | |
551 | ||
374ddcbf AT |
552 | uart0: uart@9000 { |
553 | compatible = "snps,dw-apb-uart"; | |
554 | reg = <0x9000 0x100>; | |
555 | interrupt-parent = <&sic>; | |
556 | interrupts = <8>; | |
414dcf8f | 557 | clocks = <&refclk>; |
374ddcbf | 558 | reg-shift = <2>; |
50cc24ff AT |
559 | pinctrl-0 = <&uart0_pmux>; |
560 | pinctrl-names = "default"; | |
374ddcbf AT |
561 | status = "disabled"; |
562 | }; | |
563 | ||
564 | uart1: uart@a000 { | |
565 | compatible = "snps,dw-apb-uart"; | |
566 | reg = <0xa000 0x100>; | |
567 | interrupt-parent = <&sic>; | |
568 | interrupts = <9>; | |
414dcf8f | 569 | clocks = <&refclk>; |
374ddcbf | 570 | reg-shift = <2>; |
50cc24ff AT |
571 | pinctrl-0 = <&uart1_pmux>; |
572 | pinctrl-names = "default"; | |
374ddcbf AT |
573 | status = "disabled"; |
574 | }; | |
575 | ||
5138d5c5 JZ |
576 | sm_gpio0: gpio@c000 { |
577 | compatible = "snps,dw-apb-gpio"; | |
578 | reg = <0xc000 0x400>; | |
579 | #address-cells = <1>; | |
580 | #size-cells = <0>; | |
581 | ||
582 | porte: gpio-port@4 { | |
583 | compatible = "snps,dw-apb-gpio-port"; | |
584 | gpio-controller; | |
585 | #gpio-cells = <2>; | |
586 | snps,nr-gpios = <32>; | |
587 | reg = <0>; | |
588 | }; | |
589 | }; | |
590 | ||
50cc24ff | 591 | sysctrl: pin-controller@d000 { |
f3f94f71 | 592 | compatible = "simple-mfd", "syscon"; |
50cc24ff AT |
593 | reg = <0xd000 0x100>; |
594 | ||
630c986b AT |
595 | sys_pinctrl: pin-controller { |
596 | compatible = "marvell,berlin2q-system-pinctrl"; | |
50cc24ff | 597 | |
630c986b AT |
598 | uart0_pmux: uart0-pmux { |
599 | groups = "GSM12"; | |
600 | function = "uart0"; | |
601 | }; | |
99f3deb8 | 602 | |
630c986b AT |
603 | uart1_pmux: uart1-pmux { |
604 | groups = "GSM14"; | |
605 | function = "uart1"; | |
606 | }; | |
607 | ||
608 | twsi2_pmux: twsi2-pmux { | |
609 | groups = "GSM13"; | |
610 | function = "twsi2"; | |
611 | }; | |
99f3deb8 | 612 | |
630c986b AT |
613 | twsi3_pmux: twsi3-pmux { |
614 | groups = "GSM14"; | |
615 | function = "twsi3"; | |
616 | }; | |
99f3deb8 AT |
617 | }; |
618 | ||
5be23611 AT |
619 | adc: adc { |
620 | compatible = "marvell,berlin2-adc"; | |
621 | interrupts = <12>, <14>; | |
622 | interrupt-names = "adc", "tsen"; | |
99f3deb8 | 623 | }; |
50cc24ff AT |
624 | }; |
625 | ||
374ddcbf AT |
626 | sic: interrupt-controller@e000 { |
627 | compatible = "snps,dw-apb-ictl"; | |
628 | reg = <0xe000 0x30>; | |
629 | interrupt-controller; | |
630 | #interrupt-cells = <1>; | |
631 | interrupt-parent = <&gic>; | |
632 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
633 | }; | |
634 | }; | |
635 | }; | |
636 | }; |