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374ddcbf AT |
1 | /* |
2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
414dcf8f | 9 | #include <dt-bindings/clock/berlin2q.h> |
374ddcbf AT |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
11 | ||
12 | #include "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; | |
16 | compatible = "marvell,berlin2q", "marvell,berlin"; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
d19c9367 | 21 | enable-method = "marvell,berlin-smp"; |
374ddcbf AT |
22 | |
23 | cpu@0 { | |
24 | compatible = "arm,cortex-a9"; | |
25 | device_type = "cpu"; | |
26 | next-level-cache = <&l2>; | |
27 | reg = <0>; | |
28 | }; | |
29 | ||
30 | cpu@1 { | |
31 | compatible = "arm,cortex-a9"; | |
32 | device_type = "cpu"; | |
33 | next-level-cache = <&l2>; | |
34 | reg = <1>; | |
35 | }; | |
36 | ||
37 | cpu@2 { | |
38 | compatible = "arm,cortex-a9"; | |
39 | device_type = "cpu"; | |
40 | next-level-cache = <&l2>; | |
41 | reg = <2>; | |
42 | }; | |
43 | ||
44 | cpu@3 { | |
45 | compatible = "arm,cortex-a9"; | |
46 | device_type = "cpu"; | |
47 | next-level-cache = <&l2>; | |
48 | reg = <3>; | |
49 | }; | |
50 | }; | |
51 | ||
414dcf8f | 52 | refclk: oscillator { |
374ddcbf AT |
53 | compatible = "fixed-clock"; |
54 | #clock-cells = <0>; | |
55 | clock-frequency = <25000000>; | |
56 | }; | |
57 | ||
374ddcbf AT |
58 | soc { |
59 | compatible = "simple-bus"; | |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | ||
63 | ranges = <0 0xf7000000 0x1000000>; | |
64 | interrupt-parent = <&gic>; | |
65 | ||
d4ce8042 JZ |
66 | pmu { |
67 | compatible = "arm,cortex-a9-pmu"; | |
68 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, | |
69 | <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
72 | }; | |
73 | ||
0d859a6a AT |
74 | sdhci0: sdhci@ab0000 { |
75 | compatible = "mrvl,pxav3-mmc"; | |
76 | reg = <0xab0000 0x200>; | |
77 | clocks = <&chip CLKID_SDIO1XIN>; | |
78 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | sdhci1: sdhci@ab0800 { | |
83 | compatible = "mrvl,pxav3-mmc"; | |
84 | reg = <0xab0800 0x200>; | |
85 | clocks = <&chip CLKID_SDIO1XIN>; | |
86 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | sdhci2: sdhci@ab1000 { | |
91 | compatible = "mrvl,pxav3-mmc"; | |
92 | reg = <0xab1000 0x200>; | |
93 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
94 | clocks = <&chip CLKID_SDIO1XIN>; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
374ddcbf AT |
98 | l2: l2-cache-controller@ac0000 { |
99 | compatible = "arm,pl310-cache"; | |
100 | reg = <0xac0000 0x1000>; | |
101 | cache-level = <2>; | |
44991eb4 JZ |
102 | arm,data-latency = <2 2 2>; |
103 | arm,tag-latency = <2 2 2>; | |
374ddcbf AT |
104 | }; |
105 | ||
0bd4b346 SH |
106 | scu: snoop-control-unit@ad0000 { |
107 | compatible = "arm,cortex-a9-scu"; | |
108 | reg = <0xad0000 0x58>; | |
109 | }; | |
110 | ||
374ddcbf AT |
111 | local-timer@ad0600 { |
112 | compatible = "arm,cortex-a9-twd-timer"; | |
113 | reg = <0xad0600 0x20>; | |
414dcf8f | 114 | clocks = <&chip CLKID_TWD>; |
374ddcbf AT |
115 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
116 | }; | |
117 | ||
118 | gic: interrupt-controller@ad1000 { | |
119 | compatible = "arm,cortex-a9-gic"; | |
120 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; | |
121 | interrupt-controller; | |
122 | #interrupt-cells = <3>; | |
123 | }; | |
124 | ||
c539711e AT |
125 | usb_phy2: phy@a2f400 { |
126 | compatible = "marvell,berlin2-usb-phy"; | |
127 | reg = <0xa2f400 0x128>; | |
128 | #phy-cells = <0>; | |
129 | resets = <&chip 0x104 14>; | |
130 | status = "disabled"; | |
131 | }; | |
132 | ||
133 | usb2: usb@a30000 { | |
134 | compatible = "chipidea,usb2"; | |
135 | reg = <0xa30000 0x10000>; | |
136 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
137 | clocks = <&chip CLKID_USB2>; | |
138 | phys = <&usb_phy2>; | |
139 | phy-names = "usb-phy"; | |
140 | status = "disabled"; | |
141 | }; | |
142 | ||
143 | usb_phy0: phy@b74000 { | |
144 | compatible = "marvell,berlin2-usb-phy"; | |
145 | reg = <0xb74000 0x128>; | |
146 | #phy-cells = <0>; | |
147 | resets = <&chip 0x104 12>; | |
148 | status = "disabled"; | |
149 | }; | |
150 | ||
151 | usb_phy1: phy@b78000 { | |
152 | compatible = "marvell,berlin2-usb-phy"; | |
153 | reg = <0xb78000 0x128>; | |
154 | #phy-cells = <0>; | |
155 | resets = <&chip 0x104 13>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
bdc06cd7 AT |
159 | eth0: ethernet@b90000 { |
160 | compatible = "marvell,pxa168-eth"; | |
161 | reg = <0xb90000 0x10000>; | |
162 | clocks = <&chip CLKID_GETH0>; | |
163 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
164 | /* set by bootloader */ | |
165 | local-mac-address = [00 00 00 00 00 00]; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <0>; | |
f5799dcf | 168 | phy-connection-type = "mii"; |
bdc06cd7 AT |
169 | phy-handle = <ðphy0>; |
170 | status = "disabled"; | |
171 | ||
172 | ethphy0: ethernet-phy@0 { | |
173 | reg = <0>; | |
174 | }; | |
175 | }; | |
176 | ||
d19c9367 AT |
177 | cpu-ctrl@dd0000 { |
178 | compatible = "marvell,berlin-cpu-ctrl"; | |
179 | reg = <0xdd0000 0x10000>; | |
180 | }; | |
181 | ||
374ddcbf AT |
182 | apb@e80000 { |
183 | compatible = "simple-bus"; | |
184 | #address-cells = <1>; | |
185 | #size-cells = <1>; | |
186 | ||
187 | ranges = <0 0xe80000 0x10000>; | |
188 | interrupt-parent = <&aic>; | |
189 | ||
cedf57fc AT |
190 | gpio0: gpio@0400 { |
191 | compatible = "snps,dw-apb-gpio"; | |
192 | reg = <0x0400 0x400>; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <0>; | |
195 | ||
196 | porta: gpio-port@0 { | |
197 | compatible = "snps,dw-apb-gpio-port"; | |
198 | gpio-controller; | |
199 | #gpio-cells = <2>; | |
200 | snps,nr-gpios = <32>; | |
201 | reg = <0>; | |
202 | interrupt-controller; | |
203 | #interrupt-cells = <2>; | |
204 | interrupts = <0>; | |
205 | }; | |
206 | }; | |
207 | ||
208 | gpio1: gpio@0800 { | |
209 | compatible = "snps,dw-apb-gpio"; | |
210 | reg = <0x0800 0x400>; | |
211 | #address-cells = <1>; | |
212 | #size-cells = <0>; | |
213 | ||
214 | portb: gpio-port@1 { | |
215 | compatible = "snps,dw-apb-gpio-port"; | |
216 | gpio-controller; | |
217 | #gpio-cells = <2>; | |
218 | snps,nr-gpios = <32>; | |
219 | reg = <0>; | |
220 | interrupt-controller; | |
221 | #interrupt-cells = <2>; | |
222 | interrupts = <1>; | |
223 | }; | |
224 | }; | |
225 | ||
226 | gpio2: gpio@0c00 { | |
227 | compatible = "snps,dw-apb-gpio"; | |
228 | reg = <0x0c00 0x400>; | |
229 | #address-cells = <1>; | |
230 | #size-cells = <0>; | |
231 | ||
232 | portc: gpio-port@2 { | |
233 | compatible = "snps,dw-apb-gpio-port"; | |
234 | gpio-controller; | |
235 | #gpio-cells = <2>; | |
236 | snps,nr-gpios = <32>; | |
237 | reg = <0>; | |
238 | interrupt-controller; | |
239 | #interrupt-cells = <2>; | |
240 | interrupts = <2>; | |
241 | }; | |
242 | }; | |
243 | ||
244 | gpio3: gpio@1000 { | |
245 | compatible = "snps,dw-apb-gpio"; | |
246 | reg = <0x1000 0x400>; | |
247 | #address-cells = <1>; | |
248 | #size-cells = <0>; | |
249 | ||
250 | portd: gpio-port@3 { | |
251 | compatible = "snps,dw-apb-gpio-port"; | |
252 | gpio-controller; | |
253 | #gpio-cells = <2>; | |
254 | snps,nr-gpios = <32>; | |
255 | reg = <0>; | |
256 | interrupt-controller; | |
257 | #interrupt-cells = <2>; | |
258 | interrupts = <3>; | |
259 | }; | |
260 | }; | |
261 | ||
99f3deb8 AT |
262 | i2c0: i2c@1400 { |
263 | compatible = "snps,designware-i2c"; | |
264 | #address-cells = <1>; | |
265 | #size-cells = <0>; | |
266 | reg = <0x1400 0x100>; | |
267 | interrupt-parent = <&aic>; | |
268 | interrupts = <4>; | |
269 | clocks = <&chip CLKID_CFG>; | |
270 | pinctrl-0 = <&twsi0_pmux>; | |
271 | pinctrl-names = "default"; | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
275 | i2c1: i2c@1800 { | |
276 | compatible = "snps,designware-i2c"; | |
277 | #address-cells = <1>; | |
278 | #size-cells = <0>; | |
279 | reg = <0x1800 0x100>; | |
280 | interrupt-parent = <&aic>; | |
281 | interrupts = <5>; | |
282 | clocks = <&chip CLKID_CFG>; | |
283 | pinctrl-0 = <&twsi1_pmux>; | |
284 | pinctrl-names = "default"; | |
285 | status = "disabled"; | |
286 | }; | |
287 | ||
374ddcbf AT |
288 | timer0: timer@2c00 { |
289 | compatible = "snps,dw-apb-timer"; | |
290 | reg = <0x2c00 0x14>; | |
414dcf8f | 291 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
292 | clock-names = "timer"; |
293 | interrupts = <8>; | |
294 | }; | |
295 | ||
296 | timer1: timer@2c14 { | |
297 | compatible = "snps,dw-apb-timer"; | |
298 | reg = <0x2c14 0x14>; | |
414dcf8f | 299 | clocks = <&chip CLKID_CFG>; |
374ddcbf | 300 | clock-names = "timer"; |
374ddcbf AT |
301 | }; |
302 | ||
303 | timer2: timer@2c28 { | |
304 | compatible = "snps,dw-apb-timer"; | |
305 | reg = <0x2c28 0x14>; | |
414dcf8f | 306 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
307 | clock-names = "timer"; |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | timer3: timer@2c3c { | |
312 | compatible = "snps,dw-apb-timer"; | |
313 | reg = <0x2c3c 0x14>; | |
414dcf8f | 314 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
315 | clock-names = "timer"; |
316 | status = "disabled"; | |
317 | }; | |
318 | ||
319 | timer4: timer@2c50 { | |
320 | compatible = "snps,dw-apb-timer"; | |
321 | reg = <0x2c50 0x14>; | |
414dcf8f | 322 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
323 | clock-names = "timer"; |
324 | status = "disabled"; | |
325 | }; | |
326 | ||
327 | timer5: timer@2c64 { | |
328 | compatible = "snps,dw-apb-timer"; | |
329 | reg = <0x2c64 0x14>; | |
414dcf8f | 330 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
331 | clock-names = "timer"; |
332 | status = "disabled"; | |
333 | }; | |
334 | ||
335 | timer6: timer@2c78 { | |
336 | compatible = "snps,dw-apb-timer"; | |
337 | reg = <0x2c78 0x14>; | |
414dcf8f | 338 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
339 | clock-names = "timer"; |
340 | status = "disabled"; | |
341 | }; | |
342 | ||
343 | timer7: timer@2c8c { | |
344 | compatible = "snps,dw-apb-timer"; | |
345 | reg = <0x2c8c 0x14>; | |
414dcf8f | 346 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
347 | clock-names = "timer"; |
348 | status = "disabled"; | |
349 | }; | |
350 | ||
351 | aic: interrupt-controller@3800 { | |
352 | compatible = "snps,dw-apb-ictl"; | |
353 | reg = <0x3800 0x30>; | |
354 | interrupt-controller; | |
355 | #interrupt-cells = <1>; | |
356 | interrupt-parent = <&gic>; | |
357 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
358 | }; | |
cedf57fc AT |
359 | |
360 | gpio4: gpio@5000 { | |
361 | compatible = "snps,dw-apb-gpio"; | |
362 | reg = <0x5000 0x400>; | |
363 | #address-cells = <1>; | |
364 | #size-cells = <0>; | |
365 | ||
366 | porte: gpio-port@4 { | |
367 | compatible = "snps,dw-apb-gpio-port"; | |
368 | gpio-controller; | |
369 | #gpio-cells = <2>; | |
370 | snps,nr-gpios = <32>; | |
371 | reg = <0>; | |
372 | }; | |
373 | }; | |
374 | ||
375 | gpio5: gpio@c000 { | |
376 | compatible = "snps,dw-apb-gpio"; | |
377 | reg = <0xc000 0x400>; | |
378 | #address-cells = <1>; | |
379 | #size-cells = <0>; | |
380 | ||
381 | portf: gpio-port@5 { | |
382 | compatible = "snps,dw-apb-gpio-port"; | |
383 | gpio-controller; | |
384 | #gpio-cells = <2>; | |
385 | snps,nr-gpios = <32>; | |
386 | reg = <0>; | |
387 | }; | |
388 | }; | |
374ddcbf AT |
389 | }; |
390 | ||
414dcf8f AB |
391 | chip: chip-control@ea0000 { |
392 | compatible = "marvell,berlin2q-chip-ctrl"; | |
393 | #clock-cells = <1>; | |
1e27a261 | 394 | #reset-cells = <2>; |
414dcf8f AB |
395 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
396 | clocks = <&refclk>; | |
397 | clock-names = "refclk"; | |
99f3deb8 AT |
398 | |
399 | twsi0_pmux: twsi0-pmux { | |
400 | groups = "G6"; | |
401 | function = "twsi0"; | |
402 | }; | |
403 | ||
404 | twsi1_pmux: twsi1-pmux { | |
405 | groups = "G7"; | |
406 | function = "twsi1"; | |
407 | }; | |
0bd4b346 SH |
408 | }; |
409 | ||
70a2b717 AT |
410 | ahci: sata@e90000 { |
411 | compatible = "marvell,berlin2q-ahci", "generic-ahci"; | |
412 | reg = <0xe90000 0x1000>; | |
413 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
414 | clocks = <&chip CLKID_SATA>; | |
415 | #address-cells = <1>; | |
416 | #size-cells = <0>; | |
417 | ||
418 | sata0: sata-port@0 { | |
419 | reg = <0>; | |
420 | phys = <&sata_phy 0>; | |
421 | status = "disabled"; | |
422 | }; | |
423 | ||
424 | sata1: sata-port@1 { | |
425 | reg = <1>; | |
426 | phys = <&sata_phy 1>; | |
427 | status = "disabled"; | |
428 | }; | |
429 | }; | |
430 | ||
431 | sata_phy: phy@e900a0 { | |
432 | compatible = "marvell,berlin2q-sata-phy"; | |
433 | reg = <0xe900a0 0x200>; | |
434 | clocks = <&chip CLKID_SATA>; | |
435 | #address-cells = <1>; | |
436 | #size-cells = <0>; | |
437 | #phy-cells = <1>; | |
438 | status = "disabled"; | |
439 | ||
440 | sata-phy@0 { | |
441 | reg = <0>; | |
442 | }; | |
443 | ||
444 | sata-phy@1 { | |
445 | reg = <1>; | |
446 | }; | |
447 | }; | |
448 | ||
c539711e AT |
449 | usb0: usb@ed0000 { |
450 | compatible = "chipidea,usb2"; | |
451 | reg = <0xed0000 0x10000>; | |
452 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
453 | clocks = <&chip CLKID_USB0>; | |
454 | phys = <&usb_phy0>; | |
455 | phy-names = "usb-phy"; | |
456 | status = "disabled"; | |
457 | }; | |
458 | ||
459 | usb1: usb@ee0000 { | |
460 | compatible = "chipidea,usb2"; | |
461 | reg = <0xee0000 0x10000>; | |
462 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
463 | clocks = <&chip CLKID_USB1>; | |
464 | phys = <&usb_phy1>; | |
465 | phy-names = "usb-phy"; | |
466 | status = "disabled"; | |
467 | }; | |
468 | ||
374ddcbf AT |
469 | apb@fc0000 { |
470 | compatible = "simple-bus"; | |
471 | #address-cells = <1>; | |
472 | #size-cells = <1>; | |
473 | ||
474 | ranges = <0 0xfc0000 0x10000>; | |
475 | interrupt-parent = <&sic>; | |
476 | ||
99f3deb8 AT |
477 | i2c2: i2c@7000 { |
478 | compatible = "snps,designware-i2c"; | |
479 | #address-cells = <1>; | |
480 | #size-cells = <0>; | |
481 | reg = <0x7000 0x100>; | |
482 | interrupt-parent = <&sic>; | |
483 | interrupts = <6>; | |
484 | clocks = <&refclk>; | |
485 | pinctrl-0 = <&twsi2_pmux>; | |
486 | pinctrl-names = "default"; | |
487 | status = "disabled"; | |
488 | }; | |
489 | ||
490 | i2c3: i2c@8000 { | |
491 | compatible = "snps,designware-i2c"; | |
492 | #address-cells = <1>; | |
493 | #size-cells = <0>; | |
494 | reg = <0x8000 0x100>; | |
495 | interrupt-parent = <&sic>; | |
496 | interrupts = <7>; | |
497 | clocks = <&refclk>; | |
498 | pinctrl-0 = <&twsi3_pmux>; | |
499 | pinctrl-names = "default"; | |
500 | status = "disabled"; | |
501 | }; | |
502 | ||
374ddcbf AT |
503 | uart0: uart@9000 { |
504 | compatible = "snps,dw-apb-uart"; | |
505 | reg = <0x9000 0x100>; | |
506 | interrupt-parent = <&sic>; | |
507 | interrupts = <8>; | |
414dcf8f | 508 | clocks = <&refclk>; |
374ddcbf | 509 | reg-shift = <2>; |
50cc24ff AT |
510 | pinctrl-0 = <&uart0_pmux>; |
511 | pinctrl-names = "default"; | |
374ddcbf AT |
512 | status = "disabled"; |
513 | }; | |
514 | ||
515 | uart1: uart@a000 { | |
516 | compatible = "snps,dw-apb-uart"; | |
517 | reg = <0xa000 0x100>; | |
518 | interrupt-parent = <&sic>; | |
519 | interrupts = <9>; | |
414dcf8f | 520 | clocks = <&refclk>; |
374ddcbf | 521 | reg-shift = <2>; |
50cc24ff AT |
522 | pinctrl-0 = <&uart1_pmux>; |
523 | pinctrl-names = "default"; | |
374ddcbf AT |
524 | status = "disabled"; |
525 | }; | |
526 | ||
50cc24ff AT |
527 | sysctrl: pin-controller@d000 { |
528 | compatible = "marvell,berlin2q-system-ctrl"; | |
529 | reg = <0xd000 0x100>; | |
530 | ||
531 | uart0_pmux: uart0-pmux { | |
532 | groups = "GSM12"; | |
533 | function = "uart0"; | |
534 | }; | |
535 | ||
536 | uart1_pmux: uart1-pmux { | |
537 | groups = "GSM14"; | |
538 | function = "uart1"; | |
539 | }; | |
99f3deb8 AT |
540 | |
541 | twsi2_pmux: twsi2-pmux { | |
542 | groups = "GSM13"; | |
543 | function = "twsi2"; | |
544 | }; | |
545 | ||
546 | twsi3_pmux: twsi3-pmux { | |
547 | groups = "GSM14"; | |
548 | function = "twsi3"; | |
549 | }; | |
50cc24ff AT |
550 | }; |
551 | ||
374ddcbf AT |
552 | sic: interrupt-controller@e000 { |
553 | compatible = "snps,dw-apb-ictl"; | |
554 | reg = <0xe000 0x30>; | |
555 | interrupt-controller; | |
556 | #interrupt-cells = <1>; | |
557 | interrupt-parent = <&gic>; | |
558 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
559 | }; | |
560 | }; | |
561 | }; | |
562 | }; |