[deliverable/linux.git] / arch / arm / boot / dts / dove.dtsi

/include/ "skeleton.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	compatible = "marvell,dove";
	model = "Marvell Armada 88AP510 SoC";
	interrupt-parent = <&intc>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "marvell,pj4a", "marvell,sheeva-v7";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	l2: l2-cache {
		compatible = "marvell,tauros2-cache";
		marvell,tauros2-cache-features = <0>;
	};

	i2c-mux {
		compatible = "i2c-mux-pinctrl";
		#address-cells = <1>;
		#size-cells = <0>;

		i2c-parent = <&i2c>;

		pinctrl-names = "i2c0", "i2c1", "i2c2";
		pinctrl-0 = <&pmx_i2cmux_0>;
		pinctrl-1 = <&pmx_i2cmux_1>;
		pinctrl-2 = <&pmx_i2cmux_2>;

		i2c0: i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";
		};

		i2c1: i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Requires pmx_i2c1 on i2c controller node */
			status = "disabled";
		};

		i2c2: i2c@2 {
			reg = <2>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Requires pmx_i2c2 on i2c controller node */
			status = "disabled";
		};
	};

	mbus {
		compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
		pcie-io-aperture  = <0xf2000000 0x00200000>; /*   2M I/O space */

		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000   /* MBUS regs  1M */
			  MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000   /* AXI  regs 16M */
			  MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000   /* BootROM  128M */
			  MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000   /* CESA SRAM  1M */
			  MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU  SRAM  1M */

		pcie: pcie-controller {
			compatible = "marvell,dove-pcie";
			status = "disabled";
			device_type = "pci";
			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&intc>;
			bus-range = <0x00 0xff>;

			ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
			          0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
				  0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0   /* Port 0.0 Mem */
				  0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0   /* Port 0.0 I/O */
				  0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0   /* Port 1.0 Mem */
				  0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */

			pcie0: pcie-port@0 {
				device_type = "pci";
				status = "disabled";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				clocks = <&gate_clk 4>;
				marvell,pcie-port = <0>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
				          0x81000000 0 0 0x81000000 0x1 0 1 0>;

				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &intc 16>;
			};

			pcie1: pcie-port@1 {
				device_type = "pci";
				status = "disabled";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				clocks = <&gate_clk 5>;
				marvell,pcie-port = <1>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
				          0x81000000 0 0 0x81000000 0x2 0 1 0>;

				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &intc 18>;
			};
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000   /* MBUS regs  1M */
				  0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000   /* AXI  regs 16M */
				  0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
				  0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */

			spi0: spi-ctrl@10600 {
				compatible = "marvell,orion-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <6>;
				reg = <0x10600 0x28>;
				clocks = <&core_clk 0>;
				pinctrl-0 = <&pmx_spi0>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c: i2c-ctrl@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <11>;
				clock-frequency = <400000>;
				timeout-ms = <1000>;
				clocks = <&core_clk 0>;
				status = "okay";
			};

			uart0: serial@12000 {
				compatible = "ns16550a";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <7>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "ns16550a";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <8>;
				clocks = <&core_clk 0>;
				pinctrl-0 = <&pmx_uart1>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@12200 {
				compatible = "ns16550a";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <9>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "ns16550a";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <10>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			spi1: spi-ctrl@14600 {
				compatible = "marvell,orion-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <5>;
				reg = <0x14600 0x28>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			mbusc: mbus-ctrl@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x80>, <0x800100 0x8>;
			};

			sysc: system-ctrl@20000 {
				compatible = "marvell,orion-system-controller";
				reg = <0x20000 0x110>;
			};

			bridge_intc: bridge-interrupt-ctrl@20110 {
				compatible = "marvell,orion-bridge-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x20110 0x8>;
				interrupts = <0>;
				marvell,#interrupts = <5>;
			};

			intc: main-interrupt-ctrl@20200 {
				compatible = "marvell,orion-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x20200 0x10>, <0x20210 0x10>;
			};

			timer: timer@20300 {
				compatible = "marvell,orion-timer";
				reg = <0x20300 0x20>;
				interrupt-parent = <&bridge_intc>;
				interrupts = <1>, <2>;
				clocks = <&core_clk 0>;
			};

			watchdog@20300 {
				compatible = "marvell,orion-wdt";
				reg = <0x20300 0x28>, <0x20108 0x4>;
				interrupt-parent = <&bridge_intc>;
				interrupts = <3>;
				clocks = <&core_clk 0>;
			};

			crypto: crypto-engine@30000 {
				compatible = "marvell,orion-crypto";
				reg = <0x30000 0x10000>,
				      <0xffffe000 0x800>;
				reg-names = "regs", "sram";
				interrupts = <31>;
				clocks = <&gate_clk 15>;
				status = "okay";
			};

			ehci0: usb-host@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x1000>;
				interrupts = <24>;
				clocks = <&gate_clk 0>;
				status = "okay";
			};

			ehci1: usb-host@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x1000>;
				interrupts = <25>;
				clocks = <&gate_clk 1>;
				status = "okay";
			};

			xor0: dma-engine@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gate_clk 23>;
				status = "okay";

				channel0 {
					interrupts = <39>;
					dmacap,memcpy;
					dmacap,xor;
				};

				channel1 {
					interrupts = <40>;
					dmacap,memcpy;
					dmacap,xor;
				};
			};

			xor1: dma-engine@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gate_clk 24>;
				status = "okay";

				channel0 {
					interrupts = <42>;
					dmacap,memcpy;
					dmacap,xor;
				};

				channel1 {
					interrupts = <43>;
					dmacap,memcpy;
					dmacap,xor;
				};
			};

			sdio1: sdio-host@90000 {
				compatible = "marvell,dove-sdhci";
				reg = <0x90000 0x100>;
				interrupts = <36>, <38>;
				clocks = <&gate_clk 9>;
				pinctrl-0 = <&pmx_sdio1>;
				pinctrl-names = "default";
				status = "disabled";
			};

			eth: ethernet-ctrl@72000 {
				compatible = "marvell,orion-eth";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x72000 0x4000>;
				clocks = <&gate_clk 2>;
				marvell,tx-checksum-limit = <1600>;
				status = "disabled";

				ethernet-port@0 {
					compatible = "marvell,orion-eth-port";
					reg = <0>;
					interrupts = <29>;
					/* overwrite MAC address in bootloader */
					local-mac-address = [00 00 00 00 00 00];
					phy-handle = <&ethphy>;
				};
			};

			mdio: mdio-bus@72004 {
				compatible = "marvell,orion-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x72004 0x84>;
				interrupts = <30>;
				clocks = <&gate_clk 2>;
				status = "disabled";

				ethphy: ethernet-phy {
					/* set phy address in board file */
				};
			};

			sdio0: sdio-host@92000 {
				compatible = "marvell,dove-sdhci";
				reg = <0x92000 0x100>;
				interrupts = <35>, <37>;
				clocks = <&gate_clk 8>;
				pinctrl-0 = <&pmx_sdio0>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sata0: sata-host@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x2400>;
				interrupts = <62>;
				clocks = <&gate_clk 3>;
				phys = <&sata_phy0>;
				phy-names = "port0";
				nr-ports = <1>;
				status = "disabled";
			};

			sata_phy0: sata-phy@a2000 {
				compatible = "marvell,mvebu-sata-phy";
				reg = <0xa2000 0x0334>;
				clocks = <&gate_clk 3>;
				clock-names = "sata";
				#phy-cells = <0>;
				status = "ok";
			};

			audio0: audio-controller@b0000 {
				compatible = "marvell,dove-audio";
				reg = <0xb0000 0x2210>;
				interrupts = <19>, <20>;
				clocks = <&gate_clk 12>;
				clock-names = "internal";
				status = "disabled";
			};

			audio1: audio-controller@b4000 {
				compatible = "marvell,dove-audio";
				reg = <0xb4000 0x2210>;
				interrupts = <21>, <22>;
				clocks = <&gate_clk 13>;
				clock-names = "internal";
				status = "disabled";
			};

			thermal: thermal-diode@d001c {
				compatible = "marvell,dove-thermal";
				reg = <0xd001c 0x0c>, <0xd005c 0x08>;
			};

			gate_clk: clock-gating-ctrl@d0038 {
				compatible = "marvell,dove-gating-clock";
				reg = <0xd0038 0x4>;
				clocks = <&core_clk 0>;
				#clock-cells = <1>;
			};

			pinctrl: pin-ctrl@d0200 {
				compatible = "marvell,dove-pinctrl";
				reg = <0xd0200 0x14>,
				      <0xd0440 0x04>;
				clocks = <&gate_clk 22>;

				pmx_gpio_0: pmx-gpio-0 {
					marvell,pins = "mpp0";
					marvell,function = "gpio";
				};

				pmx_gpio_1: pmx-gpio-1 {
					marvell,pins = "mpp1";
					marvell,function = "gpio";
				};

				pmx_gpio_2: pmx-gpio-2 {
					marvell,pins = "mpp2";
					marvell,function = "gpio";
				};

				pmx_gpio_3: pmx-gpio-3 {
					marvell,pins = "mpp3";
					marvell,function = "gpio";
				};

				pmx_gpio_4: pmx-gpio-4 {
					marvell,pins = "mpp4";
					marvell,function = "gpio";
				};

				pmx_gpio_5: pmx-gpio-5 {
					marvell,pins = "mpp5";
					marvell,function = "gpio";
				};

				pmx_gpio_6: pmx-gpio-6 {
					marvell,pins = "mpp6";
					marvell,function = "gpio";
				};

				pmx_gpio_7: pmx-gpio-7 {
					marvell,pins = "mpp7";
					marvell,function = "gpio";
				};

				pmx_gpio_8: pmx-gpio-8 {
					marvell,pins = "mpp8";
					marvell,function = "gpio";
				};

				pmx_gpio_9: pmx-gpio-9 {
					marvell,pins = "mpp9";
					marvell,function = "gpio";
				};

				pmx_pcie1_clkreq: pmx-pcie1-clkreq {
					marvell,pins = "mpp9";
					marvell,function = "pex1";
				};

				pmx_gpio_10: pmx-gpio-10 {
					marvell,pins = "mpp10";
					marvell,function = "gpio";
				};

				pmx_gpio_11: pmx-gpio-11 {
					marvell,pins = "mpp11";
					marvell,function = "gpio";
				};

				pmx_pcie0_clkreq: pmx-pcie0-clkreq {
					marvell,pins = "mpp11";
					marvell,function = "pex0";
				};

				pmx_gpio_12: pmx-gpio-12 {
					marvell,pins = "mpp12";
					marvell,function = "gpio";
				};

				pmx_gpio_13: pmx-gpio-13 {
					marvell,pins = "mpp13";
					marvell,function = "gpio";
				};

				pmx_audio1_extclk: pmx-audio1-extclk {
					marvell,pins = "mpp13";
					marvell,function = "audio1";
				};

				pmx_gpio_14: pmx-gpio-14 {
					marvell,pins = "mpp14";
					marvell,function = "gpio";
				};

				pmx_gpio_15: pmx-gpio-15 {
					marvell,pins = "mpp15";
					marvell,function = "gpio";
				};

				pmx_gpio_16: pmx-gpio-16 {
					marvell,pins = "mpp16";
					marvell,function = "gpio";
				};

				pmx_gpio_17: pmx-gpio-17 {
					marvell,pins = "mpp17";
					marvell,function = "gpio";
				};

				pmx_gpio_18: pmx-gpio-18 {
					marvell,pins = "mpp18";
					marvell,function = "gpio";
				};

				pmx_gpio_19: pmx-gpio-19 {
					marvell,pins = "mpp19";
					marvell,function = "gpio";
				};

				pmx_gpio_20: pmx-gpio-20 {
					marvell,pins = "mpp20";
					marvell,function = "gpio";
				};

				pmx_gpio_21: pmx-gpio-21 {
					marvell,pins = "mpp21";
					marvell,function = "gpio";
				};

				pmx_camera: pmx-camera {
					marvell,pins = "mpp_camera";
					marvell,function = "camera";
				};

				pmx_camera_gpio: pmx-camera-gpio {
					marvell,pins = "mpp_camera";
					marvell,function = "gpio";
				};

				pmx_sdio0: pmx-sdio0 {
					marvell,pins = "mpp_sdio0";
					marvell,function = "sdio0";
				};

				pmx_sdio0_gpio: pmx-sdio0-gpio {
					marvell,pins = "mpp_sdio0";
					marvell,function = "gpio";
				};

				pmx_sdio1: pmx-sdio1 {
					marvell,pins = "mpp_sdio1";
					marvell,function = "sdio1";
				};

				pmx_sdio1_gpio: pmx-sdio1-gpio {
					marvell,pins = "mpp_sdio1";
					marvell,function = "gpio";
				};

				pmx_audio1_gpio: pmx-audio1-gpio {
					marvell,pins = "mpp_audio1";
					marvell,function = "gpio";
				};

				pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
					marvell,pins = "mpp_audio1";
					marvell,function = "i2s1/spdifo";
				};

				pmx_spi0: pmx-spi0 {
					marvell,pins = "mpp_spi0";
					marvell,function = "spi0";
				};

				pmx_spi0_gpio: pmx-spi0-gpio {
					marvell,pins = "mpp_spi0";
					marvell,function = "gpio";
				};

				pmx_spi1_4_7: pmx-spi1-4-7 {
					marvell,pins = "mpp4", "mpp5",
						"mpp6", "mpp7";
					marvell,function = "spi1";
				};

				pmx_spi1_20_23: pmx-spi1-20-23 {
					marvell,pins = "mpp20", "mpp21",
						"mpp22", "mpp23";
					marvell,function = "spi1";
				};

				pmx_uart1: pmx-uart1 {
					marvell,pins = "mpp_uart1";
					marvell,function = "uart1";
				};

				pmx_uart1_gpio: pmx-uart1-gpio {
					marvell,pins = "mpp_uart1";
					marvell,function = "gpio";
				};

				pmx_nand: pmx-nand {
					marvell,pins = "mpp_nand";
					marvell,function = "nand";
				};

				pmx_nand_gpo: pmx-nand-gpo {
					marvell,pins = "mpp_nand";
					marvell,function = "gpo";
				};

				pmx_i2c1: pmx-i2c1 {
					marvell,pins = "mpp17", "mpp19";
					marvell,function = "twsi";
				};

				pmx_i2c2: pmx-i2c2 {
					marvell,pins = "mpp_audio1";
					marvell,function = "twsi";
				};

				pmx_ssp_i2c2: pmx-ssp-i2c2 {
					marvell,pins = "mpp_audio1";
					marvell,function = "ssp/twsi";
				};

				pmx_i2cmux_0: pmx-i2cmux-0 {
					marvell,pins = "twsi";
					marvell,function = "twsi-opt1";
				};

				pmx_i2cmux_1: pmx-i2cmux-1 {
					marvell,pins = "twsi";
					marvell,function = "twsi-opt2";
				};

				pmx_i2cmux_2: pmx-i2cmux-2 {
					marvell,pins = "twsi";
					marvell,function = "twsi-opt3";
				};
			};

			core_clk: core-clocks@d0214 {
				compatible = "marvell,dove-core-clock";
				reg = <0xd0214 0x4>;
				#clock-cells = <1>;
			};

			gpio0: gpio-ctrl@d0400 {
				compatible = "marvell,orion-gpio";
				#gpio-cells = <2>;
				gpio-controller;
				reg = <0xd0400 0x20>;
				ngpios = <32>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <12>, <13>, <14>, <60>;
			};

			gpio1: gpio-ctrl@d0420 {
				compatible = "marvell,orion-gpio";
				#gpio-cells = <2>;
				gpio-controller;
				reg = <0xd0420 0x20>;
				ngpios = <32>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <61>;
			};

			rtc: real-time-clock@d8500 {
				compatible = "marvell,orion-rtc";
				reg = <0xd8500 0x20>;
			};

			gconf: global-config@e802c {
				compatible = "marvell,dove-global-config",
				             "syscon";
				reg = <0xe802c 0x14>;
			};

			gpio2: gpio-ctrl@e8400 {
				compatible = "marvell,orion-gpio";
				#gpio-cells = <2>;
				gpio-controller;
				reg = <0xe8400 0x0c>;
				ngpios = <8>;
			};

			lcd1: lcd-controller@810000 {
				compatible = "marvell,dove-lcd";
				reg = <0x810000 0x1000>;
				interrupts = <46>;
				status = "disabled";
			};

			lcd0: lcd-controller@820000 {
				compatible = "marvell,dove-lcd";
				reg = <0x820000 0x1000>;
				interrupts = <47>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
80a8b54b SH	1	/include/ "skeleton.dtsi"
80a8b54b SH	2
eb472c4c SH	3	#include <dt-bindings/gpio/gpio.h>
	4	#include <dt-bindings/interrupt-controller/irq.h>
	5
6953af77 SH	6	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
6953af77 SH	7
80a8b54b SH	8	/ {
	9	compatible = "marvell,dove";
	10	model = "Marvell Armada 88AP510 SoC";
0ad44659	11	interrupt-parent = <&intc>;
80a8b54b	12
9139acd1 SH	13	aliases {
	14	gpio0 = &gpio0;
	15	gpio1 = &gpio1;
	16	gpio2 = &gpio2;
	17	};
	18
2d299834 SH	19	cpus {
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	cpu0: cpu@0 {
	24	compatible = "marvell,pj4a", "marvell,sheeva-v7";
	25	device_type = "cpu";
	26	next-level-cache = <&l2>;
	27	reg = <0>;
	28	};
	29	};
	30
	31	l2: l2-cache {
	32	compatible = "marvell,tauros2-cache";
	33	marvell,tauros2-cache-features = <0>;
	34	};
	35
7ec7e546 SH	36	i2c-mux {
	37	compatible = "i2c-mux-pinctrl";
	38	#address-cells = <1>;
	39	#size-cells = <0>;
	40
	41	i2c-parent = <&i2c>;
	42
	43	pinctrl-names = "i2c0", "i2c1", "i2c2";
	44	pinctrl-0 = <&pmx_i2cmux_0>;
	45	pinctrl-1 = <&pmx_i2cmux_1>;
	46	pinctrl-2 = <&pmx_i2cmux_2>;
	47
	48	i2c0: i2c@0 {
	49	reg = <0>;
	50	#address-cells = <1>;
	51	#size-cells = <0>;
	52	status = "okay";
	53	};
	54
	55	i2c1: i2c@1 {
	56	reg = <1>;
	57	#address-cells = <1>;
	58	#size-cells = <0>;
	59	/* Requires pmx_i2c1 on i2c controller node */
	60	status = "disabled";
	61	};
	62
	63	i2c2: i2c@2 {
	64	reg = <2>;
	65	#address-cells = <1>;
	66	#size-cells = <0>;
	67	/* Requires pmx_i2c2 on i2c controller node */
	68	status = "disabled";
	69	};
	70	};
	71
960ee4e7 SH	72	mbus {
	73	compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
	74	#address-cells = <2>;
	75	#size-cells = <1>;
	76	controller = <&mbusc>;
	77	pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
	78	pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
	79
	80	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
	81	MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
	82	MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
	83	MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
	84	MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
4c3f6b86	85
74ecaa40 SH	86	pcie: pcie-controller {
	87	compatible = "marvell,dove-pcie";
	88	status = "disabled";
	89	device_type = "pci";
	90	#address-cells = <3>;
	91	#size-cells = <2>;
	92
	93	msi-parent = <&intc>;
	94	bus-range = <0x00 0xff>;
	95
	96	ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
	97	0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
	98	0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
	99	0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
	100	0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
	101	0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
	102
83ce82ee	103	pcie0: pcie-port@0 {
74ecaa40 SH	104	device_type = "pci";
	105	status = "disabled";
	106	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	107	reg = <0x0800 0 0 0 0>;
	108	clocks = <&gate_clk 4>;
	109	marvell,pcie-port = <0>;
	110
	111	#address-cells = <3>;
	112	#size-cells = <2>;
	113	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	114	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	115
	116	#interrupt-cells = <1>;
	117	interrupt-map-mask = <0 0 0 0>;
	118	interrupt-map = <0 0 0 0 &intc 16>;
	119	};
	120
83ce82ee	121	pcie1: pcie-port@1 {
74ecaa40 SH	122	device_type = "pci";
	123	status = "disabled";
	124	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
	125	reg = <0x1000 0 0 0 0>;
	126	clocks = <&gate_clk 5>;
	127	marvell,pcie-port = <1>;
	128
	129	#address-cells = <3>;
	130	#size-cells = <2>;
	131	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	132	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	133
	134	#interrupt-cells = <1>;
	135	interrupt-map-mask = <0 0 0 0>;
	136	interrupt-map = <0 0 0 0 &intc 18>;
	137	};
	138	};
	139
0ad44659 SH	140	internal-regs {
0ad44659 SH	141	compatible = "simple-bus";
4c3f6b86	142	#address-cells = <1>;
0ad44659 SH	143	#size-cells = <1>;
	144	ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
	145	0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
	146	0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
	147	0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
	148
b31b3211 JC	149	spi0: spi-ctrl@10600 {
	150	compatible = "marvell,orion-spi";
	151	#address-cells = <1>;
	152	#size-cells = <0>;
	153	cell-index = <0>;
	154	interrupts = <6>;
	155	reg = <0x10600 0x28>;
0ad44659	156	clocks = <&core_clk 0>;
b31b3211 JC	157	pinctrl-0 = <&pmx_spi0>;
	158	pinctrl-names = "default";
	159	status = "disabled";
0ad44659 SH	160	};
0ad44659 SH	161
7ec7e546	162	i2c: i2c-ctrl@11000 {
b31b3211 JC	163	compatible = "marvell,mv64xxx-i2c";
	164	reg = <0x11000 0x20>;
	165	#address-cells = <1>;
	166	#size-cells = <0>;
	167	interrupts = <11>;
	168	clock-frequency = <400000>;
	169	timeout-ms = <1000>;
0ad44659	170	clocks = <&core_clk 0>;
7ec7e546	171	status = "okay";
0ad44659 SH	172	};
	173
	174	uart0: serial@12000 {
	175	compatible = "ns16550a";
	176	reg = <0x12000 0x100>;
	177	reg-shift = <2>;
	178	interrupts = <7>;
	179	clocks = <&core_clk 0>;
	180	status = "disabled";
	181	};
	182
	183	uart1: serial@12100 {
	184	compatible = "ns16550a";
	185	reg = <0x12100 0x100>;
	186	reg-shift = <2>;
	187	interrupts = <8>;
	188	clocks = <&core_clk 0>;
	189	pinctrl-0 = <&pmx_uart1>;
	190	pinctrl-names = "default";
	191	status = "disabled";
	192	};
	193
	194	uart2: serial@12200 {
	195	compatible = "ns16550a";
a74cd13b	196	reg = <0x12200 0x100>;
0ad44659 SH	197	reg-shift = <2>;
	198	interrupts = <9>;
	199	clocks = <&core_clk 0>;
	200	status = "disabled";
	201	};
	202
	203	uart3: serial@12300 {
	204	compatible = "ns16550a";
a74cd13b	205	reg = <0x12300 0x100>;
0ad44659 SH	206	reg-shift = <2>;
	207	interrupts = <10>;
	208	clocks = <&core_clk 0>;
	209	status = "disabled";
	210	};
	211
b31b3211 JC	212	spi1: spi-ctrl@14600 {
	213	compatible = "marvell,orion-spi";
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	cell-index = <1>;
	217	interrupts = <5>;
	218	reg = <0x14600 0x28>;
	219	clocks = <&core_clk 0>;
	220	status = "disabled";
	221	};
	222
	223	mbusc: mbus-ctrl@20000 {
	224	compatible = "marvell,mbus-controller";
	225	reg = <0x20000 0x80>, <0x800100 0x8>;
	226	};
	227
a16761ac SH	228	sysc: system-ctrl@20000 {
	229	compatible = "marvell,orion-system-controller";
	230	reg = <0x20000 0x110>;
	231	};
	232
b31b3211 JC	233	bridge_intc: bridge-interrupt-ctrl@20110 {
b31b3211 JC	234	compatible = "marvell,orion-bridge-intc";
0ad44659	235	interrupt-controller;
b31b3211 JC	236	#interrupt-cells = <1>;
	237	reg = <0x20110 0x8>;
	238	interrupts = <0>;
	239	marvell,#interrupts = <5>;
0ad44659 SH	240	};
0ad44659 SH	241
b31b3211 JC	242	intc: main-interrupt-ctrl@20200 {
b31b3211 JC	243	compatible = "marvell,orion-intc";
0ad44659	244	interrupt-controller;
b31b3211 JC	245	#interrupt-cells = <1>;
b31b3211 JC	246	reg = <0x20200 0x10>, <0x20210 0x10>;
0ad44659 SH	247	};
0ad44659 SH	248
b31b3211 JC	249	timer: timer@20300 {
	250	compatible = "marvell,orion-timer";
	251	reg = <0x20300 0x20>;
	252	interrupt-parent = <&bridge_intc>;
	253	interrupts = <1>, <2>;
	254	clocks = <&core_clk 0>;
	255	};
	256
7a5b293f EG	257	watchdog@20300 {
	258	compatible = "marvell,orion-wdt";
	259	reg = <0x20300 0x28>, <0x20108 0x4>;
	260	interrupt-parent = <&bridge_intc>;
	261	interrupts = <3>;
	262	clocks = <&core_clk 0>;
	263	};
	264
b31b3211 JC	265	crypto: crypto-engine@30000 {
	266	compatible = "marvell,orion-crypto";
	267	reg = <0x30000 0x10000>,
	268	<0xffffe000 0x800>;
	269	reg-names = "regs", "sram";
	270	interrupts = <31>;
	271	clocks = <&gate_clk 15>;
	272	status = "okay";
	273	};
	274
	275	ehci0: usb-host@50000 {
	276	compatible = "marvell,orion-ehci";
	277	reg = <0x50000 0x1000>;
	278	interrupts = <24>;
	279	clocks = <&gate_clk 0>;
	280	status = "okay";
	281	};
	282
	283	ehci1: usb-host@51000 {
	284	compatible = "marvell,orion-ehci";
	285	reg = <0x51000 0x1000>;
	286	interrupts = <25>;
	287	clocks = <&gate_clk 1>;
	288	status = "okay";
	289	};
	290
	291	xor0: dma-engine@60800 {
	292	compatible = "marvell,orion-xor";
	293	reg = <0x60800 0x100
	294	0x60a00 0x100>;
	295	clocks = <&gate_clk 23>;
	296	status = "okay";
	297
	298	channel0 {
	299	interrupts = <39>;
	300	dmacap,memcpy;
	301	dmacap,xor;
	302	};
	303
	304	channel1 {
	305	interrupts = <40>;
	306	dmacap,memcpy;
	307	dmacap,xor;
	308	};
	309	};
	310
	311	xor1: dma-engine@60900 {
	312	compatible = "marvell,orion-xor";
	313	reg = <0x60900 0x100
	314	0x60b00 0x100>;
	315	clocks = <&gate_clk 24>;
	316	status = "okay";
	317
	318	channel0 {
	319	interrupts = <42>;
	320	dmacap,memcpy;
	321	dmacap,xor;
	322	};
	323
	324	channel1 {
	325	interrupts = <43>;
	326	dmacap,memcpy;
	327	dmacap,xor;
	328	};
329	};
330
331	sdio1: sdio-host@90000 {
332	compatible = "marvell,dove-sdhci";
333	reg = <0x90000 0x100>;
334	interrupts = <36>, <38>;
335	clocks = <&gate_clk 9>;
336	pinctrl-0 = <&pmx_sdio1>;
337	pinctrl-names = "default";
338	status = "disabled";
339	};
340
341	eth: ethernet-ctrl@72000 {
342	compatible = "marvell,orion-eth";
343	#address-cells = <1>;
344	#size-cells = <0>;
345	reg = <0x72000 0x4000>;
346	clocks = <&gate_clk 2>;
347	marvell,tx-checksum-limit = <1600>;
348	status = "disabled";
349
350	ethernet-port@0 {
b31b3211 JC	351	compatible = "marvell,orion-eth-port";
	352	reg = <0>;
	353	interrupts = <29>;
	354	/* overwrite MAC address in bootloader */
	355	local-mac-address = [00 00 00 00 00 00];
	356	phy-handle = <&ethphy>;
	357	};
	358	};
	359
	360	mdio: mdio-bus@72004 {
	361	compatible = "marvell,orion-mdio";
	362	#address-cells = <1>;
	363	#size-cells = <0>;
	364	reg = <0x72004 0x84>;
	365	interrupts = <30>;
	366	clocks = <&gate_clk 2>;
	367	status = "disabled";
	368
	369	ethphy: ethernet-phy {
b31b3211 JC	370	/* set phy address in board file */
	371	};
	372	};
	373
	374	sdio0: sdio-host@92000 {
	375	compatible = "marvell,dove-sdhci";
	376	reg = <0x92000 0x100>;
	377	interrupts = <35>, <37>;
	378	clocks = <&gate_clk 8>;
	379	pinctrl-0 = <&pmx_sdio0>;
	380	pinctrl-names = "default";
	381	status = "disabled";
	382	};
	383
	384	sata0: sata-host@a0000 {
	385	compatible = "marvell,orion-sata";
	386	reg = <0xa0000 0x2400>;
	387	interrupts = <62>;
	388	clocks = <&gate_clk 3>;
0ad82cd8 AL	389	phys = <&sata_phy0>;
0ad82cd8 AL	390	phy-names = "port0";
b31b3211 JC	391	nr-ports = <1>;
	392	status = "disabled";
	393	};
	394
0ad82cd8 AL	395	sata_phy0: sata-phy@a2000 {
	396	compatible = "marvell,mvebu-sata-phy";
	397	reg = <0xa2000 0x0334>;
	398	clocks = <&gate_clk 3>;
	399	clock-names = "sata";
	400	#phy-cells = <0>;
	401	status = "ok";
	402	};
	403
b31b3211 JC	404	audio0: audio-controller@b0000 {
	405	compatible = "marvell,dove-audio";
	406	reg = <0xb0000 0x2210>;
	407	interrupts = <19>, <20>;
	408	clocks = <&gate_clk 12>;
	409	clock-names = "internal";
	410	status = "disabled";
	411	};
	412
	413	audio1: audio-controller@b4000 {
	414	compatible = "marvell,dove-audio";
	415	reg = <0xb4000 0x2210>;
	416	interrupts = <21>, <22>;
	417	clocks = <&gate_clk 13>;
	418	clock-names = "internal";
	419	status = "disabled";
	420	};
	421
	422	thermal: thermal-diode@d001c {
	423	compatible = "marvell,dove-thermal";
	424	reg = <0xd001c 0x0c>, <0xd005c 0x08>;
	425	};
	426
	427	gate_clk: clock-gating-ctrl@d0038 {
	428	compatible = "marvell,dove-gating-clock";
	429	reg = <0xd0038 0x4>;
	430	clocks = <&core_clk 0>;
	431	#clock-cells = <1>;
	432	};
	433
0ad44659 SH	434	pinctrl: pin-ctrl@d0200 {
0ad44659 SH	435	compatible = "marvell,dove-pinctrl";
5db26374	436	reg = <0xd0200 0x14>,
df76299f	437	<0xd0440 0x04>;
0ad44659 SH	438	clocks = <&gate_clk 22>;
	439
	440	pmx_gpio_0: pmx-gpio-0 {
	441	marvell,pins = "mpp0";
	442	marvell,function = "gpio";
	443	};
	444
	445	pmx_gpio_1: pmx-gpio-1 {
	446	marvell,pins = "mpp1";
	447	marvell,function = "gpio";
	448	};
	449
	450	pmx_gpio_2: pmx-gpio-2 {
	451	marvell,pins = "mpp2";
	452	marvell,function = "gpio";
	453	};
	454
	455	pmx_gpio_3: pmx-gpio-3 {
	456	marvell,pins = "mpp3";
	457	marvell,function = "gpio";
	458	};
	459
	460	pmx_gpio_4: pmx-gpio-4 {
	461	marvell,pins = "mpp4";
	462	marvell,function = "gpio";
	463	};
	464
	465	pmx_gpio_5: pmx-gpio-5 {
	466	marvell,pins = "mpp5";
	467	marvell,function = "gpio";
	468	};
	469
	470	pmx_gpio_6: pmx-gpio-6 {
	471	marvell,pins = "mpp6";
	472	marvell,function = "gpio";
	473	};
	474
	475	pmx_gpio_7: pmx-gpio-7 {
	476	marvell,pins = "mpp7";
	477	marvell,function = "gpio";
	478	};
	479
	480	pmx_gpio_8: pmx-gpio-8 {
	481	marvell,pins = "mpp8";
	482	marvell,function = "gpio";
	483	};
	484
	485	pmx_gpio_9: pmx-gpio-9 {
	486	marvell,pins = "mpp9";
	487	marvell,function = "gpio";
	488	};
	489
1a1b9d25 SH	490	pmx_pcie1_clkreq: pmx-pcie1-clkreq {
	491	marvell,pins = "mpp9";
	492	marvell,function = "pex1";
	493	};
	494
0ad44659 SH	495	pmx_gpio_10: pmx-gpio-10 {
	496	marvell,pins = "mpp10";
	497	marvell,function = "gpio";
	498	};
	499
	500	pmx_gpio_11: pmx-gpio-11 {
	501	marvell,pins = "mpp11";
	502	marvell,function = "gpio";
	503	};
	504
1a1b9d25 SH	505	pmx_pcie0_clkreq: pmx-pcie0-clkreq {
	506	marvell,pins = "mpp11";
	507	marvell,function = "pex0";
	508	};
	509
0ad44659 SH	510	pmx_gpio_12: pmx-gpio-12 {
	511	marvell,pins = "mpp12";
	512	marvell,function = "gpio";
	513	};
	514
	515	pmx_gpio_13: pmx-gpio-13 {
	516	marvell,pins = "mpp13";
	517	marvell,function = "gpio";
	518	};
	519
34ea5342 JFM	520	pmx_audio1_extclk: pmx-audio1-extclk {
	521	marvell,pins = "mpp13";
	522	marvell,function = "audio1";
	523	};
	524
0ad44659 SH	525	pmx_gpio_14: pmx-gpio-14 {
	526	marvell,pins = "mpp14";
	527	marvell,function = "gpio";
	528	};
	529
	530	pmx_gpio_15: pmx-gpio-15 {
	531	marvell,pins = "mpp15";
	532	marvell,function = "gpio";
	533	};
	534
	535	pmx_gpio_16: pmx-gpio-16 {
	536	marvell,pins = "mpp16";
	537	marvell,function = "gpio";
	538	};
	539
	540	pmx_gpio_17: pmx-gpio-17 {
	541	marvell,pins = "mpp17";
	542	marvell,function = "gpio";
	543	};
	544
	545	pmx_gpio_18: pmx-gpio-18 {
	546	marvell,pins = "mpp18";
	547	marvell,function = "gpio";
	548	};
	549
	550	pmx_gpio_19: pmx-gpio-19 {
	551	marvell,pins = "mpp19";
	552	marvell,function = "gpio";
	553	};
	554
	555	pmx_gpio_20: pmx-gpio-20 {
	556	marvell,pins = "mpp20";
	557	marvell,function = "gpio";
	558	};
	559
	560	pmx_gpio_21: pmx-gpio-21 {
	561	marvell,pins = "mpp21";
	562	marvell,function = "gpio";
	563	};
	564
	565	pmx_camera: pmx-camera {
	566	marvell,pins = "mpp_camera";
	567	marvell,function = "camera";
	568	};
	569
	570	pmx_camera_gpio: pmx-camera-gpio {
	571	marvell,pins = "mpp_camera";
	572	marvell,function = "gpio";
	573	};
	574
	575	pmx_sdio0: pmx-sdio0 {
	576	marvell,pins = "mpp_sdio0";
	577	marvell,function = "sdio0";
	578	};
	579
	580	pmx_sdio0_gpio: pmx-sdio0-gpio {
	581	marvell,pins = "mpp_sdio0";
	582	marvell,function = "gpio";
	583	};
	584
	585	pmx_sdio1: pmx-sdio1 {
	586	marvell,pins = "mpp_sdio1";
	587	marvell,function = "sdio1";
	588	};
589
590	pmx_sdio1_gpio: pmx-sdio1-gpio {
591	marvell,pins = "mpp_sdio1";
592	marvell,function = "gpio";
593	};
594
595	pmx_audio1_gpio: pmx-audio1-gpio {
596	marvell,pins = "mpp_audio1";
597	marvell,function = "gpio";
598	};
599
34ea5342 JFM	600	pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
	601	marvell,pins = "mpp_audio1";
	602	marvell,function = "i2s1/spdifo";
	603	};
	604
0ad44659 SH	605	pmx_spi0: pmx-spi0 {
	606	marvell,pins = "mpp_spi0";
	607	marvell,function = "spi0";
	608	};
	609
	610	pmx_spi0_gpio: pmx-spi0-gpio {
	611	marvell,pins = "mpp_spi0";
	612	marvell,function = "gpio";
	613	};
	614
1a1b9d25 SH	615	pmx_spi1_4_7: pmx-spi1-4-7 {
	616	marvell,pins = "mpp4", "mpp5",
	617	"mpp6", "mpp7";
	618	marvell,function = "spi1";
	619	};
	620
	621	pmx_spi1_20_23: pmx-spi1-20-23 {
	622	marvell,pins = "mpp20", "mpp21",
	623	"mpp22", "mpp23";
	624	marvell,function = "spi1";
	625	};
	626
0ad44659 SH	627	pmx_uart1: pmx-uart1 {
	628	marvell,pins = "mpp_uart1";
	629	marvell,function = "uart1";
	630	};
	631
	632	pmx_uart1_gpio: pmx-uart1-gpio {
	633	marvell,pins = "mpp_uart1";
	634	marvell,function = "gpio";
	635	};
	636
	637	pmx_nand: pmx-nand {
	638	marvell,pins = "mpp_nand";
	639	marvell,function = "nand";
	640	};
	641
	642	pmx_nand_gpo: pmx-nand-gpo {
	643	marvell,pins = "mpp_nand";
	644	marvell,function = "gpo";
	645	};
1a1b9d25 SH	646
	647	pmx_i2c1: pmx-i2c1 {
	648	marvell,pins = "mpp17", "mpp19";
	649	marvell,function = "twsi";
	650	};
	651
	652	pmx_i2c2: pmx-i2c2 {
	653	marvell,pins = "mpp_audio1";
	654	marvell,function = "twsi";
	655	};
	656
	657	pmx_ssp_i2c2: pmx-ssp-i2c2 {
	658	marvell,pins = "mpp_audio1";
	659	marvell,function = "ssp/twsi";
	660	};
	661
	662	pmx_i2cmux_0: pmx-i2cmux-0 {
	663	marvell,pins = "twsi";
	664	marvell,function = "twsi-opt1";
	665	};
	666
	667	pmx_i2cmux_1: pmx-i2cmux-1 {
	668	marvell,pins = "twsi";
	669	marvell,function = "twsi-opt2";
	670	};
	671
	672	pmx_i2cmux_2: pmx-i2cmux-2 {
	673	marvell,pins = "twsi";
	674	marvell,function = "twsi-opt3";
	675	};
0ad44659 SH	676	};
0ad44659 SH	677
b31b3211 JC	678	core_clk: core-clocks@d0214 {
	679	compatible = "marvell,dove-core-clock";
	680	reg = <0xd0214 0x4>;
	681	#clock-cells = <1>;
0ad44659 SH	682	};
0ad44659 SH	683
b31b3211 JC	684	gpio0: gpio-ctrl@d0400 {
	685	compatible = "marvell,orion-gpio";
	686	#gpio-cells = <2>;
	687	gpio-controller;
	688	reg = <0xd0400 0x20>;
	689	ngpios = <32>;
	690	interrupt-controller;
	691	#interrupt-cells = <2>;
	692	interrupts = <12>, <13>, <14>, <60>;
0ad44659 SH	693	};
0ad44659 SH	694
b31b3211 JC	695	gpio1: gpio-ctrl@d0420 {
	696	compatible = "marvell,orion-gpio";
	697	#gpio-cells = <2>;
	698	gpio-controller;
	699	reg = <0xd0420 0x20>;
	700	ngpios = <32>;
	701	interrupt-controller;
	702	#interrupt-cells = <2>;
	703	interrupts = <61>;
0ad44659 SH	704	};
	705
	706	rtc: real-time-clock@d8500 {
	707	compatible = "marvell,orion-rtc";
	708	reg = <0xd8500 0x20>;
	709	};
	710
7a98c18f SH	711	gconf: global-config@e802c {
	712	compatible = "marvell,dove-global-config",
	713	"syscon";
	714	reg = <0xe802c 0x14>;
	715	};
	716
b31b3211 JC	717	gpio2: gpio-ctrl@e8400 {
	718	compatible = "marvell,orion-gpio";
	719	#gpio-cells = <2>;
	720	gpio-controller;
	721	reg = <0xe8400 0x0c>;
	722	ngpios = <8>;
080972aa	723	};
087b0470 RK	724
	725	lcd1: lcd-controller@810000 {
	726	compatible = "marvell,dove-lcd";
	727	reg = <0x810000 0x1000>;
	728	interrupts = <46>;
	729	status = "disabled";
	730	};
	731
	732	lcd0: lcd-controller@820000 {
	733	compatible = "marvell,dove-lcd";
	734	reg = <0x820000 0x1000>;
	735	interrupts = <47>;
	736	status = "disabled";
	737	};
4c3f6b86	738	};
80a8b54b SH	739	};
80a8b54b SH	740	};