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ARM: dts: DRA7: Enable Timers 13 through 16
[deliverable/linux.git] / arch / arm / boot / dts / dra7.dtsi
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
a46631c4 15#define MAX_SOURCES 400
a46631c4 16
6e58b8f1 17/ {
dae320ec
LV		 18 #address-cells = <2>;
19 #size-cells = <2>;
6e58b8f1
S		 20
21 compatible = "ti,dra7xx";
783d3186 22 interrupt-parent = <&crossbar_mpu>;
6e58b8f1
S		 23
24 aliases {
20b80942
NM		 25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
6e58b8f1
S		 30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
065bd7fe
NM		 36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
ef9c5b69
M		 40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
9ec49b9f
RQ		 42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
480b2b32 44 spi0 = &qspi;
6e58b8f1
S		 45 };
46
6e58b8f1
S		 47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
783d3186 53 interrupt-parent = <&gic>;
6e58b8f1
S		 54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
dae320ec
LV		 60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x1000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
6e58b8f1 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
783d3186 65 interrupt-parent = <&gic>;
6e58b8f1
S		 66 };
67
7136d457
MZ		 68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
dae320ec 72 reg = <0x0 0x48281000 0x0 0x1000>;
7136d457 73 interrupt-parent = <&gic>;
6e58b8f1
S		 74 };
75
76 /*
5c5be9db 77 * The soc node represents the soc top level view. It is used for IPs
6e58b8f1
S		 78 * that are not memory mapped in the MPU view or for the MPU itself.
79 */
80 soc {
81 compatible = "ti,omap-infra";
82 mpu {
83 compatible = "ti,omap5-mpu";
84 ti,hwmods = "mpu";
85 };
86 };
87
88 /*
89 * XXX: Use a flat representation of the SOC interconnect.
90 * The real OMAP interconnect network is quite complex.
b7ab524b 91 * Since it will not bring real advantage to represent that in DT for
6e58b8f1
S		 92 * the moment, just use a fake OCP bus entry to represent the whole bus
93 * hierarchy.
94 */
95 ocp {
fba387a6 96 compatible = "ti,dra7-l3-noc", "simple-bus";
6e58b8f1
S		 97 #address-cells = <1>;
98 #size-cells = <1>;
dae320ec 99 ranges = <0x0 0x0 0x0 0xc0000000>;
6e58b8f1 100 ti,hwmods = "l3_main_1", "l3_main_2";
dae320ec
LV		 101 reg = <0x0 0x44000000 0x0 0x1000000>,
102 <0x0 0x45000000 0x0 0x1000>;
783d3186 103 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
7136d457 104 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 105
d919501f
TK		 106 l4_cfg: l4@4a000000 {
107 compatible = "ti,dra7-l4-cfg", "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x4a000000 0x22c000>;
ee6c7507 111
d919501f
TK		 112 scm: scm@2000 {
113 compatible = "ti,dra7-scm-core", "simple-bus";
114 reg = <0x2000 0x2000>;
ee6c7507 115 #address-cells = <1>;
d919501f
TK		 116 #size-cells = <1>;
117 ranges = <0 0x2000 0x2000>;
118
119 scm_conf: scm_conf@0 {
cd455673 120 compatible = "syscon", "simple-bus";
d919501f
TK		 121 reg = <0x0 0x1400>;
122 #address-cells = <1>;
123 #size-cells = <1>;
9a5e3f27 124 ranges = <0 0x0 0x1400>;
d919501f 125
308cfdaf 126 pbias_regulator: pbias_regulator@e00 {
737f146f 127 compatible = "ti,pbias-dra7", "ti,pbias-omap";
d919501f
TK		 128 reg = <0xe00 0x4>;
129 syscon = <&scm_conf>;
130 pbias_mmc_reg: pbias_mmc_omap5 {
131 regulator-name = "pbias_mmc_omap5";
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <3000000>;
134 };
135 };
2d5a3c80
TV		 136
137 scm_conf_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
d919501f
TK		 141 };
142
143 dra7_pmx_core: pinmux@1400 {
144 compatible = "ti,dra7-padconf",
145 "pinctrl-single";
1c5cb6fd 146 reg = <0x1400 0x0468>;
d919501f
TK		 147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0x3fffffff>;
153 };
33cb3a13
RQ		 154
155 scm_conf1: scm_conf@1c04 {
156 compatible = "syscon";
157 reg = <0x1c04 0x0020>;
158 };
43acf169
KVA		 159
160 scm_conf_pcie: scm_conf@1c24 {
161 compatible = "syscon";
162 reg = <0x1c24 0x0024>;
163 };
3d2a58bc
PU		 164
165 sdma_xbar: dma-router@b78 {
166 compatible = "ti,dra7-dma-crossbar";
167 reg = <0xb78 0xfc>;
168 #dma-cells = <1>;
169 dma-requests = <205>;
170 ti,dma-safe-map = <0>;
171 dma-masters = <&sdma>;
172 };
248948fb
PU		 173
174 edma_xbar: dma-router@c78 {
175 compatible = "ti,dra7-dma-crossbar";
176 reg = <0xc78 0x7c>;
177 #dma-cells = <2>;
178 dma-requests = <204>;
179 ti,dma-safe-map = <0>;
180 dma-masters = <&edma>;
181 };
d919501f
TK		 182 };
183
184 cm_core_aon: cm_core_aon@5000 {
185 compatible = "ti,dra7-cm-core-aon";
186 reg = <0x5000 0x2000>;
187
188 cm_core_aon_clocks: clocks {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 };
192
193 cm_core_aon_clockdomains: clockdomains {
194 };
ee6c7507
TK		 195 };
196
d919501f
TK		 197 cm_core: cm_core@8000 {
198 compatible = "ti,dra7-cm-core";
199 reg = <0x8000 0x3000>;
200
201 cm_core_clocks: clocks {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
206 cm_core_clockdomains: clockdomains {
207 };
ee6c7507 208 };
d919501f 209 };
ee6c7507 210
d919501f
TK		 211 l4_wkup: l4@4ae00000 {
212 compatible = "ti,dra7-l4-wkup", "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 0x4ae00000 0x3f000>;
216
217 counter32k: counter@4000 {
218 compatible = "ti,omap-counter32k";
219 reg = <0x4000 0x40>;
220 ti,hwmods = "counter_32k";
221 };
222
223 prm: prm@6000 {
224 compatible = "ti,dra7-prm";
225 reg = <0x6000 0x3000>;
226 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
227
228 prm_clocks: clocks {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 };
232
233 prm_clockdomains: clockdomains {
234 };
ee6c7507
TK		 235 };
236 };
237
18dcd79d
KVA		 238 axi@0 {
239 compatible = "simple-bus";
240 #size-cells = <1>;
241 #address-cells = <1>;
242 ranges = <0x51000000 0x51000000 0x3000
243 0x0 0x20000000 0x10000000>;
73c8f0cb 244 pcie1: pcie@51000000 {
18dcd79d
KVA		 245 compatible = "ti,dra7-pcie";
246 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
247 reg-names = "rc_dbics", "ti_conf", "config";
248 interrupts = <0 232 0x4>, <0 233 0x4>;
249 #address-cells = <3>;
250 #size-cells = <2>;
251 device_type = "pci";
252 ranges = <0x81000000 0 0 0x03000 0 0x00010000
253 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
254 #interrupt-cells = <1>;
255 num-lanes = <1>;
256 ti,hwmods = "pcie1";
257 phys = <&pcie1_phy>;
258 phy-names = "pcie-phy0";
259 interrupt-map-mask = <0 0 0 7>;
260 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
261 <0 0 0 2 &pcie1_intc 2>,
262 <0 0 0 3 &pcie1_intc 3>,
263 <0 0 0 4 &pcie1_intc 4>;
264 pcie1_intc: interrupt-controller {
265 interrupt-controller;
266 #address-cells = <0>;
267 #interrupt-cells = <1>;
268 };
269 };
270 };
271
272 axi@1 {
273 compatible = "simple-bus";
274 #size-cells = <1>;
275 #address-cells = <1>;
276 ranges = <0x51800000 0x51800000 0x3000
277 0x0 0x30000000 0x10000000>;
278 status = "disabled";
279 pcie@51000000 {
280 compatible = "ti,dra7-pcie";
281 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
282 reg-names = "rc_dbics", "ti_conf", "config";
283 interrupts = <0 355 0x4>, <0 356 0x4>;
284 #address-cells = <3>;
285 #size-cells = <2>;
286 device_type = "pci";
287 ranges = <0x81000000 0 0 0x03000 0 0x00010000
288 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
289 #interrupt-cells = <1>;
290 num-lanes = <1>;
291 ti,hwmods = "pcie2";
292 phys = <&pcie2_phy>;
293 phy-names = "pcie-phy0";
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
296 <0 0 0 2 &pcie2_intc 2>,
297 <0 0 0 3 &pcie2_intc 3>,
298 <0 0 0 4 &pcie2_intc 4>;
299 pcie2_intc: interrupt-controller {
300 interrupt-controller;
301 #address-cells = <0>;
302 #interrupt-cells = <1>;
303 };
304 };
305 };
306
f7397edf
K		 307 bandgap: bandgap@4a0021e0 {
308 reg = <0x4a0021e0 0xc
309 0x4a00232c 0xc
310 0x4a002380 0x2c
311 0x4a0023C0 0x3c
312 0x4a002564 0x8
313 0x4a002574 0x50>;
314 compatible = "ti,dra752-bandgap";
315 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
316 #thermal-sensor-cells = <1>;
317 };
318
99639ace
SA		 319 dsp1_system: dsp_system@40d00000 {
320 compatible = "syscon";
321 reg = <0x40d00000 0x100>;
322 };
323
6e58b8f1
S		 324 sdma: dma-controller@4a056000 {
325 compatible = "ti,omap4430-sdma";
326 reg = <0x4a056000 0x1000>;
a46631c4
S		 327 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 331 #dma-cells = <1>;
08d9b327
PU		 332 dma-channels = <32>;
333 dma-requests = <127>;
6e58b8f1
S		 334 };
335
248948fb
PU		 336 edma: edma@43300000 {
337 compatible = "ti,edma3-tpcc";
338 ti,hwmods = "tpcc";
339 reg = <0x43300000 0x100000>;
340 reg-names = "edma3_cc";
341 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "edma3_ccint", "emda3_mperr",
345 "edma3_ccerrint";
346 dma-requests = <64>;
347 #dma-cells = <2>;
348
349 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
350
351 /*
352 * memcpy is disabled, can be enabled with:
353 * ti,edma-memcpy-channels = <20 21>;
354 * for example. Note that these channels need to be
355 * masked in the xbar as well.
356 */
357 };
358
359 edma_tptc0: tptc@43400000 {
360 compatible = "ti,edma3-tptc";
361 ti,hwmods = "tptc0";
362 reg = <0x43400000 0x100000>;
363 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-names = "edma3_tcerrint";
365 };
366
367 edma_tptc1: tptc@43500000 {
368 compatible = "ti,edma3-tptc";
369 ti,hwmods = "tptc1";
370 reg = <0x43500000 0x100000>;
371 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "edma3_tcerrint";
373 };
374
6e58b8f1
S		 375 gpio1: gpio@4ae10000 {
376 compatible = "ti,omap4-gpio";
377 reg = <0x4ae10000 0x200>;
a46631c4 378 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 379 ti,hwmods = "gpio1";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
e49d519c 383 #interrupt-cells = <2>;
6e58b8f1
S		 384 };
385
386 gpio2: gpio@48055000 {
387 compatible = "ti,omap4-gpio";
388 reg = <0x48055000 0x200>;
a46631c4 389 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 390 ti,hwmods = "gpio2";
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
e49d519c 394 #interrupt-cells = <2>;
6e58b8f1
S		 395 };
396
397 gpio3: gpio@48057000 {
398 compatible = "ti,omap4-gpio";
399 reg = <0x48057000 0x200>;
a46631c4 400 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 401 ti,hwmods = "gpio3";
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
e49d519c 405 #interrupt-cells = <2>;
6e58b8f1
S		 406 };
407
408 gpio4: gpio@48059000 {
409 compatible = "ti,omap4-gpio";
410 reg = <0x48059000 0x200>;
a46631c4 411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 412 ti,hwmods = "gpio4";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
e49d519c 416 #interrupt-cells = <2>;
6e58b8f1
S		 417 };
418
419 gpio5: gpio@4805b000 {
420 compatible = "ti,omap4-gpio";
421 reg = <0x4805b000 0x200>;
a46631c4 422 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 423 ti,hwmods = "gpio5";
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-controller;
e49d519c 427 #interrupt-cells = <2>;
6e58b8f1
S		 428 };
429
430 gpio6: gpio@4805d000 {
431 compatible = "ti,omap4-gpio";
432 reg = <0x4805d000 0x200>;
a46631c4 433 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 434 ti,hwmods = "gpio6";
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
e49d519c 438 #interrupt-cells = <2>;
6e58b8f1
S		 439 };
440
441 gpio7: gpio@48051000 {
442 compatible = "ti,omap4-gpio";
443 reg = <0x48051000 0x200>;
a46631c4 444 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 445 ti,hwmods = "gpio7";
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
e49d519c 449 #interrupt-cells = <2>;
6e58b8f1
S		 450 };
451
452 gpio8: gpio@48053000 {
453 compatible = "ti,omap4-gpio";
454 reg = <0x48053000 0x200>;
a46631c4 455 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 456 ti,hwmods = "gpio8";
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
e49d519c 460 #interrupt-cells = <2>;
6e58b8f1
S		 461 };
462
463 uart1: serial@4806a000 {
2a0e5ef6 464 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 465 reg = <0x4806a000 0x100>;
783d3186 466 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 467 ti,hwmods = "uart1";
468 clock-frequency = <48000000>;
469 status = "disabled";
3a0830de 470 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
f0199a29 471 dma-names = "tx", "rx";
6e58b8f1
S		 472 };
473
474 uart2: serial@4806c000 {
2a0e5ef6 475 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 476 reg = <0x4806c000 0x100>;
783d3186 477 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 478 ti,hwmods = "uart2";
479 clock-frequency = <48000000>;
480 status = "disabled";
3a0830de 481 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
f0199a29 482 dma-names = "tx", "rx";
6e58b8f1
S		 483 };
484
485 uart3: serial@48020000 {
2a0e5ef6 486 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 487 reg = <0x48020000 0x100>;
783d3186 488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 489 ti,hwmods = "uart3";
490 clock-frequency = <48000000>;
491 status = "disabled";
3a0830de 492 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
f0199a29 493 dma-names = "tx", "rx";
6e58b8f1
S		 494 };
495
496 uart4: serial@4806e000 {
2a0e5ef6 497 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 498 reg = <0x4806e000 0x100>;
783d3186 499 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 500 ti,hwmods = "uart4";
501 clock-frequency = <48000000>;
502 status = "disabled";
3a0830de 503 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
f0199a29 504 dma-names = "tx", "rx";
6e58b8f1
S		 505 };
506
507 uart5: serial@48066000 {
2a0e5ef6 508 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 509 reg = <0x48066000 0x100>;
783d3186 510 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 511 ti,hwmods = "uart5";
512 clock-frequency = <48000000>;
513 status = "disabled";
3a0830de 514 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
f0199a29 515 dma-names = "tx", "rx";
6e58b8f1
S		 516 };
517
518 uart6: serial@48068000 {
2a0e5ef6 519 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 520 reg = <0x48068000 0x100>;
783d3186 521 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 522 ti,hwmods = "uart6";
523 clock-frequency = <48000000>;
524 status = "disabled";
3a0830de 525 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
f0199a29 526 dma-names = "tx", "rx";
6e58b8f1
S		 527 };
528
529 uart7: serial@48420000 {
2a0e5ef6 530 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 531 reg = <0x48420000 0x100>;
783d3186 532 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 533 ti,hwmods = "uart7";
534 clock-frequency = <48000000>;
535 status = "disabled";
536 };
537
538 uart8: serial@48422000 {
2a0e5ef6 539 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 540 reg = <0x48422000 0x100>;
783d3186 541 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 542 ti,hwmods = "uart8";
543 clock-frequency = <48000000>;
544 status = "disabled";
545 };
546
547 uart9: serial@48424000 {
2a0e5ef6 548 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 549 reg = <0x48424000 0x100>;
783d3186 550 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 551 ti,hwmods = "uart9";
552 clock-frequency = <48000000>;
553 status = "disabled";
554 };
555
556 uart10: serial@4ae2b000 {
2a0e5ef6 557 compatible = "ti,dra742-uart", "ti,omap4-uart";
6e58b8f1 558 reg = <0x4ae2b000 0x100>;
783d3186 559 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 560 ti,hwmods = "uart10";
561 clock-frequency = <48000000>;
562 status = "disabled";
563 };
564
38baefb3
SA		 565 mailbox1: mailbox@4a0f4000 {
566 compatible = "ti,omap4-mailbox";
567 reg = <0x4a0f4000 0x200>;
b46a6ae6
SA		 568 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 571 ti,hwmods = "mailbox1";
24df0453 572 #mbox-cells = <1>;
38baefb3
SA		 573 ti,mbox-num-users = <3>;
574 ti,mbox-num-fifos = <8>;
575 status = "disabled";
576 };
577
578 mailbox2: mailbox@4883a000 {
579 compatible = "ti,omap4-mailbox";
580 reg = <0x4883a000 0x200>;
b46a6ae6
SA		 581 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 585 ti,hwmods = "mailbox2";
24df0453 586 #mbox-cells = <1>;
38baefb3
SA		 587 ti,mbox-num-users = <4>;
588 ti,mbox-num-fifos = <12>;
589 status = "disabled";
590 };
591
592 mailbox3: mailbox@4883c000 {
593 compatible = "ti,omap4-mailbox";
594 reg = <0x4883c000 0x200>;
b46a6ae6
SA		 595 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 599 ti,hwmods = "mailbox3";
24df0453 600 #mbox-cells = <1>;
38baefb3
SA		 601 ti,mbox-num-users = <4>;
602 ti,mbox-num-fifos = <12>;
603 status = "disabled";
604 };
605
606 mailbox4: mailbox@4883e000 {
607 compatible = "ti,omap4-mailbox";
608 reg = <0x4883e000 0x200>;
b46a6ae6
SA		 609 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 613 ti,hwmods = "mailbox4";
24df0453 614 #mbox-cells = <1>;
38baefb3
SA		 615 ti,mbox-num-users = <4>;
616 ti,mbox-num-fifos = <12>;
617 status = "disabled";
618 };
619
620 mailbox5: mailbox@48840000 {
621 compatible = "ti,omap4-mailbox";
622 reg = <0x48840000 0x200>;
b46a6ae6
SA		 623 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 627 ti,hwmods = "mailbox5";
24df0453 628 #mbox-cells = <1>;
38baefb3
SA		 629 ti,mbox-num-users = <4>;
630 ti,mbox-num-fifos = <12>;
631 status = "disabled";
632 };
633
634 mailbox6: mailbox@48842000 {
635 compatible = "ti,omap4-mailbox";
636 reg = <0x48842000 0x200>;
b46a6ae6
SA		 637 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 641 ti,hwmods = "mailbox6";
24df0453 642 #mbox-cells = <1>;
38baefb3
SA		 643 ti,mbox-num-users = <4>;
644 ti,mbox-num-fifos = <12>;
645 status = "disabled";
646 };
647
648 mailbox7: mailbox@48844000 {
649 compatible = "ti,omap4-mailbox";
650 reg = <0x48844000 0x200>;
b46a6ae6
SA		 651 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 655 ti,hwmods = "mailbox7";
24df0453 656 #mbox-cells = <1>;
38baefb3
SA		 657 ti,mbox-num-users = <4>;
658 ti,mbox-num-fifos = <12>;
659 status = "disabled";
660 };
661
662 mailbox8: mailbox@48846000 {
663 compatible = "ti,omap4-mailbox";
664 reg = <0x48846000 0x200>;
b46a6ae6
SA		 665 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 669 ti,hwmods = "mailbox8";
24df0453 670 #mbox-cells = <1>;
38baefb3
SA		 671 ti,mbox-num-users = <4>;
672 ti,mbox-num-fifos = <12>;
673 status = "disabled";
674 };
675
676 mailbox9: mailbox@4885e000 {
677 compatible = "ti,omap4-mailbox";
678 reg = <0x4885e000 0x200>;
b46a6ae6
SA		 679 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 683 ti,hwmods = "mailbox9";
24df0453 684 #mbox-cells = <1>;
38baefb3
SA		 685 ti,mbox-num-users = <4>;
686 ti,mbox-num-fifos = <12>;
687 status = "disabled";
688 };
689
690 mailbox10: mailbox@48860000 {
691 compatible = "ti,omap4-mailbox";
692 reg = <0x48860000 0x200>;
b46a6ae6
SA		 693 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 697 ti,hwmods = "mailbox10";
24df0453 698 #mbox-cells = <1>;
38baefb3
SA		 699 ti,mbox-num-users = <4>;
700 ti,mbox-num-fifos = <12>;
701 status = "disabled";
702 };
703
704 mailbox11: mailbox@48862000 {
705 compatible = "ti,omap4-mailbox";
706 reg = <0x48862000 0x200>;
b46a6ae6
SA		 707 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 711 ti,hwmods = "mailbox11";
24df0453 712 #mbox-cells = <1>;
38baefb3
SA		 713 ti,mbox-num-users = <4>;
714 ti,mbox-num-fifos = <12>;
715 status = "disabled";
716 };
717
718 mailbox12: mailbox@48864000 {
719 compatible = "ti,omap4-mailbox";
720 reg = <0x48864000 0x200>;
b46a6ae6
SA		 721 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 725 ti,hwmods = "mailbox12";
24df0453 726 #mbox-cells = <1>;
38baefb3
SA		 727 ti,mbox-num-users = <4>;
728 ti,mbox-num-fifos = <12>;
729 status = "disabled";
730 };
731
732 mailbox13: mailbox@48802000 {
733 compatible = "ti,omap4-mailbox";
734 reg = <0x48802000 0x200>;
b46a6ae6
SA		 735 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
38baefb3 739 ti,hwmods = "mailbox13";
24df0453 740 #mbox-cells = <1>;
38baefb3
SA		 741 ti,mbox-num-users = <4>;
742 ti,mbox-num-fifos = <12>;
743 status = "disabled";
744 };
745
6e58b8f1
S		 746 timer1: timer@4ae18000 {
747 compatible = "ti,omap5430-timer";
748 reg = <0x4ae18000 0x80>;
a46631c4 749 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 750 ti,hwmods = "timer1";
751 ti,timer-alwon;
752 };
753
754 timer2: timer@48032000 {
755 compatible = "ti,omap5430-timer";
756 reg = <0x48032000 0x80>;
a46631c4 757 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 758 ti,hwmods = "timer2";
759 };
760
761 timer3: timer@48034000 {
762 compatible = "ti,omap5430-timer";
763 reg = <0x48034000 0x80>;
a46631c4 764 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 765 ti,hwmods = "timer3";
766 };
767
768 timer4: timer@48036000 {
769 compatible = "ti,omap5430-timer";
770 reg = <0x48036000 0x80>;
a46631c4 771 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 772 ti,hwmods = "timer4";
773 };
774
775 timer5: timer@48820000 {
776 compatible = "ti,omap5430-timer";
777 reg = <0x48820000 0x80>;
a46631c4 778 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 779 ti,hwmods = "timer5";
6e58b8f1
S		 780 };
781
782 timer6: timer@48822000 {
783 compatible = "ti,omap5430-timer";
784 reg = <0x48822000 0x80>;
a46631c4 785 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 786 ti,hwmods = "timer6";
6e58b8f1
S		 787 };
788
789 timer7: timer@48824000 {
790 compatible = "ti,omap5430-timer";
791 reg = <0x48824000 0x80>;
a46631c4 792 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 793 ti,hwmods = "timer7";
6e58b8f1
S		 794 };
795
796 timer8: timer@48826000 {
797 compatible = "ti,omap5430-timer";
798 reg = <0x48826000 0x80>;
a46631c4 799 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 800 ti,hwmods = "timer8";
6e58b8f1
S		 801 };
802
803 timer9: timer@4803e000 {
804 compatible = "ti,omap5430-timer";
805 reg = <0x4803e000 0x80>;
a46631c4 806 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 807 ti,hwmods = "timer9";
808 };
809
810 timer10: timer@48086000 {
811 compatible = "ti,omap5430-timer";
812 reg = <0x48086000 0x80>;
a46631c4 813 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 814 ti,hwmods = "timer10";
815 };
816
817 timer11: timer@48088000 {
818 compatible = "ti,omap5430-timer";
819 reg = <0x48088000 0x80>;
a46631c4 820 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 821 ti,hwmods = "timer11";
6e58b8f1
S		 822 };
823
824 timer13: timer@48828000 {
825 compatible = "ti,omap5430-timer";
826 reg = <0x48828000 0x80>;
a46631c4 827 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 828 ti,hwmods = "timer13";
6e58b8f1
S		 829 };
830
831 timer14: timer@4882a000 {
832 compatible = "ti,omap5430-timer";
833 reg = <0x4882a000 0x80>;
a46631c4 834 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 835 ti,hwmods = "timer14";
6e58b8f1
S		 836 };
837
838 timer15: timer@4882c000 {
839 compatible = "ti,omap5430-timer";
840 reg = <0x4882c000 0x80>;
a46631c4 841 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 842 ti,hwmods = "timer15";
6e58b8f1
S		 843 };
844
845 timer16: timer@4882e000 {
846 compatible = "ti,omap5430-timer";
847 reg = <0x4882e000 0x80>;
a46631c4 848 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 849 ti,hwmods = "timer16";
6e58b8f1
S		 850 };
851
852 wdt2: wdt@4ae14000 {
be668835 853 compatible = "ti,omap3-wdt";
6e58b8f1 854 reg = <0x4ae14000 0x80>;
a46631c4 855 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 856 ti,hwmods = "wd_timer2";
857 };
858
dbd7c191
SA		 859 hwspinlock: spinlock@4a0f6000 {
860 compatible = "ti,omap4-hwspinlock";
861 reg = <0x4a0f6000 0x1000>;
862 ti,hwmods = "spinlock";
863 #hwlock-cells = <1>;
864 };
865
1a5fe3ca
AT		 866 dmm@4e000000 {
867 compatible = "ti,omap5-dmm";
868 reg = <0x4e000000 0x800>;
a46631c4 869 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1a5fe3ca
AT		 870 ti,hwmods = "dmm";
871 };
872
6e58b8f1
S		 873 i2c1: i2c@48070000 {
874 compatible = "ti,omap4-i2c";
875 reg = <0x48070000 0x100>;
a46631c4 876 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 877 #address-cells = <1>;
878 #size-cells = <0>;
879 ti,hwmods = "i2c1";
880 status = "disabled";
881 };
882
883 i2c2: i2c@48072000 {
884 compatible = "ti,omap4-i2c";
885 reg = <0x48072000 0x100>;
a46631c4 886 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 887 #address-cells = <1>;
888 #size-cells = <0>;
889 ti,hwmods = "i2c2";
890 status = "disabled";
891 };
892
893 i2c3: i2c@48060000 {
894 compatible = "ti,omap4-i2c";
895 reg = <0x48060000 0x100>;
a46631c4 896 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 897 #address-cells = <1>;
898 #size-cells = <0>;
899 ti,hwmods = "i2c3";
900 status = "disabled";
901 };
902
903 i2c4: i2c@4807a000 {
904 compatible = "ti,omap4-i2c";
905 reg = <0x4807a000 0x100>;
a46631c4 906 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 907 #address-cells = <1>;
908 #size-cells = <0>;
909 ti,hwmods = "i2c4";
910 status = "disabled";
911 };
912
913 i2c5: i2c@4807c000 {
914 compatible = "ti,omap4-i2c";
915 reg = <0x4807c000 0x100>;
a46631c4 916 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 917 #address-cells = <1>;
918 #size-cells = <0>;
919 ti,hwmods = "i2c5";
920 status = "disabled";
921 };
922
923 mmc1: mmc@4809c000 {
924 compatible = "ti,omap4-hsmmc";
925 reg = <0x4809c000 0x400>;
a46631c4 926 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 927 ti,hwmods = "mmc1";
928 ti,dual-volt;
929 ti,needs-special-reset;
3a0830de 930 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
6e58b8f1
S		 931 dma-names = "tx", "rx";
932 status = "disabled";
cd042fe5 933 pbias-supply = <&pbias_mmc_reg>;
6e58b8f1
S		 934 };
935
936 mmc2: mmc@480b4000 {
937 compatible = "ti,omap4-hsmmc";
938 reg = <0x480b4000 0x400>;
a46631c4 939 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 940 ti,hwmods = "mmc2";
941 ti,needs-special-reset;
3a0830de 942 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
6e58b8f1
S		 943 dma-names = "tx", "rx";
944 status = "disabled";
945 };
946
947 mmc3: mmc@480ad000 {
948 compatible = "ti,omap4-hsmmc";
949 reg = <0x480ad000 0x400>;
a46631c4 950 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 951 ti,hwmods = "mmc3";
952 ti,needs-special-reset;
3a0830de 953 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
6e58b8f1
S		 954 dma-names = "tx", "rx";
955 status = "disabled";
956 };
957
958 mmc4: mmc@480d1000 {
959 compatible = "ti,omap4-hsmmc";
960 reg = <0x480d1000 0x400>;
a46631c4 961 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 962 ti,hwmods = "mmc4";
963 ti,needs-special-reset;
3a0830de 964 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
6e58b8f1
S		 965 dma-names = "tx", "rx";
966 status = "disabled";
967 };
968
2c7e07c5
SA		 969 mmu0_dsp1: mmu@40d01000 {
970 compatible = "ti,dra7-dsp-iommu";
971 reg = <0x40d01000 0x100>;
972 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
973 ti,hwmods = "mmu0_dsp1";
974 #iommu-cells = <0>;
975 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
976 status = "disabled";
977 };
978
979 mmu1_dsp1: mmu@40d02000 {
980 compatible = "ti,dra7-dsp-iommu";
981 reg = <0x40d02000 0x100>;
982 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
983 ti,hwmods = "mmu1_dsp1";
984 #iommu-cells = <0>;
985 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
986 status = "disabled";
987 };
988
989 mmu_ipu1: mmu@58882000 {
990 compatible = "ti,dra7-iommu";
991 reg = <0x58882000 0x100>;
992 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
993 ti,hwmods = "mmu_ipu1";
994 #iommu-cells = <0>;
995 ti,iommu-bus-err-back;
996 status = "disabled";
997 };
998
999 mmu_ipu2: mmu@55082000 {
1000 compatible = "ti,dra7-iommu";
1001 reg = <0x55082000 0x100>;
1002 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1003 ti,hwmods = "mmu_ipu2";
1004 #iommu-cells = <0>;
1005 ti,iommu-bus-err-back;
1006 status = "disabled";
1007 };
1008
a1b8ee10
NM		 1009 abb_mpu: regulator-abb-mpu {
1010 compatible = "ti,abb-v3";
1011 regulator-name = "abb_mpu";
1012 #address-cells = <0>;
1013 #size-cells = <0>;
1014 clocks = <&sys_clkin1>;
1015 ti,settling-time = <50>;
1016 ti,clock-cycles = <16>;
1017
1018 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
18227346 1019 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
a1b8ee10
NM		 1020 <0x4ae0c158 0x4>;
1021 reg-names = "setup-address", "control-address",
1022 "int-address", "efuse-address",
1023 "ldo-address";
1024 ti,tranxdone-status-mask = <0x80>;
1025 /* LDOVBBMPU_FBB_MUX_CTRL */
1026 ti,ldovbb-override-mask = <0x400>;
1027 /* LDOVBBMPU_FBB_VSET_OUT */
1028 ti,ldovbb-vset-mask = <0x1F>;
1029
1030 /*
1031 * NOTE: only FBB mode used but actual vset will
1032 * determine final biasing
1033 */
1034 ti,abb_info = <
1035 /*uV ABB efuse rbb_m fbb_m vset_m*/
1036 1060000 0 0x0 0 0x02000000 0x01F00000
1037 1160000 0 0x4 0 0x02000000 0x01F00000
1038 1210000 0 0x8 0 0x02000000 0x01F00000
1039 >;
1040 };
1041
1042 abb_ivahd: regulator-abb-ivahd {
1043 compatible = "ti,abb-v3";
1044 regulator-name = "abb_ivahd";
1045 #address-cells = <0>;
1046 #size-cells = <0>;
1047 clocks = <&sys_clkin1>;
1048 ti,settling-time = <50>;
1049 ti,clock-cycles = <16>;
1050
1051 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
18227346 1052 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
a1b8ee10
NM		 1053 <0x4a002470 0x4>;
1054 reg-names = "setup-address", "control-address",
1055 "int-address", "efuse-address",
1056 "ldo-address";
1057 ti,tranxdone-status-mask = <0x40000000>;
1058 /* LDOVBBIVA_FBB_MUX_CTRL */
1059 ti,ldovbb-override-mask = <0x400>;
1060 /* LDOVBBIVA_FBB_VSET_OUT */
1061 ti,ldovbb-vset-mask = <0x1F>;
1062
1063 /*
1064 * NOTE: only FBB mode used but actual vset will
1065 * determine final biasing
1066 */
1067 ti,abb_info = <
1068 /*uV ABB efuse rbb_m fbb_m vset_m*/
1069 1055000 0 0x0 0 0x02000000 0x01F00000
1070 1150000 0 0x4 0 0x02000000 0x01F00000
1071 1250000 0 0x8 0 0x02000000 0x01F00000
1072 >;
1073 };
1074
1075 abb_dspeve: regulator-abb-dspeve {
1076 compatible = "ti,abb-v3";
1077 regulator-name = "abb_dspeve";
1078 #address-cells = <0>;
1079 #size-cells = <0>;
1080 clocks = <&sys_clkin1>;
1081 ti,settling-time = <50>;
1082 ti,clock-cycles = <16>;
1083
1084 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
18227346 1085 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
a1b8ee10
NM		 1086 <0x4a00246c 0x4>;
1087 reg-names = "setup-address", "control-address",
1088 "int-address", "efuse-address",
1089 "ldo-address";
1090 ti,tranxdone-status-mask = <0x20000000>;
1091 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1092 ti,ldovbb-override-mask = <0x400>;
1093 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1094 ti,ldovbb-vset-mask = <0x1F>;
1095
1096 /*
1097 * NOTE: only FBB mode used but actual vset will
1098 * determine final biasing
1099 */
1100 ti,abb_info = <
1101 /*uV ABB efuse rbb_m fbb_m vset_m*/
1102 1055000 0 0x0 0 0x02000000 0x01F00000
1103 1150000 0 0x4 0 0x02000000 0x01F00000
1104 1250000 0 0x8 0 0x02000000 0x01F00000
1105 >;
1106 };
1107
1108 abb_gpu: regulator-abb-gpu {
1109 compatible = "ti,abb-v3";
1110 regulator-name = "abb_gpu";
1111 #address-cells = <0>;
1112 #size-cells = <0>;
1113 clocks = <&sys_clkin1>;
1114 ti,settling-time = <50>;
1115 ti,clock-cycles = <16>;
1116
1117 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
18227346 1118 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
a1b8ee10
NM		 1119 <0x4ae0c154 0x4>;
1120 reg-names = "setup-address", "control-address",
1121 "int-address", "efuse-address",
1122 "ldo-address";
1123 ti,tranxdone-status-mask = <0x10000000>;
1124 /* LDOVBBGPU_FBB_MUX_CTRL */
1125 ti,ldovbb-override-mask = <0x400>;
1126 /* LDOVBBGPU_FBB_VSET_OUT */
1127 ti,ldovbb-vset-mask = <0x1F>;
1128
1129 /*
1130 * NOTE: only FBB mode used but actual vset will
1131 * determine final biasing
1132 */
1133 ti,abb_info = <
1134 /*uV ABB efuse rbb_m fbb_m vset_m*/
1135 1090000 0 0x0 0 0x02000000 0x01F00000
1136 1210000 0 0x4 0 0x02000000 0x01F00000
1137 1280000 0 0x8 0 0x02000000 0x01F00000
1138 >;
1139 };
1140
6e58b8f1
S		 1141 mcspi1: spi@48098000 {
1142 compatible = "ti,omap4-mcspi";
1143 reg = <0x48098000 0x200>;
a46631c4 1144 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 ti,hwmods = "mcspi1";
1148 ti,spi-num-cs = <4>;
3a0830de
PU		 1149 dmas = <&sdma_xbar 35>,
1150 <&sdma_xbar 36>,
1151 <&sdma_xbar 37>,
1152 <&sdma_xbar 38>,
1153 <&sdma_xbar 39>,
1154 <&sdma_xbar 40>,
1155 <&sdma_xbar 41>,
1156 <&sdma_xbar 42>;
6e58b8f1
S		 1157 dma-names = "tx0", "rx0", "tx1", "rx1",
1158 "tx2", "rx2", "tx3", "rx3";
1159 status = "disabled";
1160 };
1161
1162 mcspi2: spi@4809a000 {
1163 compatible = "ti,omap4-mcspi";
1164 reg = <0x4809a000 0x200>;
a46631c4 1165 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 ti,hwmods = "mcspi2";
1169 ti,spi-num-cs = <2>;
3a0830de
PU		 1170 dmas = <&sdma_xbar 43>,
1171 <&sdma_xbar 44>,
1172 <&sdma_xbar 45>,
1173 <&sdma_xbar 46>;
6e58b8f1
S		 1174 dma-names = "tx0", "rx0", "tx1", "rx1";
1175 status = "disabled";
1176 };
1177
1178 mcspi3: spi@480b8000 {
1179 compatible = "ti,omap4-mcspi";
1180 reg = <0x480b8000 0x200>;
a46631c4 1181 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1182 #address-cells = <1>;
1183 #size-cells = <0>;
1184 ti,hwmods = "mcspi3";
1185 ti,spi-num-cs = <2>;
3a0830de 1186 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
6e58b8f1
S		 1187 dma-names = "tx0", "rx0";
1188 status = "disabled";
1189 };
1190
1191 mcspi4: spi@480ba000 {
1192 compatible = "ti,omap4-mcspi";
1193 reg = <0x480ba000 0x200>;
a46631c4 1194 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 ti,hwmods = "mcspi4";
1198 ti,spi-num-cs = <1>;
3a0830de 1199 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
6e58b8f1
S		 1200 dma-names = "tx0", "rx0";
1201 status = "disabled";
1202 };
dc2dd5b8
SP		 1203
1204 qspi: qspi@4b300000 {
1205 compatible = "ti,dra7xxx-qspi";
1929d0b5
V		 1206 reg = <0x4b300000 0x100>,
1207 <0x5c000000 0x4000000>;
1208 reg-names = "qspi_base", "qspi_mmap";
1209 syscon-chipselects = <&scm_conf 0x558>;
dc2dd5b8
SP		 1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 ti,hwmods = "qspi";
1213 clocks = <&qspi_gfclk_div>;
1214 clock-names = "fck";
1215 num-cs = <4>;
a46631c4 1216 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
dc2dd5b8
SP		 1217 status = "disabled";
1218 };
7be80569 1219
7be80569
B		 1220 /* OCP2SCP3 */
1221 ocp2scp@4a090000 {
1222 compatible = "ti,omap-ocp2scp";
1223 #address-cells = <1>;
1224 #size-cells = <1>;
1225 ranges;
1226 reg = <0x4a090000 0x20>;
1227 ti,hwmods = "ocp2scp3";
1228 sata_phy: phy@4A096000 {
1229 compatible = "ti,phy-pipe3-sata";
1230 reg = <0x4A096000 0x80>, /* phy_rx */
1231 <0x4A096400 0x64>, /* phy_tx */
1232 <0x4A096800 0x40>; /* pll_ctrl */
1233 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 1234 syscon-phy-power = <&scm_conf 0x374>;
773c5a0f
RQ		 1235 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1236 clock-names = "sysclk", "refclk";
257d5d9a 1237 syscon-pllreset = <&scm_conf 0x3fc>;
7be80569
B		 1238 #phy-cells = <0>;
1239 };
692df0ef
KVA		 1240
1241 pcie1_phy: pciephy@4a094000 {
1242 compatible = "ti,phy-pipe3-pcie";
1243 reg = <0x4a094000 0x80>, /* phy_rx */
1244 <0x4a094400 0x64>; /* phy_tx */
1245 reg-names = "phy_rx", "phy_tx";
6921e58b
KVA		 1246 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1247 syscon-pcs = <&scm_conf_pcie 0x10>;
692df0ef
KVA		 1248 clocks = <&dpll_pcie_ref_ck>,
1249 <&dpll_pcie_ref_m2ldo_ck>,
1250 <&optfclk_pciephy1_32khz>,
1251 <&optfclk_pciephy1_clk>,
1252 <&optfclk_pciephy1_div_clk>,
6921e58b
KVA		 1253 <&optfclk_pciephy_div>,
1254 <&sys_clkin1>;
692df0ef
KVA		 1255 clock-names = "dpll_ref", "dpll_ref_m2",
1256 "wkupclk", "refclk",
6921e58b 1257 "div-clk", "phy-div", "sysclk";
692df0ef 1258 #phy-cells = <0>;
692df0ef
KVA		 1259 };
1260
1261 pcie2_phy: pciephy@4a095000 {
1262 compatible = "ti,phy-pipe3-pcie";
1263 reg = <0x4a095000 0x80>, /* phy_rx */
1264 <0x4a095400 0x64>; /* phy_tx */
1265 reg-names = "phy_rx", "phy_tx";
6921e58b
KVA		 1266 syscon-phy-power = <&scm_conf_pcie 0x20>;
1267 syscon-pcs = <&scm_conf_pcie 0x10>;
692df0ef
KVA		 1268 clocks = <&dpll_pcie_ref_ck>,
1269 <&dpll_pcie_ref_m2ldo_ck>,
1270 <&optfclk_pciephy2_32khz>,
1271 <&optfclk_pciephy2_clk>,
1272 <&optfclk_pciephy2_div_clk>,
6921e58b
KVA		 1273 <&optfclk_pciephy_div>,
1274 <&sys_clkin1>;
692df0ef
KVA		 1275 clock-names = "dpll_ref", "dpll_ref_m2",
1276 "wkupclk", "refclk",
6921e58b 1277 "div-clk", "phy-div", "sysclk";
692df0ef 1278 #phy-cells = <0>;
692df0ef
KVA		 1279 status = "disabled";
1280 };
7be80569
B		 1281 };
1282
1283 sata: sata@4a141100 {
1284 compatible = "snps,dwc-ahci";
1285 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
a46631c4 1286 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
7be80569
B		 1287 phys = <&sata_phy>;
1288 phy-names = "sata-phy";
1289 clocks = <&sata_ref_clk>;
1290 ti,hwmods = "sata";
1291 };
fbf3e552 1292
00edd317 1293 rtc: rtc@48838000 {
bc078316
LV		 1294 compatible = "ti,am3352-rtc";
1295 reg = <0x48838000 0x100>;
1296 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1298 ti,hwmods = "rtcss";
1299 clocks = <&sys_32k_ck>;
1300 };
1301
fbf3e552
RQ		 1302 /* OCP2SCP1 */
1303 ocp2scp@4a080000 {
1304 compatible = "ti,omap-ocp2scp";
1305 #address-cells = <1>;
1306 #size-cells = <1>;
1307 ranges;
1308 reg = <0x4a080000 0x20>;
1309 ti,hwmods = "ocp2scp1";
1310
1311 usb2_phy1: phy@4a084000 {
1312 compatible = "ti,omap-usb2";
1313 reg = <0x4a084000 0x400>;
2338c76a 1314 syscon-phy-power = <&scm_conf 0x300>;
fbf3e552
RQ		 1315 clocks = <&usb_phy1_always_on_clk32k>,
1316 <&usb_otg_ss1_refclk960m>;
1317 clock-names = "wkupclk",
1318 "refclk";
1319 #phy-cells = <0>;
1320 };
1321
1322 usb2_phy2: phy@4a085000 {
4b4f52ed
KVA		 1323 compatible = "ti,dra7x-usb2-phy2",
1324 "ti,omap-usb2";
fbf3e552 1325 reg = <0x4a085000 0x400>;
2338c76a 1326 syscon-phy-power = <&scm_conf 0xe74>;
fbf3e552
RQ		 1327 clocks = <&usb_phy2_always_on_clk32k>,
1328 <&usb_otg_ss2_refclk960m>;
1329 clock-names = "wkupclk",
1330 "refclk";
1331 #phy-cells = <0>;
1332 };
1333
1334 usb3_phy1: phy@4a084400 {
1335 compatible = "ti,omap-usb3";
1336 reg = <0x4a084400 0x80>,
1337 <0x4a084800 0x64>,
1338 <0x4a084c00 0x40>;
1339 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 1340 syscon-phy-power = <&scm_conf 0x370>;
fbf3e552
RQ		 1341 clocks = <&usb_phy3_always_on_clk32k>,
1342 <&sys_clkin1>,
1343 <&usb_otg_ss1_refclk960m>;
1344 clock-names = "wkupclk",
1345 "sysclk",
1346 "refclk";
1347 #phy-cells = <0>;
1348 };
1349 };
1350
4f6dec70 1351 omap_dwc3_1: omap_dwc3_1@48880000 {
fbf3e552
RQ		 1352 compatible = "ti,dwc3";
1353 ti,hwmods = "usb_otg_ss1";
1354 reg = <0x48880000 0x10000>;
a46631c4 1355 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1356 #address-cells = <1>;
1357 #size-cells = <1>;
1358 utmi-mode = <2>;
1359 ranges;
1360 usb1: usb@48890000 {
1361 compatible = "snps,dwc3";
1362 reg = <0x48890000 0x17000>;
964927f3
RQ		 1363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1366 interrupt-names = "peripheral",
1367 "host",
1368 "otg";
fbf3e552
RQ		 1369 phys = <&usb2_phy1>, <&usb3_phy1>;
1370 phy-names = "usb2-phy", "usb3-phy";
fbf3e552
RQ		 1371 maximum-speed = "super-speed";
1372 dr_mode = "otg";
8c606735
FB		 1373 snps,dis_u3_susphy_quirk;
1374 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1375 };
1376 };
1377
4f6dec70 1378 omap_dwc3_2: omap_dwc3_2@488c0000 {
fbf3e552
RQ		 1379 compatible = "ti,dwc3";
1380 ti,hwmods = "usb_otg_ss2";
1381 reg = <0x488c0000 0x10000>;
a46631c4 1382 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1383 #address-cells = <1>;
1384 #size-cells = <1>;
1385 utmi-mode = <2>;
1386 ranges;
1387 usb2: usb@488d0000 {
1388 compatible = "snps,dwc3";
1389 reg = <0x488d0000 0x17000>;
964927f3
RQ		 1390 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1393 interrupt-names = "peripheral",
1394 "host",
1395 "otg";
fbf3e552
RQ		 1396 phys = <&usb2_phy2>;
1397 phy-names = "usb2-phy";
fbf3e552
RQ		 1398 maximum-speed = "high-speed";
1399 dr_mode = "otg";
8c606735
FB		 1400 snps,dis_u3_susphy_quirk;
1401 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1402 };
1403 };
1404
1405 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
4f6dec70 1406 omap_dwc3_3: omap_dwc3_3@48900000 {
fbf3e552
RQ		 1407 compatible = "ti,dwc3";
1408 ti,hwmods = "usb_otg_ss3";
1409 reg = <0x48900000 0x10000>;
a46631c4 1410 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1411 #address-cells = <1>;
1412 #size-cells = <1>;
1413 utmi-mode = <2>;
1414 ranges;
1415 status = "disabled";
1416 usb3: usb@48910000 {
1417 compatible = "snps,dwc3";
1418 reg = <0x48910000 0x17000>;
964927f3
RQ		 1419 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-names = "peripheral",
1423 "host",
1424 "otg";
fbf3e552
RQ		 1425 maximum-speed = "high-speed";
1426 dr_mode = "otg";
8c606735
FB		 1427 snps,dis_u3_susphy_quirk;
1428 snps,dis_u2_susphy_quirk;
fbf3e552
RQ		 1429 };
1430 };
1431
ff66a3c8
MS		 1432 elm: elm@48078000 {
1433 compatible = "ti,am3352-elm";
1434 reg = <0x48078000 0xfc0>; /* device IO registers */
a46631c4 1435 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1436 ti,hwmods = "elm";
1437 status = "disabled";
1438 };
1439
1440 gpmc: gpmc@50000000 {
1441 compatible = "ti,am3352-gpmc";
1442 ti,hwmods = "gpmc";
1443 reg = <0x50000000 0x37c>; /* device IO registers */
a46631c4 1444 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1445 gpmc,num-cs = <8>;
1446 gpmc,num-waitpins = <2>;
1447 #address-cells = <2>;
1448 #size-cells = <1>;
488f270d
RQ		 1449 interrupt-controller;
1450 #interrupt-cells = <2>;
ff66a3c8
MS		 1451 status = "disabled";
1452 };
2ca0945f
PU		 1453
1454 atl: atl@4843c000 {
1455 compatible = "ti,dra7-atl";
1456 reg = <0x4843c000 0x3ff>;
1457 ti,hwmods = "atl";
1458 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1459 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1460 clocks = <&atl_gfclk_mux>;
1461 clock-names = "fck";
1462 status = "disabled";
1463 };
412a9bbd 1464
296ea972
PU		 1465 mcasp1: mcasp@48460000 {
1466 compatible = "ti,dra7-mcasp-audio";
1467 ti,hwmods = "mcasp1";
1468 reg = <0x48460000 0x2000>,
1469 <0x45800000 0x1000>;
1470 reg-names = "mpu","dat";
1471 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1473 interrupt-names = "tx", "rx";
1474 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1475 dma-names = "tx", "rx";
1476 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1477 <&mcasp1_ahclkr_mux>;
1478 clock-names = "fck", "ahclkx", "ahclkr";
1479 status = "disabled";
1480 };
1481
1482 mcasp2: mcasp@48464000 {
1483 compatible = "ti,dra7-mcasp-audio";
1484 ti,hwmods = "mcasp2";
1485 reg = <0x48464000 0x2000>,
1486 <0x45c00000 0x1000>;
1487 reg-names = "mpu","dat";
1488 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1490 interrupt-names = "tx", "rx";
1491 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1492 dma-names = "tx", "rx";
1493 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1494 <&mcasp2_ahclkr_mux>;
1495 clock-names = "fck", "ahclkx", "ahclkr";
1496 status = "disabled";
1497 };
1498
026d4d6d
PU		 1499 mcasp3: mcasp@48468000 {
1500 compatible = "ti,dra7-mcasp-audio";
1501 ti,hwmods = "mcasp3";
0c92de2c
MLC		 1502 reg = <0x48468000 0x2000>,
1503 <0x46000000 0x1000>;
1504 reg-names = "mpu","dat";
026d4d6d
PU		 1505 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1507 interrupt-names = "tx", "rx";
0c92de2c 1508 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
026d4d6d 1509 dma-names = "tx", "rx";
bf05c2c2 1510 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
296ea972
PU		 1511 clock-names = "fck", "ahclkx";
1512 status = "disabled";
1513 };
1514
1515 mcasp4: mcasp@4846c000 {
1516 compatible = "ti,dra7-mcasp-audio";
1517 ti,hwmods = "mcasp4";
1518 reg = <0x4846c000 0x2000>,
1519 <0x48436000 0x1000>;
1520 reg-names = "mpu","dat";
1521 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1523 interrupt-names = "tx", "rx";
1524 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1525 dma-names = "tx", "rx";
1526 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1527 clock-names = "fck", "ahclkx";
1528 status = "disabled";
1529 };
1530
1531 mcasp5: mcasp@48470000 {
1532 compatible = "ti,dra7-mcasp-audio";
1533 ti,hwmods = "mcasp5";
1534 reg = <0x48470000 0x2000>,
1535 <0x4843a000 0x1000>;
1536 reg-names = "mpu","dat";
1537 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1539 interrupt-names = "tx", "rx";
1540 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1541 dma-names = "tx", "rx";
1542 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1543 clock-names = "fck", "ahclkx";
1544 status = "disabled";
1545 };
1546
1547 mcasp6: mcasp@48474000 {
1548 compatible = "ti,dra7-mcasp-audio";
1549 ti,hwmods = "mcasp6";
1550 reg = <0x48474000 0x2000>,
1551 <0x4844c000 0x1000>;
1552 reg-names = "mpu","dat";
1553 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1555 interrupt-names = "tx", "rx";
1556 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1557 dma-names = "tx", "rx";
1558 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1559 clock-names = "fck", "ahclkx";
1560 status = "disabled";
1561 };
1562
1563 mcasp7: mcasp@48478000 {
1564 compatible = "ti,dra7-mcasp-audio";
1565 ti,hwmods = "mcasp7";
1566 reg = <0x48478000 0x2000>,
1567 <0x48450000 0x1000>;
1568 reg-names = "mpu","dat";
1569 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1571 interrupt-names = "tx", "rx";
1572 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1573 dma-names = "tx", "rx";
1574 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1575 clock-names = "fck", "ahclkx";
1576 status = "disabled";
1577 };
1578
1579 mcasp8: mcasp@4847c000 {
1580 compatible = "ti,dra7-mcasp-audio";
1581 ti,hwmods = "mcasp8";
1582 reg = <0x4847c000 0x2000>,
1583 <0x48454000 0x1000>;
1584 reg-names = "mpu","dat";
1585 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1587 interrupt-names = "tx", "rx";
1588 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1589 dma-names = "tx", "rx";
1590 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
bf05c2c2 1591 clock-names = "fck", "ahclkx";
026d4d6d
PU		 1592 status = "disabled";
1593 };
1594
783d3186 1595 crossbar_mpu: crossbar@4a002a48 {
a46631c4
S		 1596 compatible = "ti,irq-crossbar";
1597 reg = <0x4a002a48 0x130>;
783d3186 1598 interrupt-controller;
7136d457 1599 interrupt-parent = <&wakeupgen>;
783d3186 1600 #interrupt-cells = <3>;
a46631c4
S		 1601 ti,max-irqs = <160>;
1602 ti,max-crossbar-sources = <MAX_SOURCES>;
1603 ti,reg-size = <2>;
1604 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1605 ti,irqs-skip = <10 133 139 140>;
1606 ti,irqs-safe-map = <0>;
1607 };
ef9c5b69 1608
c263a5b8 1609 mac: ethernet@48484000 {
e2095318 1610 compatible = "ti,dra7-cpsw","ti,cpsw";
ef9c5b69
M		 1611 ti,hwmods = "gmac";
1612 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1613 clock-names = "fck", "cpts";
1614 cpdma_channels = <8>;
1615 ale_entries = <1024>;
1616 bd_ram_size = <0x2000>;
1617 no_bd_ram = <0>;
1618 rx_descs = <64>;
1619 mac_control = <0x20>;
1620 slaves = <2>;
1621 active_slave = <0>;
1622 cpts_clock_mult = <0x80000000>;
1623 cpts_clock_shift = <29>;
1624 reg = <0x48484000 0x1000
1625 0x48485200 0x2E00>;
1626 #address-cells = <1>;
1627 #size-cells = <1>;
0f514e69
M		 1628
1629 /*
1630 * Do not allow gating of cpsw clock as workaround
1631 * for errata i877. Keeping internal clock disabled
1632 * causes the device switching characteristics
1633 * to degrade over time and eventually fail to meet
1634 * the data manual delay time/skew specs.
1635 */
1636 ti,no-idle;
1637
ef9c5b69
M		 1638 /*
1639 * rx_thresh_pend
1640 * rx_pend
1641 * tx_pend
1642 * misc_pend
1643 */
1644 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1648 ranges;
a084e13e 1649 syscon = <&scm_conf>;
ef9c5b69
M		 1650 status = "disabled";
1651
1652 davinci_mdio: mdio@48485000 {
1653 compatible = "ti,davinci_mdio";
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1656 ti,hwmods = "davinci_mdio";
1657 bus_freq = <1000000>;
1658 reg = <0x48485000 0x100>;
1659 };
1660
1661 cpsw_emac0: slave@48480200 {
1662 /* Filled in by U-Boot */
1663 mac-address = [ 00 00 00 00 00 00 ];
1664 };
1665
1666 cpsw_emac1: slave@48480300 {
1667 /* Filled in by U-Boot */
1668 mac-address = [ 00 00 00 00 00 00 ];
1669 };
1670
1671 phy_sel: cpsw-phy-sel@4a002554 {
1672 compatible = "ti,dra7xx-cpsw-phy-sel";
1673 reg= <0x4a002554 0x4>;
1674 reg-names = "gmii-sel";
1675 };
1676 };
1677
9ec49b9f
RQ		 1678 dcan1: can@481cc000 {
1679 compatible = "ti,dra7-d_can";
1680 ti,hwmods = "dcan1";
1681 reg = <0x4ae3c000 0x2000>;
d919501f 1682 syscon-raminit = <&scm_conf 0x558 0>;
9ec49b9f
RQ		 1683 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1684 clocks = <&dcan1_sys_clk_mux>;
1685 status = "disabled";
1686 };
1687
1688 dcan2: can@481d0000 {
1689 compatible = "ti,dra7-d_can";
1690 ti,hwmods = "dcan2";
1691 reg = <0x48480000 0x2000>;
d919501f 1692 syscon-raminit = <&scm_conf 0x558 1>;
9ec49b9f
RQ		 1693 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&sys_clkin1>;
1695 status = "disabled";
1696 };
95c1cd13
TV		 1697
1698 dss: dss@58000000 {
1699 compatible = "ti,dra7-dss";
1700 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1701 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1702 status = "disabled";
1703 ti,hwmods = "dss_core";
1704 /* CTRL_CORE_DSS_PLL_CONTROL */
1705 syscon-pll-ctrl = <&scm_conf 0x538>;
1706 #address-cells = <1>;
1707 #size-cells = <1>;
1708 ranges;
1709
1710 dispc@58001000 {
1711 compatible = "ti,dra7-dispc";
1712 reg = <0x58001000 0x1000>;
1713 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1714 ti,hwmods = "dss_dispc";
1715 clocks = <&dss_dss_clk>;
1716 clock-names = "fck";
1717 /* CTRL_CORE_SMA_SW_1 */
1718 syscon-pol = <&scm_conf 0x534>;
1719 };
1720
1721 hdmi: encoder@58060000 {
1722 compatible = "ti,dra7-hdmi";
1723 reg = <0x58040000 0x200>,
1724 <0x58040200 0x80>,
1725 <0x58040300 0x80>,
1726 <0x58060000 0x19000>;
1727 reg-names = "wp", "pll", "phy", "core";
1728 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1729 status = "disabled";
1730 ti,hwmods = "dss_hdmi";
1731 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1732 clock-names = "fck", "sys_clk";
1733 };
1734 };
6e58b8f1 1735 };
f7397edf
K		 1736
1737 thermal_zones: thermal-zones {
1738 #include "omap4-cpu-thermal.dtsi"
1739 #include "omap5-gpu-thermal.dtsi"
1740 #include "omap5-core-thermal.dtsi"
667f2599
K		 1741 #include "dra7-dspeve-thermal.dtsi"
1742 #include "dra7-iva-thermal.dtsi"
f7397edf
K		 1743 };
1744
1745};
1746
1747&cpu_thermal {
1748 polling-delay = <500>; /* milliseconds */
6e58b8f1 1749};
ee6c7507
TK		 1750
1751/include/ "dra7xx-clocks.dtsi"
Linux kernel - Deliverables
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