projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / boot / dts / dra72-evm.dts
CommitLineData
38b248db
RN		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra72x.dtsi"
f56de327 11#include <dt-bindings/gpio/gpio.h>
a8d3b59c 12#include <dt-bindings/clk/ti-dra7-atl.h>
38b248db
RN		 13
14/ {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
17
18 memory {
19 device_type = "memory";
20 reg = <0x80000000 0x40000000>; /* 1024 MB */
21 };
5b434d7e 22
fadf0d0b
TV		 23 aliases {
24 display0 = &hdmi0;
25 };
26
5b434d7e
NM		 27 evm_3v3: fixedregulator-evm_3v3 {
28 compatible = "regulator-fixed";
29 regulator-name = "evm_3v3";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 };
f56de327 33
61085ee7
PU		 34 aic_dvdd: fixedregulator-aic_dvdd {
35 /* TPS77018DBVT */
36 compatible = "regulator-fixed";
37 regulator-name = "aic_dvdd";
38 vin-supply = <&evm_3v3>;
39 regulator-min-microvolt = <1800000>;
40 regulator-max-microvolt = <1800000>;
41 };
42
a238707d
KVA		 43 evm_3v3_sd: fixedregulator-sd {
44 compatible = "regulator-fixed";
45 regulator-name = "evm_3v3_sd";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 enable-active-high;
49 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
50 };
51
f56de327
RQ		 52 extcon_usb1: extcon_usb1 {
53 compatible = "linux,extcon-usb-gpio";
54 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
55 };
56
57 extcon_usb2: extcon_usb2 {
58 compatible = "linux,extcon-usb-gpio";
59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
60 };
fadf0d0b
TV		 61
62 hdmi0: connector {
63 compatible = "hdmi-connector";
64 label = "hdmi";
65
66 type = "a";
67
68 port {
69 hdmi_connector_in: endpoint {
70 remote-endpoint = <&tpd12s015_out>;
71 };
72 };
73 };
74
75 tpd12s015: encoder {
76 compatible = "ti,tpd12s015";
77
78 pinctrl-names = "default";
79 pinctrl-0 = <&tpd12s015_pins>;
80
81 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
82 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
83 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
84
85 ports {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 port@0 {
90 reg = <0>;
91
92 tpd12s015_in: endpoint {
93 remote-endpoint = <&hdmi_out>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 tpd12s015_out: endpoint {
101 remote-endpoint = <&hdmi_connector_in>;
102 };
103 };
104 };
105 };
a8d3b59c
PU		 106
107 sound0: sound@0 {
108 compatible = "simple-audio-card";
109 simple-audio-card,name = "DRA7xx-EVM";
110 simple-audio-card,widgets =
111 "Headphone", "Headphone Jack",
112 "Line", "Line Out",
113 "Microphone", "Mic Jack",
114 "Line", "Line In";
115 simple-audio-card,routing =
116 "Headphone Jack", "HPLOUT",
117 "Headphone Jack", "HPROUT",
118 "Line Out", "LLOUT",
119 "Line Out", "RLOUT",
120 "MIC3L", "Mic Jack",
121 "MIC3R", "Mic Jack",
122 "Mic Jack", "Mic Bias",
123 "LINE1L", "Line In",
124 "LINE1R", "Line In";
125 simple-audio-card,format = "dsp_b";
126 simple-audio-card,bitclock-master = <&sound0_master>;
127 simple-audio-card,frame-master = <&sound0_master>;
128 simple-audio-card,bitclock-inversion;
129
130 sound0_master: simple-audio-card,cpu {
131 sound-dai = <&mcasp3>;
132 system-clock-frequency = <5644800>;
133 };
134
135 simple-audio-card,codec {
136 sound-dai = <&tlv320aic3106>;
137 clocks = <&atl_clkin2_ck>;
138 };
139 };
38b248db
RN		 140};
141
7e9711aa
K		 142&dra7_pmx_core {
143 i2c1_pins: pinmux_i2c1_pins {
144 pinctrl-single,pins = <
9255ea84
JMC		 145 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
146 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
7e9711aa
K		 147 >;
148 };
09d4993c 149
fadf0d0b
TV		 150 i2c5_pins: pinmux_i2c5_pins {
151 pinctrl-single,pins = <
9255ea84
JMC		 152 DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
153 DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
fadf0d0b
TV		 154 >;
155 };
156
6ddd5fce
PU		 157 i2c5_pins: pinmux_i2c5_pins {
158 pinctrl-single,pins = <
9255ea84
JMC		 159 DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
160 DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
6ddd5fce
PU		 161 >;
162 };
163
09d4993c
RQ		 164 nand_default: nand_default {
165 pinctrl-single,pins = <
9255ea84
JMC		 166 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
167 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
168 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
169 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
170 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
171 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
172 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
173 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
174 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
175 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
176 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
177 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
178 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
179 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
180 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
181 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
182 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
183 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
184 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
185 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
186 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
187 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
09d4993c
RQ		 188 >;
189 };
95cc6af8
GC		 190
191 usb1_pins: pinmux_usb1_pins {
192 pinctrl-single,pins = <
9255ea84 193 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
95cc6af8
GC		 194 >;
195 };
196
197 usb2_pins: pinmux_usb2_pins {
198 pinctrl-single,pins = <
9255ea84 199 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
95cc6af8
GC		 200 >;
201 };
829acd07
NM		 202
203 tps65917_pins_default: tps65917_pins_default {
204 pinctrl-single,pins = <
9255ea84 205 DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
829acd07
NM		 206 >;
207 };
5b434d7e
NM		 208
209 mmc1_pins_default: mmc1_pins_default {
210 pinctrl-single,pins = <
9255ea84
JMC		 211 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
212 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
213 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
214 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
215 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
216 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
217 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
5b434d7e
NM		 218 >;
219 };
220
221 mmc2_pins_default: mmc2_pins_default {
222 pinctrl-single,pins = <
9255ea84
JMC		 223 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
224 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
225 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
226 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
227 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
228 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
229 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
230 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
231 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
232 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
5b434d7e
NM		 233 >;
234 };
ea95af3c
RQ		 235
236 dcan1_pins_default: dcan1_pins_default {
237 pinctrl-single,pins = <
9255ea84
JMC		 238 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
239 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
ea95af3c
RQ		 240 >;
241 };
242
243 dcan1_pins_sleep: dcan1_pins_sleep {
244 pinctrl-single,pins = <
9255ea84
JMC		 245 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
246 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
ea95af3c
RQ		 247 >;
248 };
1f43c45d
M		 249
250 qspi1_pins: pinmux_qspi1_pins {
251 pinctrl-single,pins = <
9255ea84
JMC		 252 DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
253 DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
254 DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
255 DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
256 DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
257 DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
258 DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
1f43c45d
M		 259 >;
260 };
fadf0d0b
TV		 261
262 hdmi_pins: pinmux_hdmi_pins {
263 pinctrl-single,pins = <
9255ea84
JMC		 264 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
265 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
fadf0d0b
TV		 266 >;
267 };
268
269 tpd12s015_pins: pinmux_tpd12s015_pins {
270 pinctrl-single,pins = <
9255ea84 271 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
fadf0d0b
TV		 272 >;
273 };
a8d3b59c
PU		 274
275 atl_pins: pinmux_atl_pins {
276 pinctrl-single,pins = <
9255ea84
JMC		 277 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
278 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
a8d3b59c
PU		 279 >;
280 };
281
282 mcasp3_pins: pinmux_mcasp3_pins {
283 pinctrl-single,pins = <
9255ea84
JMC		 284 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
285 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
286 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
287 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
a8d3b59c
PU		 288 >;
289 };
290
291 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
292 pinctrl-single,pins = <
9255ea84
JMC		 293 DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
294 DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
295 DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
296 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
a8d3b59c
PU		 297 >;
298 };
7e9711aa
K		 299};
300
301&i2c1 {
302 status = "okay";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c1_pins>;
305 clock-frequency = <400000>;
b359c426
K		 306
307 tps65917: tps65917@58 {
308 compatible = "ti,tps65917";
309 reg = <0x58>;
310
829acd07
NM		 311 pinctrl-names = "default";
312 pinctrl-0 = <&tps65917_pins_default>;
313
b359c426 314 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
b359c426
K		 315 interrupt-controller;
316 #interrupt-cells = <2>;
317
318 ti,system-power-controller;
319
320 tps65917_pmic {
321 compatible = "ti,tps65917-pmic";
322
323 regulators {
324 smps1_reg: smps1 {
325 /* VDD_MPU */
326 regulator-name = "smps1";
327 regulator-min-microvolt = <850000>;
328 regulator-max-microvolt = <1250000>;
329 regulator-always-on;
330 regulator-boot-on;
331 };
332
333 smps2_reg: smps2 {
334 /* VDD_CORE */
335 regulator-name = "smps2";
336 regulator-min-microvolt = <850000>;
70fcaf92 337 regulator-max-microvolt = <1060000>;
b359c426
K		 338 regulator-boot-on;
339 regulator-always-on;
340 };
341
342 smps3_reg: smps3 {
343 /* VDD_GPU IVA DSPEVE */
344 regulator-name = "smps3";
345 regulator-min-microvolt = <850000>;
346 regulator-max-microvolt = <1250000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
350
351 smps4_reg: smps4 {
352 /* VDDS1V8 */
353 regulator-name = "smps4";
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <1800000>;
356 regulator-always-on;
357 regulator-boot-on;
358 };
359
360 smps5_reg: smps5 {
361 /* VDD_DDR */
362 regulator-name = "smps5";
363 regulator-min-microvolt = <1350000>;
364 regulator-max-microvolt = <1350000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
368
369 ldo1_reg: ldo1 {
370 /* LDO1_OUT --> SDIO */
371 regulator-name = "ldo1";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <3300000>;
d62ce9ff 374 regulator-always-on;
b359c426 375 regulator-boot-on;
6686f744 376 regulator-allow-bypass;
b359c426
K		 377 };
378
379 ldo2_reg: ldo2 {
380 /* LDO2_OUT --> TP1017 (UNUSED) */
381 regulator-name = "ldo2";
382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <3300000>;
6686f744 384 regulator-allow-bypass;
b359c426
K		 385 };
386
387 ldo3_reg: ldo3 {
388 /* VDDA_1V8_PHY */
389 regulator-name = "ldo3";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 regulator-boot-on;
393 regulator-always-on;
394 };
395
396 ldo5_reg: ldo5 {
397 /* VDDA_1V8_PLL */
398 regulator-name = "ldo5";
399 regulator-min-microvolt = <1800000>;
400 regulator-max-microvolt = <1800000>;
401 regulator-always-on;
402 regulator-boot-on;
403 };
404
405 ldo4_reg: ldo4 {
406 /* VDDA_3V_USB: VDDA_USBHS33 */
407 regulator-name = "ldo4";
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 regulator-boot-on;
411 };
412 };
413 };
ab1d3c84
NM		 414
415 tps65917_power_button {
416 compatible = "ti,palmas-pwrbutton";
417 interrupt-parent = <&tps65917>;
418 interrupts = <1 IRQ_TYPE_NONE>;
419 wakeup-source;
420 ti,palmas-long-press-seconds = <6>;
421 };
b359c426 422 };
f56de327
RQ		 423
424 pcf_gpio_21: gpio@21 {
425 compatible = "ti,pcf8575";
426 reg = <0x21>;
427 lines-initial-states = <0x1408>;
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-parent = <&gpio6>;
431 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
a8d3b59c
PU		 435
436 tlv320aic3106: tlv320aic3106@19 {
437 #sound-dai-cells = <0>;
438 compatible = "ti,tlv320aic3106";
439 reg = <0x19>;
440 adc-settle-ms = <40>;
441 ai3x-micbias-vg = <1>; /* 2.0V */
442 status = "okay";
443
444 /* Regulators */
445 AVDD-supply = <&evm_3v3>;
446 IOVDD-supply = <&evm_3v3>;
447 DRVDD-supply = <&evm_3v3>;
448 DVDD-supply = <&aic_dvdd>;
449 };
7e9711aa
K		 450};
451
fadf0d0b
TV		 452&i2c5 {
453 status = "okay";
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c5_pins>;
456 clock-frequency = <400000>;
457
458 pcf_hdmi: pcf8575@26 {
459 compatible = "nxp,pcf8575";
460 reg = <0x26>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 /*
464 * initial state is used here to keep the mdio interface
465 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
466 * VIN2_S0 driven high otherwise Ethernet stops working
467 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
468 */
469 lines-initial-states = <0x0f2b>;
6ddd5fce
PU		 470
471 p1 {
472 /* vin6_sel_s0: high: VIN6, low: audio */
473 gpio-hog;
474 gpios = <1 GPIO_ACTIVE_HIGH>;
475 output-low;
476 line-name = "vin6_sel_s0";
477 };
fadf0d0b
TV		 478 };
479};
480
38b248db
RN		 481&uart1 {
482 status = "okay";
317d1567
V		 483 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
484 <&dra7_pmx_core 0x3e0>;
38b248db 485};
09d4993c
RQ		 486
487&elm {
488 status = "okay";
489};
490
491&gpmc {
492 status = "okay";
493 pinctrl-names = "default";
494 pinctrl-0 = <&nand_default>;
495 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
496 nand@0,0 {
497 /* To use NAND, DIP switch SW5 must be set like so:
498 * SW5.1 (NAND_SELn) = ON (LOW)
499 * SW5.9 (GPMC_WPN) = OFF (HIGH)
500 */
501 reg = <0 0 4>; /* device IO registers */
502 ti,nand-ecc-opt = "bch8";
503 ti,elm-id = <&elm>;
504 nand-bus-width = <16>;
505 gpmc,device-width = <2>;
506 gpmc,sync-clk-ps = <0>;
507 gpmc,cs-on-ns = <0>;
508 gpmc,cs-rd-off-ns = <80>;
509 gpmc,cs-wr-off-ns = <80>;
510 gpmc,adv-on-ns = <0>;
511 gpmc,adv-rd-off-ns = <60>;
512 gpmc,adv-wr-off-ns = <60>;
513 gpmc,we-on-ns = <10>;
514 gpmc,we-off-ns = <50>;
515 gpmc,oe-on-ns = <4>;
516 gpmc,oe-off-ns = <40>;
517 gpmc,access-ns = <40>;
518 gpmc,wr-access-ns = <80>;
519 gpmc,rd-cycle-ns = <80>;
520 gpmc,wr-cycle-ns = <80>;
521 gpmc,bus-turnaround-ns = <0>;
522 gpmc,cycle2cycle-delay-ns = <0>;
523 gpmc,clk-activation-ns = <0>;
524 gpmc,wait-monitoring-ns = <0>;
525 gpmc,wr-data-mux-bus-ns = <0>;
526 /* MTD partition table */
527 /* All SPL-* partitions are sized to minimal length
528 * which can be independently programmable. For
529 * NAND flash this is equal to size of erase-block */
530 #address-cells = <1>;
531 #size-cells = <1>;
532 partition@0 {
533 label = "NAND.SPL";
534 reg = <0x00000000 0x000020000>;
535 };
536 partition@1 {
537 label = "NAND.SPL.backup1";
538 reg = <0x00020000 0x00020000>;
539 };
540 partition@2 {
541 label = "NAND.SPL.backup2";
542 reg = <0x00040000 0x00020000>;
543 };
544 partition@3 {
545 label = "NAND.SPL.backup3";
546 reg = <0x00060000 0x00020000>;
547 };
548 partition@4 {
549 label = "NAND.u-boot-spl-os";
550 reg = <0x00080000 0x00040000>;
551 };
552 partition@5 {
553 label = "NAND.u-boot";
554 reg = <0x000c0000 0x00100000>;
555 };
556 partition@6 {
557 label = "NAND.u-boot-env";
558 reg = <0x001c0000 0x00020000>;
559 };
560 partition@7 {
561 label = "NAND.u-boot-env.backup1";
562 reg = <0x001e0000 0x00020000>;
563 };
564 partition@8 {
565 label = "NAND.kernel";
566 reg = <0x00200000 0x00800000>;
567 };
568 partition@9 {
569 label = "NAND.file-system";
570 reg = <0x00a00000 0x0f600000>;
571 };
572 };
573};
95cc6af8 574
7a15c8e7
RQ		 575&usb2_phy1 {
576 phy-supply = <&ldo4_reg>;
577};
578
579&usb2_phy2 {
580 phy-supply = <&ldo4_reg>;
581};
582
a7b0aa19
RQ		 583&omap_dwc3_1 {
584 extcon = <&extcon_usb1>;
585};
586
587&omap_dwc3_2 {
588 extcon = <&extcon_usb2>;
589};
590
95cc6af8
GC		 591&usb1 {
592 dr_mode = "peripheral";
593 pinctrl-names = "default";
594 pinctrl-0 = <&usb1_pins>;
595};
596
597&usb2 {
598 dr_mode = "host";
599 pinctrl-names = "default";
600 pinctrl-0 = <&usb2_pins>;
601};
5b434d7e
NM		 602
603&mmc1 {
604 status = "okay";
605 pinctrl-names = "default";
606 pinctrl-0 = <&mmc1_pins_default>;
a238707d
KVA		 607 vmmc-supply = <&evm_3v3_sd>;
608 vmmc_aux-supply = <&ldo1_reg>;
5b434d7e
NM		 609 bus-width = <4>;
610 /*
611 * SDCD signal is not being used here - using the fact that GPIO mode
612 * is a viable alternative
613 */
267068d8 614 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
e23b27db 615 max-frequency = <192000000>;
5b434d7e
NM		 616};
617
618&mmc2 {
619 /* SW5-3 in ON position */
620 status = "okay";
621 pinctrl-names = "default";
622 pinctrl-0 = <&mmc2_pins_default>;
623
624 vmmc-supply = <&evm_3v3>;
625 bus-width = <8>;
626 ti,non-removable;
e23b27db 627 max-frequency = <192000000>;
5b434d7e 628};
d5475152
M		 629
630&dra7_pmx_core {
631 cpsw_default: cpsw_default {
632 pinctrl-single,pins = <
633 /* Slave 2 */
9255ea84
JMC		 634 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
635 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
636 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
637 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
638 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
639 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
640 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
641 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
642 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
643 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
644 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
645 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
d5475152
M		 646 >;
647
648 };
649
650 cpsw_sleep: cpsw_sleep {
651 pinctrl-single,pins = <
652 /* Slave 2 */
9255ea84
JMC		 653 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
654 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
655 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
656 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
657 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
658 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
659 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
660 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
661 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
662 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
663 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
664 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
d5475152
M		 665 >;
666 };
667
668 davinci_mdio_default: davinci_mdio_default {
669 pinctrl-single,pins = <
670 /* MDIO */
9255ea84
JMC		 671 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
672 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
d5475152
M		 673 >;
674 };
675
676 davinci_mdio_sleep: davinci_mdio_sleep {
677 pinctrl-single,pins = <
9255ea84
JMC		 678 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
679 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
d5475152
M		 680 >;
681 };
682};
683
684&mac {
685 status = "okay";
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&cpsw_default>;
688 pinctrl-1 = <&cpsw_sleep>;
ad548430 689 slaves = <1>;
36958598 690 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
d5475152
M		 691};
692
ad548430 693&cpsw_emac0 {
d5475152
M		 694 phy_id = <&davinci_mdio>, <3>;
695 phy-mode = "rgmii";
696};
697
698&davinci_mdio {
699 pinctrl-names = "default", "sleep";
700 pinctrl-0 = <&davinci_mdio_default>;
701 pinctrl-1 = <&davinci_mdio_sleep>;
d5475152 702};
ea95af3c
RQ		 703
704&dcan1 {
705 status = "ok";
2acb5c30
RQ		 706 pinctrl-names = "default", "sleep", "active";
707 pinctrl-0 = <&dcan1_pins_sleep>;
ea95af3c 708 pinctrl-1 = <&dcan1_pins_sleep>;
2acb5c30 709 pinctrl-2 = <&dcan1_pins_default>;
ea95af3c 710};
1f43c45d
M		 711
712&qspi {
713 status = "okay";
714 pinctrl-names = "default";
715 pinctrl-0 = <&qspi1_pins>;
716
717 spi-max-frequency = <48000000>;
718 m25p80@0 {
719 compatible = "s25fl256s1";
720 spi-max-frequency = <48000000>;
721 reg = <0>;
722 spi-tx-bus-width = <1>;
723 spi-rx-bus-width = <4>;
724 spi-cpol;
725 spi-cpha;
726 #address-cells = <1>;
727 #size-cells = <1>;
728
729 /* MTD partition table.
730 * The ROM checks the first four physical blocks
731 * for a valid file to boot and the flash here is
732 * 64KiB block size.
733 */
734 partition@0 {
735 label = "QSPI.SPL";
736 reg = <0x00000000 0x000010000>;
737 };
738 partition@1 {
739 label = "QSPI.SPL.backup1";
740 reg = <0x00010000 0x00010000>;
741 };
742 partition@2 {
743 label = "QSPI.SPL.backup2";
744 reg = <0x00020000 0x00010000>;
745 };
746 partition@3 {
747 label = "QSPI.SPL.backup3";
748 reg = <0x00030000 0x00010000>;
749 };
750 partition@4 {
751 label = "QSPI.u-boot";
752 reg = <0x00040000 0x00100000>;
753 };
754 partition@5 {
755 label = "QSPI.u-boot-spl-os";
756 reg = <0x00140000 0x00080000>;
757 };
758 partition@6 {
759 label = "QSPI.u-boot-env";
760 reg = <0x001c0000 0x00010000>;
761 };
762 partition@7 {
763 label = "QSPI.u-boot-env.backup1";
764 reg = <0x001d0000 0x0010000>;
765 };
766 partition@8 {
767 label = "QSPI.kernel";
768 reg = <0x001e0000 0x0800000>;
769 };
770 partition@9 {
771 label = "QSPI.file-system";
772 reg = <0x009e0000 0x01620000>;
773 };
774 };
775};
fadf0d0b
TV		 776
777&dss {
778 status = "ok";
779
780 vdda_video-supply = <&ldo5_reg>;
781};
782
783&hdmi {
784 status = "ok";
785 vdda-supply = <&ldo3_reg>;
786
787 pinctrl-names = "default";
788 pinctrl-0 = <&hdmi_pins>;
789
790 port {
791 hdmi_out: endpoint {
792 remote-endpoint = <&tpd12s015_in>;
793 };
794 };
795};
a8d3b59c
PU		 796
797&atl {
798 pinctrl-names = "default";
799 pinctrl-0 = <&atl_pins>;
800
801 assigned-clocks = <&abe_dpll_sys_clk_mux>,
802 <&atl_gfclk_mux>,
803 <&dpll_abe_ck>,
804 <&dpll_abe_m2x2_ck>,
805 <&atl_clkin2_ck>;
806 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
807 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
808
809 status = "okay";
810
811 atl2 {
812 bws = <DRA7_ATL_WS_MCASP2_FSX>;
813 aws = <DRA7_ATL_WS_MCASP3_FSX>;
814 };
815};
816
817&mcasp3 {
818 #sound-dai-cells = <0>;
819 pinctrl-names = "default", "sleep";
820 pinctrl-0 = <&mcasp3_pins>;
821 pinctrl-1 = <&mcasp3_sleep_pins>;
822
823 assigned-clocks = <&mcasp3_ahclkx_mux>;
824 assigned-clock-parents = <&atl_clkin2_ck>;
825
826 status = "okay";
827
828 op-mode = <0>; /* MCASP_IIS_MODE */
829 tdm-slots = <2>;
830 /* 4 serializer */
831 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
832 1 2 0 0
833 >;
834};
43914a35
SA		 835
836&mailbox5 {
837 status = "okay";
838 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
839 status = "okay";
840 };
841 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
842 status = "okay";
843 };
844};
845
846&mailbox6 {
847 status = "okay";
848 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
849 status = "okay";
850 };
851};
Linux kernel - Deliverables
This page took 0.145572 seconds and 5 git commands to generate.