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Merge branch 'mkp-fixes' into fixes
[deliverable/linux.git] / arch / arm / boot / dts / dra72-evm.dts
CommitLineData
38b248db
RN		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra72x.dtsi"
f56de327 11#include <dt-bindings/gpio/gpio.h>
a8d3b59c 12#include <dt-bindings/clk/ti-dra7-atl.h>
38b248db
RN		 13
14/ {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
17
18 memory {
19 device_type = "memory";
20 reg = <0x80000000 0x40000000>; /* 1024 MB */
21 };
5b434d7e 22
fadf0d0b
TV		 23 aliases {
24 display0 = &hdmi0;
25 };
26
5b434d7e
NM		 27 evm_3v3: fixedregulator-evm_3v3 {
28 compatible = "regulator-fixed";
29 regulator-name = "evm_3v3";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 };
f56de327 33
61085ee7
PU		 34 aic_dvdd: fixedregulator-aic_dvdd {
35 /* TPS77018DBVT */
36 compatible = "regulator-fixed";
37 regulator-name = "aic_dvdd";
38 vin-supply = <&evm_3v3>;
39 regulator-min-microvolt = <1800000>;
40 regulator-max-microvolt = <1800000>;
41 };
42
a238707d
KVA		 43 evm_3v3_sd: fixedregulator-sd {
44 compatible = "regulator-fixed";
45 regulator-name = "evm_3v3_sd";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 enable-active-high;
49 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
50 };
51
f56de327
RQ		 52 extcon_usb1: extcon_usb1 {
53 compatible = "linux,extcon-usb-gpio";
54 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
55 };
56
57 extcon_usb2: extcon_usb2 {
58 compatible = "linux,extcon-usb-gpio";
59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
60 };
fadf0d0b
TV		 61
62 hdmi0: connector {
63 compatible = "hdmi-connector";
64 label = "hdmi";
65
66 type = "a";
67
68 port {
69 hdmi_connector_in: endpoint {
70 remote-endpoint = <&tpd12s015_out>;
71 };
72 };
73 };
74
75 tpd12s015: encoder {
76 compatible = "ti,tpd12s015";
77
78 pinctrl-names = "default";
79 pinctrl-0 = <&tpd12s015_pins>;
80
81 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
82 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
83 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
84
85 ports {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 port@0 {
90 reg = <0>;
91
92 tpd12s015_in: endpoint {
93 remote-endpoint = <&hdmi_out>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 tpd12s015_out: endpoint {
101 remote-endpoint = <&hdmi_connector_in>;
102 };
103 };
104 };
105 };
a8d3b59c
PU		 106
107 sound0: sound@0 {
108 compatible = "simple-audio-card";
109 simple-audio-card,name = "DRA7xx-EVM";
110 simple-audio-card,widgets =
111 "Headphone", "Headphone Jack",
112 "Line", "Line Out",
113 "Microphone", "Mic Jack",
114 "Line", "Line In";
115 simple-audio-card,routing =
116 "Headphone Jack", "HPLOUT",
117 "Headphone Jack", "HPROUT",
118 "Line Out", "LLOUT",
119 "Line Out", "RLOUT",
120 "MIC3L", "Mic Jack",
121 "MIC3R", "Mic Jack",
122 "Mic Jack", "Mic Bias",
123 "LINE1L", "Line In",
124 "LINE1R", "Line In";
125 simple-audio-card,format = "dsp_b";
126 simple-audio-card,bitclock-master = <&sound0_master>;
127 simple-audio-card,frame-master = <&sound0_master>;
128 simple-audio-card,bitclock-inversion;
129
130 sound0_master: simple-audio-card,cpu {
131 sound-dai = <&mcasp3>;
132 system-clock-frequency = <5644800>;
133 };
134
135 simple-audio-card,codec {
136 sound-dai = <&tlv320aic3106>;
137 clocks = <&atl_clkin2_ck>;
138 };
139 };
38b248db
RN		 140};
141
7e9711aa
K		 142&dra7_pmx_core {
143 i2c1_pins: pinmux_i2c1_pins {
144 pinctrl-single,pins = <
145 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
146 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
147 >;
148 };
09d4993c 149
fadf0d0b
TV		 150 i2c5_pins: pinmux_i2c5_pins {
151 pinctrl-single,pins = <
152 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
153 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
154 >;
155 };
156
6ddd5fce
PU		 157 i2c5_pins: pinmux_i2c5_pins {
158 pinctrl-single,pins = <
159 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
160 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
161 >;
162 };
163
09d4993c
RQ		 164 nand_default: nand_default {
165 pinctrl-single,pins = <
166 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
167 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
168 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
169 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
170 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
171 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
172 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
173 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
174 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
175 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
176 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
177 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
178 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
179 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
180 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
181 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
182 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
183 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
184 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
185 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
186 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
187 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
188 >;
189 };
95cc6af8
GC		 190
191 usb1_pins: pinmux_usb1_pins {
192 pinctrl-single,pins = <
193 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
194 >;
195 };
196
197 usb2_pins: pinmux_usb2_pins {
198 pinctrl-single,pins = <
199 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
200 >;
201 };
829acd07
NM		 202
203 tps65917_pins_default: tps65917_pins_default {
204 pinctrl-single,pins = <
205 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
206 >;
207 };
5b434d7e
NM		 208
209 mmc1_pins_default: mmc1_pins_default {
210 pinctrl-single,pins = <
211 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
212 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
213 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
214 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
215 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
216 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
217 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
218 >;
219 };
220
221 mmc2_pins_default: mmc2_pins_default {
222 pinctrl-single,pins = <
223 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
224 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
225 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
226 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
227 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
228 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
229 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
230 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
231 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
232 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
233 >;
234 };
ea95af3c
RQ		 235
236 dcan1_pins_default: dcan1_pins_default {
237 pinctrl-single,pins = <
d80d581b
RQ		 238 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
239 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
ea95af3c
RQ		 240 >;
241 };
242
243 dcan1_pins_sleep: dcan1_pins_sleep {
244 pinctrl-single,pins = <
d80d581b
RQ		 245 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
246 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
ea95af3c
RQ		 247 >;
248 };
1f43c45d
M		 249
250 qspi1_pins: pinmux_qspi1_pins {
251 pinctrl-single,pins = <
252 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
253 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
254 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
255 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
256 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
257 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
258 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
259 >;
260 };
fadf0d0b
TV		 261
262 hdmi_pins: pinmux_hdmi_pins {
263 pinctrl-single,pins = <
264 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
265 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
266 >;
267 };
268
269 tpd12s015_pins: pinmux_tpd12s015_pins {
270 pinctrl-single,pins = <
271 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
272 >;
273 };
a8d3b59c
PU		 274
275 atl_pins: pinmux_atl_pins {
276 pinctrl-single,pins = <
277 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
278 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
279 >;
280 };
281
282 mcasp3_pins: pinmux_mcasp3_pins {
283 pinctrl-single,pins = <
284 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
285 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
286 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
287 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
288 >;
289 };
290
291 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
292 pinctrl-single,pins = <
293 0x324 (PIN_INPUT_PULLDOWN | MUX_MODE15)
294 0x328 (PIN_INPUT_PULLDOWN | MUX_MODE15)
295 0x32c (PIN_INPUT_PULLDOWN | MUX_MODE15)
296 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE15)
297 >;
298 };
7e9711aa
K		 299};
300
301&i2c1 {
302 status = "okay";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c1_pins>;
305 clock-frequency = <400000>;
b359c426
K		 306
307 tps65917: tps65917@58 {
308 compatible = "ti,tps65917";
309 reg = <0x58>;
310
829acd07
NM		 311 pinctrl-names = "default";
312 pinctrl-0 = <&tps65917_pins_default>;
313
b359c426 314 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
b359c426
K		 315 interrupt-controller;
316 #interrupt-cells = <2>;
317
318 ti,system-power-controller;
319
320 tps65917_pmic {
321 compatible = "ti,tps65917-pmic";
322
323 regulators {
324 smps1_reg: smps1 {
325 /* VDD_MPU */
326 regulator-name = "smps1";
327 regulator-min-microvolt = <850000>;
328 regulator-max-microvolt = <1250000>;
329 regulator-always-on;
330 regulator-boot-on;
331 };
332
333 smps2_reg: smps2 {
334 /* VDD_CORE */
335 regulator-name = "smps2";
336 regulator-min-microvolt = <850000>;
70fcaf92 337 regulator-max-microvolt = <1060000>;
b359c426
K		 338 regulator-boot-on;
339 regulator-always-on;
340 };
341
342 smps3_reg: smps3 {
343 /* VDD_GPU IVA DSPEVE */
344 regulator-name = "smps3";
345 regulator-min-microvolt = <850000>;
346 regulator-max-microvolt = <1250000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
350
351 smps4_reg: smps4 {
352 /* VDDS1V8 */
353 regulator-name = "smps4";
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <1800000>;
356 regulator-always-on;
357 regulator-boot-on;
358 };
359
360 smps5_reg: smps5 {
361 /* VDD_DDR */
362 regulator-name = "smps5";
363 regulator-min-microvolt = <1350000>;
364 regulator-max-microvolt = <1350000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
368
369 ldo1_reg: ldo1 {
370 /* LDO1_OUT --> SDIO */
371 regulator-name = "ldo1";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <3300000>;
d62ce9ff 374 regulator-always-on;
b359c426
K		 375 regulator-boot-on;
376 };
377
378 ldo2_reg: ldo2 {
379 /* LDO2_OUT --> TP1017 (UNUSED) */
380 regulator-name = "ldo2";
381 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <3300000>;
383 };
384
385 ldo3_reg: ldo3 {
386 /* VDDA_1V8_PHY */
387 regulator-name = "ldo3";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 ldo5_reg: ldo5 {
395 /* VDDA_1V8_PLL */
396 regulator-name = "ldo5";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
399 regulator-always-on;
400 regulator-boot-on;
401 };
402
403 ldo4_reg: ldo4 {
404 /* VDDA_3V_USB: VDDA_USBHS33 */
405 regulator-name = "ldo4";
406 regulator-min-microvolt = <3300000>;
407 regulator-max-microvolt = <3300000>;
408 regulator-boot-on;
409 };
410 };
411 };
ab1d3c84
NM		 412
413 tps65917_power_button {
414 compatible = "ti,palmas-pwrbutton";
415 interrupt-parent = <&tps65917>;
416 interrupts = <1 IRQ_TYPE_NONE>;
417 wakeup-source;
418 ti,palmas-long-press-seconds = <6>;
419 };
b359c426 420 };
f56de327
RQ		 421
422 pcf_gpio_21: gpio@21 {
423 compatible = "ti,pcf8575";
424 reg = <0x21>;
425 lines-initial-states = <0x1408>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-parent = <&gpio6>;
429 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 };
a8d3b59c
PU		 433
434 tlv320aic3106: tlv320aic3106@19 {
435 #sound-dai-cells = <0>;
436 compatible = "ti,tlv320aic3106";
437 reg = <0x19>;
438 adc-settle-ms = <40>;
439 ai3x-micbias-vg = <1>; /* 2.0V */
440 status = "okay";
441
442 /* Regulators */
443 AVDD-supply = <&evm_3v3>;
444 IOVDD-supply = <&evm_3v3>;
445 DRVDD-supply = <&evm_3v3>;
446 DVDD-supply = <&aic_dvdd>;
447 };
7e9711aa
K		 448};
449
fadf0d0b
TV		 450&i2c5 {
451 status = "okay";
452 pinctrl-names = "default";
453 pinctrl-0 = <&i2c5_pins>;
454 clock-frequency = <400000>;
455
456 pcf_hdmi: pcf8575@26 {
457 compatible = "nxp,pcf8575";
458 reg = <0x26>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 /*
462 * initial state is used here to keep the mdio interface
463 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
464 * VIN2_S0 driven high otherwise Ethernet stops working
465 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
466 */
467 lines-initial-states = <0x0f2b>;
6ddd5fce
PU		 468
469 p1 {
470 /* vin6_sel_s0: high: VIN6, low: audio */
471 gpio-hog;
472 gpios = <1 GPIO_ACTIVE_HIGH>;
473 output-low;
474 line-name = "vin6_sel_s0";
475 };
fadf0d0b
TV		 476 };
477};
478
38b248db
RN		 479&uart1 {
480 status = "okay";
481};
09d4993c
RQ		 482
483&elm {
484 status = "okay";
485};
486
487&gpmc {
488 status = "okay";
489 pinctrl-names = "default";
490 pinctrl-0 = <&nand_default>;
491 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
492 nand@0,0 {
493 /* To use NAND, DIP switch SW5 must be set like so:
494 * SW5.1 (NAND_SELn) = ON (LOW)
495 * SW5.9 (GPMC_WPN) = OFF (HIGH)
496 */
497 reg = <0 0 4>; /* device IO registers */
498 ti,nand-ecc-opt = "bch8";
499 ti,elm-id = <&elm>;
500 nand-bus-width = <16>;
501 gpmc,device-width = <2>;
502 gpmc,sync-clk-ps = <0>;
503 gpmc,cs-on-ns = <0>;
504 gpmc,cs-rd-off-ns = <80>;
505 gpmc,cs-wr-off-ns = <80>;
506 gpmc,adv-on-ns = <0>;
507 gpmc,adv-rd-off-ns = <60>;
508 gpmc,adv-wr-off-ns = <60>;
509 gpmc,we-on-ns = <10>;
510 gpmc,we-off-ns = <50>;
511 gpmc,oe-on-ns = <4>;
512 gpmc,oe-off-ns = <40>;
513 gpmc,access-ns = <40>;
514 gpmc,wr-access-ns = <80>;
515 gpmc,rd-cycle-ns = <80>;
516 gpmc,wr-cycle-ns = <80>;
517 gpmc,bus-turnaround-ns = <0>;
518 gpmc,cycle2cycle-delay-ns = <0>;
519 gpmc,clk-activation-ns = <0>;
520 gpmc,wait-monitoring-ns = <0>;
521 gpmc,wr-data-mux-bus-ns = <0>;
522 /* MTD partition table */
523 /* All SPL-* partitions are sized to minimal length
524 * which can be independently programmable. For
525 * NAND flash this is equal to size of erase-block */
526 #address-cells = <1>;
527 #size-cells = <1>;
528 partition@0 {
529 label = "NAND.SPL";
530 reg = <0x00000000 0x000020000>;
531 };
532 partition@1 {
533 label = "NAND.SPL.backup1";
534 reg = <0x00020000 0x00020000>;
535 };
536 partition@2 {
537 label = "NAND.SPL.backup2";
538 reg = <0x00040000 0x00020000>;
539 };
540 partition@3 {
541 label = "NAND.SPL.backup3";
542 reg = <0x00060000 0x00020000>;
543 };
544 partition@4 {
545 label = "NAND.u-boot-spl-os";
546 reg = <0x00080000 0x00040000>;
547 };
548 partition@5 {
549 label = "NAND.u-boot";
550 reg = <0x000c0000 0x00100000>;
551 };
552 partition@6 {
553 label = "NAND.u-boot-env";
554 reg = <0x001c0000 0x00020000>;
555 };
556 partition@7 {
557 label = "NAND.u-boot-env.backup1";
558 reg = <0x001e0000 0x00020000>;
559 };
560 partition@8 {
561 label = "NAND.kernel";
562 reg = <0x00200000 0x00800000>;
563 };
564 partition@9 {
565 label = "NAND.file-system";
566 reg = <0x00a00000 0x0f600000>;
567 };
568 };
569};
95cc6af8 570
7a15c8e7
RQ		 571&usb2_phy1 {
572 phy-supply = <&ldo4_reg>;
573};
574
575&usb2_phy2 {
576 phy-supply = <&ldo4_reg>;
577};
578
a7b0aa19
RQ		 579&omap_dwc3_1 {
580 extcon = <&extcon_usb1>;
581};
582
583&omap_dwc3_2 {
584 extcon = <&extcon_usb2>;
585};
586
95cc6af8
GC		 587&usb1 {
588 dr_mode = "peripheral";
589 pinctrl-names = "default";
590 pinctrl-0 = <&usb1_pins>;
591};
592
593&usb2 {
594 dr_mode = "host";
595 pinctrl-names = "default";
596 pinctrl-0 = <&usb2_pins>;
597};
5b434d7e
NM		 598
599&mmc1 {
600 status = "okay";
601 pinctrl-names = "default";
602 pinctrl-0 = <&mmc1_pins_default>;
a238707d
KVA		 603 vmmc-supply = <&evm_3v3_sd>;
604 vmmc_aux-supply = <&ldo1_reg>;
5b434d7e
NM		 605 bus-width = <4>;
606 /*
607 * SDCD signal is not being used here - using the fact that GPIO mode
608 * is a viable alternative
609 */
267068d8 610 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
e23b27db 611 max-frequency = <192000000>;
5b434d7e
NM		 612};
613
614&mmc2 {
615 /* SW5-3 in ON position */
616 status = "okay";
617 pinctrl-names = "default";
618 pinctrl-0 = <&mmc2_pins_default>;
619
620 vmmc-supply = <&evm_3v3>;
621 bus-width = <8>;
622 ti,non-removable;
e23b27db 623 max-frequency = <192000000>;
5b434d7e 624};
d5475152
M		 625
626&dra7_pmx_core {
627 cpsw_default: cpsw_default {
628 pinctrl-single,pins = <
629 /* Slave 2 */
630 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
631 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
632 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
633 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
634 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
635 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
636 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
637 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
638 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
639 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
640 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
641 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
642 >;
643
644 };
645
646 cpsw_sleep: cpsw_sleep {
647 pinctrl-single,pins = <
648 /* Slave 2 */
649 0x198 (MUX_MODE15)
650 0x19c (MUX_MODE15)
651 0x1a0 (MUX_MODE15)
652 0x1a4 (MUX_MODE15)
653 0x1a8 (MUX_MODE15)
654 0x1ac (MUX_MODE15)
655 0x1b0 (MUX_MODE15)
656 0x1b4 (MUX_MODE15)
657 0x1b8 (MUX_MODE15)
658 0x1bc (MUX_MODE15)
659 0x1c0 (MUX_MODE15)
660 0x1c4 (MUX_MODE15)
661 >;
662 };
663
664 davinci_mdio_default: davinci_mdio_default {
665 pinctrl-single,pins = <
666 /* MDIO */
667 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
668 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
669 >;
670 };
671
672 davinci_mdio_sleep: davinci_mdio_sleep {
673 pinctrl-single,pins = <
674 0x23c (MUX_MODE15)
675 0x240 (MUX_MODE15)
676 >;
677 };
678};
679
680&mac {
681 status = "okay";
682 pinctrl-names = "default", "sleep";
683 pinctrl-0 = <&cpsw_default>;
684 pinctrl-1 = <&cpsw_sleep>;
ad548430 685 slaves = <1>;
36958598 686 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
d5475152
M		 687};
688
ad548430 689&cpsw_emac0 {
d5475152
M		 690 phy_id = <&davinci_mdio>, <3>;
691 phy-mode = "rgmii";
692};
693
694&davinci_mdio {
695 pinctrl-names = "default", "sleep";
696 pinctrl-0 = <&davinci_mdio_default>;
697 pinctrl-1 = <&davinci_mdio_sleep>;
d5475152 698};
ea95af3c
RQ		 699
700&dcan1 {
701 status = "ok";
2acb5c30
RQ		 702 pinctrl-names = "default", "sleep", "active";
703 pinctrl-0 = <&dcan1_pins_sleep>;
ea95af3c 704 pinctrl-1 = <&dcan1_pins_sleep>;
2acb5c30 705 pinctrl-2 = <&dcan1_pins_default>;
ea95af3c 706};
1f43c45d
M		 707
708&qspi {
709 status = "okay";
710 pinctrl-names = "default";
711 pinctrl-0 = <&qspi1_pins>;
712
713 spi-max-frequency = <48000000>;
714 m25p80@0 {
715 compatible = "s25fl256s1";
716 spi-max-frequency = <48000000>;
717 reg = <0>;
718 spi-tx-bus-width = <1>;
719 spi-rx-bus-width = <4>;
720 spi-cpol;
721 spi-cpha;
722 #address-cells = <1>;
723 #size-cells = <1>;
724
725 /* MTD partition table.
726 * The ROM checks the first four physical blocks
727 * for a valid file to boot and the flash here is
728 * 64KiB block size.
729 */
730 partition@0 {
731 label = "QSPI.SPL";
732 reg = <0x00000000 0x000010000>;
733 };
734 partition@1 {
735 label = "QSPI.SPL.backup1";
736 reg = <0x00010000 0x00010000>;
737 };
738 partition@2 {
739 label = "QSPI.SPL.backup2";
740 reg = <0x00020000 0x00010000>;
741 };
742 partition@3 {
743 label = "QSPI.SPL.backup3";
744 reg = <0x00030000 0x00010000>;
745 };
746 partition@4 {
747 label = "QSPI.u-boot";
748 reg = <0x00040000 0x00100000>;
749 };
750 partition@5 {
751 label = "QSPI.u-boot-spl-os";
752 reg = <0x00140000 0x00080000>;
753 };
754 partition@6 {
755 label = "QSPI.u-boot-env";
756 reg = <0x001c0000 0x00010000>;
757 };
758 partition@7 {
759 label = "QSPI.u-boot-env.backup1";
760 reg = <0x001d0000 0x0010000>;
761 };
762 partition@8 {
763 label = "QSPI.kernel";
764 reg = <0x001e0000 0x0800000>;
765 };
766 partition@9 {
767 label = "QSPI.file-system";
768 reg = <0x009e0000 0x01620000>;
769 };
770 };
771};
fadf0d0b
TV		 772
773&dss {
774 status = "ok";
775
776 vdda_video-supply = <&ldo5_reg>;
777};
778
779&hdmi {
780 status = "ok";
781 vdda-supply = <&ldo3_reg>;
782
783 pinctrl-names = "default";
784 pinctrl-0 = <&hdmi_pins>;
785
786 port {
787 hdmi_out: endpoint {
788 remote-endpoint = <&tpd12s015_in>;
789 };
790 };
791};
a8d3b59c
PU		 792
793&atl {
794 pinctrl-names = "default";
795 pinctrl-0 = <&atl_pins>;
796
797 assigned-clocks = <&abe_dpll_sys_clk_mux>,
798 <&atl_gfclk_mux>,
799 <&dpll_abe_ck>,
800 <&dpll_abe_m2x2_ck>,
801 <&atl_clkin2_ck>;
802 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
803 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
804
805 status = "okay";
806
807 atl2 {
808 bws = <DRA7_ATL_WS_MCASP2_FSX>;
809 aws = <DRA7_ATL_WS_MCASP3_FSX>;
810 };
811};
812
813&mcasp3 {
814 #sound-dai-cells = <0>;
815 pinctrl-names = "default", "sleep";
816 pinctrl-0 = <&mcasp3_pins>;
817 pinctrl-1 = <&mcasp3_sleep_pins>;
818
819 assigned-clocks = <&mcasp3_ahclkx_mux>;
820 assigned-clock-parents = <&atl_clkin2_ck>;
821
822 status = "okay";
823
824 op-mode = <0>; /* MCASP_IIS_MODE */
825 tdm-slots = <2>;
826 /* 4 serializer */
827 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
828 1 2 0 0
829 >;
830};
43914a35
SA		 831
832&mailbox5 {
833 status = "okay";
834 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
835 status = "okay";
836 };
837 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
838 status = "okay";
839 };
840};
841
842&mailbox6 {
843 status = "okay";
844 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
845 status = "okay";
846 };
847};
Linux kernel - Deliverables
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