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ARM: dts: dra7-evm: Enable the system mailboxes 5 and 6
[deliverable/linux.git] / arch / arm / boot / dts / dra72-evm.dts
CommitLineData
38b248db
RN		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra72x.dtsi"
f56de327 11#include <dt-bindings/gpio/gpio.h>
a8d3b59c 12#include <dt-bindings/clk/ti-dra7-atl.h>
38b248db
RN		 13
14/ {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
17
18 memory {
19 device_type = "memory";
20 reg = <0x80000000 0x40000000>; /* 1024 MB */
21 };
5b434d7e 22
fadf0d0b
TV		 23 aliases {
24 display0 = &hdmi0;
25 };
26
5b434d7e
NM		 27 evm_3v3: fixedregulator-evm_3v3 {
28 compatible = "regulator-fixed";
29 regulator-name = "evm_3v3";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 };
f56de327 33
61085ee7
PU		 34 aic_dvdd: fixedregulator-aic_dvdd {
35 /* TPS77018DBVT */
36 compatible = "regulator-fixed";
37 regulator-name = "aic_dvdd";
38 vin-supply = <&evm_3v3>;
39 regulator-min-microvolt = <1800000>;
40 regulator-max-microvolt = <1800000>;
41 };
42
a238707d
KVA		 43 evm_3v3_sd: fixedregulator-sd {
44 compatible = "regulator-fixed";
45 regulator-name = "evm_3v3_sd";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 enable-active-high;
49 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
50 };
51
f56de327
RQ		 52 extcon_usb1: extcon_usb1 {
53 compatible = "linux,extcon-usb-gpio";
54 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
55 };
56
57 extcon_usb2: extcon_usb2 {
58 compatible = "linux,extcon-usb-gpio";
59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
60 };
fadf0d0b
TV		 61
62 hdmi0: connector {
63 compatible = "hdmi-connector";
64 label = "hdmi";
65
66 type = "a";
67
68 port {
69 hdmi_connector_in: endpoint {
70 remote-endpoint = <&tpd12s015_out>;
71 };
72 };
73 };
74
75 tpd12s015: encoder {
76 compatible = "ti,tpd12s015";
77
78 pinctrl-names = "default";
79 pinctrl-0 = <&tpd12s015_pins>;
80
81 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
82 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
83 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
84
85 ports {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 port@0 {
90 reg = <0>;
91
92 tpd12s015_in: endpoint {
93 remote-endpoint = <&hdmi_out>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 tpd12s015_out: endpoint {
101 remote-endpoint = <&hdmi_connector_in>;
102 };
103 };
104 };
105 };
a8d3b59c
PU		 106
107 sound0: sound@0 {
108 compatible = "simple-audio-card";
109 simple-audio-card,name = "DRA7xx-EVM";
110 simple-audio-card,widgets =
111 "Headphone", "Headphone Jack",
112 "Line", "Line Out",
113 "Microphone", "Mic Jack",
114 "Line", "Line In";
115 simple-audio-card,routing =
116 "Headphone Jack", "HPLOUT",
117 "Headphone Jack", "HPROUT",
118 "Line Out", "LLOUT",
119 "Line Out", "RLOUT",
120 "MIC3L", "Mic Jack",
121 "MIC3R", "Mic Jack",
122 "Mic Jack", "Mic Bias",
123 "LINE1L", "Line In",
124 "LINE1R", "Line In";
125 simple-audio-card,format = "dsp_b";
126 simple-audio-card,bitclock-master = <&sound0_master>;
127 simple-audio-card,frame-master = <&sound0_master>;
128 simple-audio-card,bitclock-inversion;
129
130 sound0_master: simple-audio-card,cpu {
131 sound-dai = <&mcasp3>;
132 system-clock-frequency = <5644800>;
133 };
134
135 simple-audio-card,codec {
136 sound-dai = <&tlv320aic3106>;
137 clocks = <&atl_clkin2_ck>;
138 };
139 };
38b248db
RN		 140};
141
7e9711aa
K		 142&dra7_pmx_core {
143 i2c1_pins: pinmux_i2c1_pins {
144 pinctrl-single,pins = <
145 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
146 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
147 >;
148 };
09d4993c 149
fadf0d0b
TV		 150 i2c5_pins: pinmux_i2c5_pins {
151 pinctrl-single,pins = <
152 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
153 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
154 >;
155 };
156
6ddd5fce
PU		 157 i2c5_pins: pinmux_i2c5_pins {
158 pinctrl-single,pins = <
159 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
160 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
161 >;
162 };
163
09d4993c
RQ		 164 nand_default: nand_default {
165 pinctrl-single,pins = <
166 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
167 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
168 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
169 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
170 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
171 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
172 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
173 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
174 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
175 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
176 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
177 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
178 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
179 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
180 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
181 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
182 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
183 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
184 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
185 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
186 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
187 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
188 >;
189 };
95cc6af8
GC		 190
191 usb1_pins: pinmux_usb1_pins {
192 pinctrl-single,pins = <
193 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
194 >;
195 };
196
197 usb2_pins: pinmux_usb2_pins {
198 pinctrl-single,pins = <
199 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
200 >;
201 };
829acd07
NM		 202
203 tps65917_pins_default: tps65917_pins_default {
204 pinctrl-single,pins = <
205 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
206 >;
207 };
5b434d7e
NM		 208
209 mmc1_pins_default: mmc1_pins_default {
210 pinctrl-single,pins = <
211 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
212 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
213 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
214 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
215 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
216 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
217 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
218 >;
219 };
220
221 mmc2_pins_default: mmc2_pins_default {
222 pinctrl-single,pins = <
223 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
224 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
225 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
226 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
227 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
228 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
229 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
230 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
231 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
232 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
233 >;
234 };
ea95af3c
RQ		 235
236 dcan1_pins_default: dcan1_pins_default {
237 pinctrl-single,pins = <
d80d581b
RQ		 238 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
239 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
ea95af3c
RQ		 240 >;
241 };
242
243 dcan1_pins_sleep: dcan1_pins_sleep {
244 pinctrl-single,pins = <
d80d581b
RQ		 245 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
246 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
ea95af3c
RQ		 247 >;
248 };
1f43c45d
M		 249
250 qspi1_pins: pinmux_qspi1_pins {
251 pinctrl-single,pins = <
252 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
253 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
254 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
255 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
256 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
257 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
258 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
259 >;
260 };
fadf0d0b
TV		 261
262 hdmi_pins: pinmux_hdmi_pins {
263 pinctrl-single,pins = <
264 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
265 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
266 >;
267 };
268
269 tpd12s015_pins: pinmux_tpd12s015_pins {
270 pinctrl-single,pins = <
271 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
272 >;
273 };
a8d3b59c
PU		 274
275 atl_pins: pinmux_atl_pins {
276 pinctrl-single,pins = <
277 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
278 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
279 >;
280 };
281
282 mcasp3_pins: pinmux_mcasp3_pins {
283 pinctrl-single,pins = <
284 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
285 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
286 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
287 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
288 >;
289 };
290
291 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
292 pinctrl-single,pins = <
293 0x324 (PIN_INPUT_PULLDOWN | MUX_MODE15)
294 0x328 (PIN_INPUT_PULLDOWN | MUX_MODE15)
295 0x32c (PIN_INPUT_PULLDOWN | MUX_MODE15)
296 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE15)
297 >;
298 };
7e9711aa
K		 299};
300
301&i2c1 {
302 status = "okay";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c1_pins>;
305 clock-frequency = <400000>;
b359c426
K		 306
307 tps65917: tps65917@58 {
308 compatible = "ti,tps65917";
309 reg = <0x58>;
310
829acd07
NM		 311 pinctrl-names = "default";
312 pinctrl-0 = <&tps65917_pins_default>;
313
b359c426 314 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
b359c426
K		 315 interrupt-controller;
316 #interrupt-cells = <2>;
317
318 ti,system-power-controller;
319
320 tps65917_pmic {
321 compatible = "ti,tps65917-pmic";
322
323 regulators {
324 smps1_reg: smps1 {
325 /* VDD_MPU */
326 regulator-name = "smps1";
327 regulator-min-microvolt = <850000>;
328 regulator-max-microvolt = <1250000>;
329 regulator-always-on;
330 regulator-boot-on;
331 };
332
333 smps2_reg: smps2 {
334 /* VDD_CORE */
335 regulator-name = "smps2";
336 regulator-min-microvolt = <850000>;
70fcaf92 337 regulator-max-microvolt = <1060000>;
b359c426
K		 338 regulator-boot-on;
339 regulator-always-on;
340 };
341
342 smps3_reg: smps3 {
343 /* VDD_GPU IVA DSPEVE */
344 regulator-name = "smps3";
345 regulator-min-microvolt = <850000>;
346 regulator-max-microvolt = <1250000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
350
351 smps4_reg: smps4 {
352 /* VDDS1V8 */
353 regulator-name = "smps4";
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <1800000>;
356 regulator-always-on;
357 regulator-boot-on;
358 };
359
360 smps5_reg: smps5 {
361 /* VDD_DDR */
362 regulator-name = "smps5";
363 regulator-min-microvolt = <1350000>;
364 regulator-max-microvolt = <1350000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
368
369 ldo1_reg: ldo1 {
370 /* LDO1_OUT --> SDIO */
371 regulator-name = "ldo1";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <3300000>;
d62ce9ff 374 regulator-always-on;
b359c426
K		 375 regulator-boot-on;
376 };
377
378 ldo2_reg: ldo2 {
379 /* LDO2_OUT --> TP1017 (UNUSED) */
380 regulator-name = "ldo2";
381 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <3300000>;
383 };
384
385 ldo3_reg: ldo3 {
386 /* VDDA_1V8_PHY */
387 regulator-name = "ldo3";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 ldo5_reg: ldo5 {
395 /* VDDA_1V8_PLL */
396 regulator-name = "ldo5";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
399 regulator-always-on;
400 regulator-boot-on;
401 };
402
403 ldo4_reg: ldo4 {
404 /* VDDA_3V_USB: VDDA_USBHS33 */
405 regulator-name = "ldo4";
406 regulator-min-microvolt = <3300000>;
407 regulator-max-microvolt = <3300000>;
408 regulator-boot-on;
409 };
410 };
411 };
ab1d3c84
NM		 412
413 tps65917_power_button {
414 compatible = "ti,palmas-pwrbutton";
415 interrupt-parent = <&tps65917>;
416 interrupts = <1 IRQ_TYPE_NONE>;
417 wakeup-source;
418 ti,palmas-long-press-seconds = <6>;
419 };
b359c426 420 };
f56de327
RQ		 421
422 pcf_gpio_21: gpio@21 {
423 compatible = "ti,pcf8575";
424 reg = <0x21>;
425 lines-initial-states = <0x1408>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-parent = <&gpio6>;
429 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
ad548430
V		 432
433 cpsw_sel_s0 {
434 gpio-hog;
435 gpios = <4 GPIO_ACTIVE_HIGH>;
436 output-low;
437 };
f56de327 438 };
a8d3b59c
PU		 439
440 tlv320aic3106: tlv320aic3106@19 {
441 #sound-dai-cells = <0>;
442 compatible = "ti,tlv320aic3106";
443 reg = <0x19>;
444 adc-settle-ms = <40>;
445 ai3x-micbias-vg = <1>; /* 2.0V */
446 status = "okay";
447
448 /* Regulators */
449 AVDD-supply = <&evm_3v3>;
450 IOVDD-supply = <&evm_3v3>;
451 DRVDD-supply = <&evm_3v3>;
452 DVDD-supply = <&aic_dvdd>;
453 };
7e9711aa
K		 454};
455
fadf0d0b
TV		 456&i2c5 {
457 status = "okay";
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c5_pins>;
460 clock-frequency = <400000>;
461
462 pcf_hdmi: pcf8575@26 {
463 compatible = "nxp,pcf8575";
464 reg = <0x26>;
465 gpio-controller;
466 #gpio-cells = <2>;
467 /*
468 * initial state is used here to keep the mdio interface
469 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
470 * VIN2_S0 driven high otherwise Ethernet stops working
471 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
472 */
473 lines-initial-states = <0x0f2b>;
6ddd5fce
PU		 474
475 p1 {
476 /* vin6_sel_s0: high: VIN6, low: audio */
477 gpio-hog;
478 gpios = <1 GPIO_ACTIVE_HIGH>;
479 output-low;
480 line-name = "vin6_sel_s0";
481 };
fadf0d0b
TV		 482 };
483};
484
38b248db
RN		 485&uart1 {
486 status = "okay";
487};
09d4993c
RQ		 488
489&elm {
490 status = "okay";
491};
492
493&gpmc {
494 status = "okay";
495 pinctrl-names = "default";
496 pinctrl-0 = <&nand_default>;
497 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
498 nand@0,0 {
499 /* To use NAND, DIP switch SW5 must be set like so:
500 * SW5.1 (NAND_SELn) = ON (LOW)
501 * SW5.9 (GPMC_WPN) = OFF (HIGH)
502 */
503 reg = <0 0 4>; /* device IO registers */
504 ti,nand-ecc-opt = "bch8";
505 ti,elm-id = <&elm>;
506 nand-bus-width = <16>;
507 gpmc,device-width = <2>;
508 gpmc,sync-clk-ps = <0>;
509 gpmc,cs-on-ns = <0>;
510 gpmc,cs-rd-off-ns = <80>;
511 gpmc,cs-wr-off-ns = <80>;
512 gpmc,adv-on-ns = <0>;
513 gpmc,adv-rd-off-ns = <60>;
514 gpmc,adv-wr-off-ns = <60>;
515 gpmc,we-on-ns = <10>;
516 gpmc,we-off-ns = <50>;
517 gpmc,oe-on-ns = <4>;
518 gpmc,oe-off-ns = <40>;
519 gpmc,access-ns = <40>;
520 gpmc,wr-access-ns = <80>;
521 gpmc,rd-cycle-ns = <80>;
522 gpmc,wr-cycle-ns = <80>;
523 gpmc,bus-turnaround-ns = <0>;
524 gpmc,cycle2cycle-delay-ns = <0>;
525 gpmc,clk-activation-ns = <0>;
526 gpmc,wait-monitoring-ns = <0>;
527 gpmc,wr-data-mux-bus-ns = <0>;
528 /* MTD partition table */
529 /* All SPL-* partitions are sized to minimal length
530 * which can be independently programmable. For
531 * NAND flash this is equal to size of erase-block */
532 #address-cells = <1>;
533 #size-cells = <1>;
534 partition@0 {
535 label = "NAND.SPL";
536 reg = <0x00000000 0x000020000>;
537 };
538 partition@1 {
539 label = "NAND.SPL.backup1";
540 reg = <0x00020000 0x00020000>;
541 };
542 partition@2 {
543 label = "NAND.SPL.backup2";
544 reg = <0x00040000 0x00020000>;
545 };
546 partition@3 {
547 label = "NAND.SPL.backup3";
548 reg = <0x00060000 0x00020000>;
549 };
550 partition@4 {
551 label = "NAND.u-boot-spl-os";
552 reg = <0x00080000 0x00040000>;
553 };
554 partition@5 {
555 label = "NAND.u-boot";
556 reg = <0x000c0000 0x00100000>;
557 };
558 partition@6 {
559 label = "NAND.u-boot-env";
560 reg = <0x001c0000 0x00020000>;
561 };
562 partition@7 {
563 label = "NAND.u-boot-env.backup1";
564 reg = <0x001e0000 0x00020000>;
565 };
566 partition@8 {
567 label = "NAND.kernel";
568 reg = <0x00200000 0x00800000>;
569 };
570 partition@9 {
571 label = "NAND.file-system";
572 reg = <0x00a00000 0x0f600000>;
573 };
574 };
575};
95cc6af8 576
7a15c8e7
RQ		 577&usb2_phy1 {
578 phy-supply = <&ldo4_reg>;
579};
580
581&usb2_phy2 {
582 phy-supply = <&ldo4_reg>;
583};
584
a7b0aa19
RQ		 585&omap_dwc3_1 {
586 extcon = <&extcon_usb1>;
587};
588
589&omap_dwc3_2 {
590 extcon = <&extcon_usb2>;
591};
592
95cc6af8
GC		 593&usb1 {
594 dr_mode = "peripheral";
595 pinctrl-names = "default";
596 pinctrl-0 = <&usb1_pins>;
597};
598
599&usb2 {
600 dr_mode = "host";
601 pinctrl-names = "default";
602 pinctrl-0 = <&usb2_pins>;
603};
5b434d7e
NM		 604
605&mmc1 {
606 status = "okay";
607 pinctrl-names = "default";
608 pinctrl-0 = <&mmc1_pins_default>;
a238707d
KVA		 609 vmmc-supply = <&evm_3v3_sd>;
610 vmmc_aux-supply = <&ldo1_reg>;
5b434d7e
NM		 611 bus-width = <4>;
612 /*
613 * SDCD signal is not being used here - using the fact that GPIO mode
614 * is a viable alternative
615 */
616 cd-gpios = <&gpio6 27 0>;
e23b27db 617 max-frequency = <192000000>;
5b434d7e
NM		 618};
619
620&mmc2 {
621 /* SW5-3 in ON position */
622 status = "okay";
623 pinctrl-names = "default";
624 pinctrl-0 = <&mmc2_pins_default>;
625
626 vmmc-supply = <&evm_3v3>;
627 bus-width = <8>;
628 ti,non-removable;
e23b27db 629 max-frequency = <192000000>;
5b434d7e 630};
d5475152
M		 631
632&dra7_pmx_core {
633 cpsw_default: cpsw_default {
634 pinctrl-single,pins = <
635 /* Slave 2 */
636 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
637 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
638 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
639 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
640 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
641 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
642 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
643 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
644 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
645 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
646 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
647 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
648 >;
649
650 };
651
652 cpsw_sleep: cpsw_sleep {
653 pinctrl-single,pins = <
654 /* Slave 2 */
655 0x198 (MUX_MODE15)
656 0x19c (MUX_MODE15)
657 0x1a0 (MUX_MODE15)
658 0x1a4 (MUX_MODE15)
659 0x1a8 (MUX_MODE15)
660 0x1ac (MUX_MODE15)
661 0x1b0 (MUX_MODE15)
662 0x1b4 (MUX_MODE15)
663 0x1b8 (MUX_MODE15)
664 0x1bc (MUX_MODE15)
665 0x1c0 (MUX_MODE15)
666 0x1c4 (MUX_MODE15)
667 >;
668 };
669
670 davinci_mdio_default: davinci_mdio_default {
671 pinctrl-single,pins = <
672 /* MDIO */
673 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
674 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
675 >;
676 };
677
678 davinci_mdio_sleep: davinci_mdio_sleep {
679 pinctrl-single,pins = <
680 0x23c (MUX_MODE15)
681 0x240 (MUX_MODE15)
682 >;
683 };
684};
685
686&mac {
687 status = "okay";
688 pinctrl-names = "default", "sleep";
689 pinctrl-0 = <&cpsw_default>;
690 pinctrl-1 = <&cpsw_sleep>;
ad548430 691 slaves = <1>;
d5475152
M		 692};
693
ad548430 694&cpsw_emac0 {
d5475152
M		 695 phy_id = <&davinci_mdio>, <3>;
696 phy-mode = "rgmii";
697};
698
699&davinci_mdio {
700 pinctrl-names = "default", "sleep";
701 pinctrl-0 = <&davinci_mdio_default>;
702 pinctrl-1 = <&davinci_mdio_sleep>;
d5475152 703};
ea95af3c
RQ		 704
705&dcan1 {
706 status = "ok";
2acb5c30
RQ		 707 pinctrl-names = "default", "sleep", "active";
708 pinctrl-0 = <&dcan1_pins_sleep>;
ea95af3c 709 pinctrl-1 = <&dcan1_pins_sleep>;
2acb5c30 710 pinctrl-2 = <&dcan1_pins_default>;
ea95af3c 711};
1f43c45d
M		 712
713&qspi {
714 status = "okay";
715 pinctrl-names = "default";
716 pinctrl-0 = <&qspi1_pins>;
717
718 spi-max-frequency = <48000000>;
719 m25p80@0 {
720 compatible = "s25fl256s1";
721 spi-max-frequency = <48000000>;
722 reg = <0>;
723 spi-tx-bus-width = <1>;
724 spi-rx-bus-width = <4>;
725 spi-cpol;
726 spi-cpha;
727 #address-cells = <1>;
728 #size-cells = <1>;
729
730 /* MTD partition table.
731 * The ROM checks the first four physical blocks
732 * for a valid file to boot and the flash here is
733 * 64KiB block size.
734 */
735 partition@0 {
736 label = "QSPI.SPL";
737 reg = <0x00000000 0x000010000>;
738 };
739 partition@1 {
740 label = "QSPI.SPL.backup1";
741 reg = <0x00010000 0x00010000>;
742 };
743 partition@2 {
744 label = "QSPI.SPL.backup2";
745 reg = <0x00020000 0x00010000>;
746 };
747 partition@3 {
748 label = "QSPI.SPL.backup3";
749 reg = <0x00030000 0x00010000>;
750 };
751 partition@4 {
752 label = "QSPI.u-boot";
753 reg = <0x00040000 0x00100000>;
754 };
755 partition@5 {
756 label = "QSPI.u-boot-spl-os";
757 reg = <0x00140000 0x00080000>;
758 };
759 partition@6 {
760 label = "QSPI.u-boot-env";
761 reg = <0x001c0000 0x00010000>;
762 };
763 partition@7 {
764 label = "QSPI.u-boot-env.backup1";
765 reg = <0x001d0000 0x0010000>;
766 };
767 partition@8 {
768 label = "QSPI.kernel";
769 reg = <0x001e0000 0x0800000>;
770 };
771 partition@9 {
772 label = "QSPI.file-system";
773 reg = <0x009e0000 0x01620000>;
774 };
775 };
776};
fadf0d0b
TV		 777
778&dss {
779 status = "ok";
780
781 vdda_video-supply = <&ldo5_reg>;
782};
783
784&hdmi {
785 status = "ok";
786 vdda-supply = <&ldo3_reg>;
787
788 pinctrl-names = "default";
789 pinctrl-0 = <&hdmi_pins>;
790
791 port {
792 hdmi_out: endpoint {
793 remote-endpoint = <&tpd12s015_in>;
794 };
795 };
796};
a8d3b59c
PU		 797
798&atl {
799 pinctrl-names = "default";
800 pinctrl-0 = <&atl_pins>;
801
802 assigned-clocks = <&abe_dpll_sys_clk_mux>,
803 <&atl_gfclk_mux>,
804 <&dpll_abe_ck>,
805 <&dpll_abe_m2x2_ck>,
806 <&atl_clkin2_ck>;
807 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
808 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
809
810 status = "okay";
811
812 atl2 {
813 bws = <DRA7_ATL_WS_MCASP2_FSX>;
814 aws = <DRA7_ATL_WS_MCASP3_FSX>;
815 };
816};
817
818&mcasp3 {
819 #sound-dai-cells = <0>;
820 pinctrl-names = "default", "sleep";
821 pinctrl-0 = <&mcasp3_pins>;
822 pinctrl-1 = <&mcasp3_sleep_pins>;
823
824 assigned-clocks = <&mcasp3_ahclkx_mux>;
825 assigned-clock-parents = <&atl_clkin2_ck>;
826
827 status = "okay";
828
829 op-mode = <0>; /* MCASP_IIS_MODE */
830 tdm-slots = <2>;
831 /* 4 serializer */
832 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
833 1 2 0 0
834 >;
835};
Linux kernel - Deliverables
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