[deliverable/linux.git] / arch / arm / boot / dts / dra72-evm.dts

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"

/ {
	model = "TI DRA722";
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>; /* 1024 MB */
	};
};

&dra7_pmx_core {
	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
		>;
	};

	nand_default: nand_default {
		pinctrl-single,pins = <
			0x0	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
			0x4	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
			0x8	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
			0xc	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
			0x10	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
			0x14	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
			0x18	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
			0x1c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
			0x20	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
			0x24	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
			0x28	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
			0x2c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
			0x30	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
			0x34	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
			0x38	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
			0x3c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
			0xb4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
			0xc4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
			0xcc	(PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
			0xc8	(PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
			0xd0	(PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
			0xd8	(PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
		>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
		>;
	};

	usb2_pins: pinmux_usb2_pins {
		pinctrl-single,pins = <
			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
		>;
	};

	tps65917_pins_default: tps65917_pins_default {
		pinctrl-single,pins = <
			0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
		>;
	};
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <400000>;

	tps65917: tps65917@58 {
		compatible = "ti,tps65917";
		reg = <0x58>;

		pinctrl-names = "default";
		pinctrl-0 = <&tps65917_pins_default>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
		interrupt-parent = <&gic>;
		interrupt-controller;
		#interrupt-cells = <2>;

		ti,system-power-controller;

		tps65917_pmic {
			compatible = "ti,tps65917-pmic";

			regulators {
				smps1_reg: smps1 {
					/* VDD_MPU */
					regulator-name = "smps1";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps2_reg: smps2 {
					/* VDD_CORE */
					regulator-name = "smps2";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1030000>;
					regulator-boot-on;
					regulator-always-on;
				};

				smps3_reg: smps3 {
					/* VDD_GPU IVA DSPEVE */
					regulator-name = "smps3";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-boot-on;
					regulator-always-on;
				};

				smps4_reg: smps4 {
					/* VDDS1V8 */
					regulator-name = "smps4";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps5_reg: smps5 {
					/* VDD_DDR */
					regulator-name = "smps5";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo1_reg: ldo1 {
					/* LDO1_OUT --> SDIO  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				ldo2_reg: ldo2 {
					/* LDO2_OUT --> TP1017 (UNUSED)  */
					regulator-name = "ldo2";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHY */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo5_reg: ldo5 {
					/* VDDA_1V8_PLL */
					regulator-name = "ldo5";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo4_reg: ldo4 {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldo4";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};
			};
		};
	};
};

&uart1 {
	status = "okay";
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_default>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		reg = <0 0 4>;		/* device IO registers */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&usb2_phy1 {
	phy-supply = <&ldo4_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldo4_reg>;
};

&usb1 {
	dr_mode = "peripheral";
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
};

&usb2 {
	dr_mode = "host";
	pinctrl-names = "default";
	pinctrl-0 = <&usb2_pins>;
};
Commit	Line	Data
38b248db RN	1	/*
	2	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	/dts-v1/;
	9
	10	#include "dra72x.dtsi"
	11
	12	/ {
	13	model = "TI DRA722";
	14	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
	15
	16	memory {
	17	device_type = "memory";
	18	reg = <0x80000000 0x40000000>; /* 1024 MB */
	19	};
	20	};
	21
7e9711aa K	22	&dra7_pmx_core {
	23	i2c1_pins: pinmux_i2c1_pins {
	24	pinctrl-single,pins = <
	25	0x400 (PIN_INPUT \| MUX_MODE0) /* i2c1_sda.i2c1_sda */
	26	0x404 (PIN_INPUT \| MUX_MODE0) /* i2c1_scl.i2c1_scl */
	27	>;
	28	};
09d4993c RQ	29
	30	nand_default: nand_default {
	31	pinctrl-single,pins = <
	32	0x0 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad0 */
	33	0x4 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad1 */
	34	0x8 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad2 */
	35	0xc (PIN_INPUT \| MUX_MODE0) /* gpmc_ad3 */
	36	0x10 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad4 */
	37	0x14 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad5 */
	38	0x18 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad6 */
	39	0x1c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad7 */
	40	0x20 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad8 */
	41	0x24 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad9 */
	42	0x28 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad10 */
	43	0x2c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad11 */
	44	0x30 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad12 */
	45	0x34 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad13 */
	46	0x38 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad14 */
	47	0x3c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad15 */
	48	0xb4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_cs0 */
	49	0xc4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale */
	50	0xcc (PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen */
	51	0xc8 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren */
	52	0xd0 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_ben0 */
	53	0xd8 (PIN_INPUT \| MUX_MODE0) /* gpmc_wait0 */
	54	>;
	55	};
95cc6af8 GC	56
	57	usb1_pins: pinmux_usb1_pins {
	58	pinctrl-single,pins = <
	59	0x280 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb1_drvvbus */
	60	>;
	61	};
	62
	63	usb2_pins: pinmux_usb2_pins {
	64	pinctrl-single,pins = <
	65	0x284 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb2_drvvbus */
	66	>;
	67	};
829acd07 NM	68
	69	tps65917_pins_default: tps65917_pins_default {
	70	pinctrl-single,pins = <
	71	0x424 (PIN_INPUT_PULLUP \| MUX_MODE1) /* wakeup3.sys_nirq1 */
	72	>;
	73	};
7e9711aa K	74	};
	75
	76	&i2c1 {
	77	status = "okay";
	78	pinctrl-names = "default";
	79	pinctrl-0 = <&i2c1_pins>;
	80	clock-frequency = <400000>;
b359c426 K	81
	82	tps65917: tps65917@58 {
	83	compatible = "ti,tps65917";
	84	reg = <0x58>;
	85
829acd07 NM	86	pinctrl-names = "default";
	87	pinctrl-0 = <&tps65917_pins_default>;
	88
b359c426 K	89	interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
	90	interrupt-parent = <&gic>;
	91	interrupt-controller;
	92	#interrupt-cells = <2>;
	93
	94	ti,system-power-controller;
	95
	96	tps65917_pmic {
	97	compatible = "ti,tps65917-pmic";
	98
	99	regulators {
	100	smps1_reg: smps1 {
	101	/* VDD_MPU */
	102	regulator-name = "smps1";
	103	regulator-min-microvolt = <850000>;
	104	regulator-max-microvolt = <1250000>;
	105	regulator-always-on;
	106	regulator-boot-on;
	107	};
	108
	109	smps2_reg: smps2 {
	110	/* VDD_CORE */
	111	regulator-name = "smps2";
	112	regulator-min-microvolt = <850000>;
	113	regulator-max-microvolt = <1030000>;
	114	regulator-boot-on;
	115	regulator-always-on;
	116	};
	117
	118	smps3_reg: smps3 {
	119	/* VDD_GPU IVA DSPEVE */
	120	regulator-name = "smps3";
	121	regulator-min-microvolt = <850000>;
	122	regulator-max-microvolt = <1250000>;
	123	regulator-boot-on;
	124	regulator-always-on;
	125	};
	126
	127	smps4_reg: smps4 {
	128	/* VDDS1V8 */
	129	regulator-name = "smps4";
	130	regulator-min-microvolt = <1800000>;
	131	regulator-max-microvolt = <1800000>;
	132	regulator-always-on;
	133	regulator-boot-on;
	134	};
	135
	136	smps5_reg: smps5 {
	137	/* VDD_DDR */
	138	regulator-name = "smps5";
	139	regulator-min-microvolt = <1350000>;
	140	regulator-max-microvolt = <1350000>;
	141	regulator-boot-on;
	142	regulator-always-on;
	143	};
	144
	145	ldo1_reg: ldo1 {
	146	/* LDO1_OUT --> SDIO */
	147	regulator-name = "ldo1";
	148	regulator-min-microvolt = <1800000>;
	149	regulator-max-microvolt = <3300000>;
	150	regulator-boot-on;
	151	};
	152
153	ldo2_reg: ldo2 {
154	/* LDO2_OUT --> TP1017 (UNUSED) */
155	regulator-name = "ldo2";
156	regulator-min-microvolt = <1800000>;
157	regulator-max-microvolt = <3300000>;
158	};
159
160	ldo3_reg: ldo3 {
161	/* VDDA_1V8_PHY */
162	regulator-name = "ldo3";
163	regulator-min-microvolt = <1800000>;
164	regulator-max-microvolt = <1800000>;
165	regulator-boot-on;
166	regulator-always-on;
167	};
168
169	ldo5_reg: ldo5 {
170	/* VDDA_1V8_PLL */
171	regulator-name = "ldo5";
172	regulator-min-microvolt = <1800000>;
173	regulator-max-microvolt = <1800000>;
174	regulator-always-on;
175	regulator-boot-on;
176	};
177
178	ldo4_reg: ldo4 {
179	/* VDDA_3V_USB: VDDA_USBHS33 */
180	regulator-name = "ldo4";
181	regulator-min-microvolt = <3300000>;
182	regulator-max-microvolt = <3300000>;
183	regulator-boot-on;
184	};
185	};
186	};
187	};
7e9711aa K	188	};
7e9711aa K	189
38b248db RN	190	&uart1 {
	191	status = "okay";
	192	};
09d4993c RQ	193
	194	&elm {
	195	status = "okay";
	196	};
	197
	198	&gpmc {
	199	status = "okay";
	200	pinctrl-names = "default";
	201	pinctrl-0 = <&nand_default>;
	202	ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
	203	nand@0,0 {
	204	/* To use NAND, DIP switch SW5 must be set like so:
	205	* SW5.1 (NAND_SELn) = ON (LOW)
	206	* SW5.9 (GPMC_WPN) = OFF (HIGH)
	207	*/
	208	reg = <0 0 4>; /* device IO registers */
	209	ti,nand-ecc-opt = "bch8";
	210	ti,elm-id = <&elm>;
	211	nand-bus-width = <16>;
	212	gpmc,device-width = <2>;
	213	gpmc,sync-clk-ps = <0>;
	214	gpmc,cs-on-ns = <0>;
	215	gpmc,cs-rd-off-ns = <80>;
	216	gpmc,cs-wr-off-ns = <80>;
	217	gpmc,adv-on-ns = <0>;
	218	gpmc,adv-rd-off-ns = <60>;
	219	gpmc,adv-wr-off-ns = <60>;
	220	gpmc,we-on-ns = <10>;
	221	gpmc,we-off-ns = <50>;
	222	gpmc,oe-on-ns = <4>;
	223	gpmc,oe-off-ns = <40>;
	224	gpmc,access-ns = <40>;
	225	gpmc,wr-access-ns = <80>;
	226	gpmc,rd-cycle-ns = <80>;
	227	gpmc,wr-cycle-ns = <80>;
	228	gpmc,bus-turnaround-ns = <0>;
	229	gpmc,cycle2cycle-delay-ns = <0>;
	230	gpmc,clk-activation-ns = <0>;
	231	gpmc,wait-monitoring-ns = <0>;
	232	gpmc,wr-data-mux-bus-ns = <0>;
	233	/* MTD partition table */
	234	/* All SPL-* partitions are sized to minimal length
	235	* which can be independently programmable. For
	236	* NAND flash this is equal to size of erase-block */
	237	#address-cells = <1>;
	238	#size-cells = <1>;
	239	partition@0 {
	240	label = "NAND.SPL";
	241	reg = <0x00000000 0x000020000>;
	242	};
	243	partition@1 {
	244	label = "NAND.SPL.backup1";
	245	reg = <0x00020000 0x00020000>;
	246	};
	247	partition@2 {
	248	label = "NAND.SPL.backup2";
	249	reg = <0x00040000 0x00020000>;
	250	};
	251	partition@3 {
	252	label = "NAND.SPL.backup3";
	253	reg = <0x00060000 0x00020000>;
	254	};
	255	partition@4 {
	256	label = "NAND.u-boot-spl-os";
257	reg = <0x00080000 0x00040000>;
258	};
259	partition@5 {
260	label = "NAND.u-boot";
261	reg = <0x000c0000 0x00100000>;
262	};
263	partition@6 {
264	label = "NAND.u-boot-env";
265	reg = <0x001c0000 0x00020000>;
266	};
267	partition@7 {
268	label = "NAND.u-boot-env.backup1";
269	reg = <0x001e0000 0x00020000>;
270	};
271	partition@8 {
272	label = "NAND.kernel";
273	reg = <0x00200000 0x00800000>;
274	};
275	partition@9 {
276	label = "NAND.file-system";
277	reg = <0x00a00000 0x0f600000>;
278	};
279	};
280	};
95cc6af8	281
7a15c8e7 RQ	282	&usb2_phy1 {
	283	phy-supply = <&ldo4_reg>;
	284	};
	285
	286	&usb2_phy2 {
	287	phy-supply = <&ldo4_reg>;
	288	};
	289
95cc6af8 GC	290	&usb1 {
	291	dr_mode = "peripheral";
	292	pinctrl-names = "default";
	293	pinctrl-0 = <&usb1_pins>;
	294	};
	295
	296	&usb2 {
	297	dr_mode = "host";
	298	pinctrl-names = "default";
	299	pinctrl-0 = <&usb2_pins>;
	300	};