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38b248db RN |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | #include "dra7.dtsi" | |
11 | ||
12 | / { | |
13 | compatible = "ti,dra742", "ti,dra74", "ti,dra7"; | |
14 | ||
15 | cpus { | |
38b248db RN |
16 | cpu@1 { |
17 | device_type = "cpu"; | |
18 | compatible = "arm,cortex-a15"; | |
19 | reg = <1>; | |
f80bc97f | 20 | operating-points-v2 = <&cpu0_opp_table>; |
38b248db RN |
21 | }; |
22 | }; | |
f53e3c53 LW |
23 | |
24 | pmu { | |
25 | compatible = "arm,cortex-a15-pmu"; | |
7136d457 | 26 | interrupt-parent = <&wakeupgen>; |
783d3186 MZ |
27 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
28 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
f53e3c53 | 29 | }; |
6b14eb47 RQ |
30 | |
31 | ocp { | |
bddbe6db SA |
32 | dsp2_system: dsp_system@41500000 { |
33 | compatible = "syscon"; | |
34 | reg = <0x41500000 0x100>; | |
35 | }; | |
36 | ||
4f6dec70 | 37 | omap_dwc3_4: omap_dwc3_4@48940000 { |
6b14eb47 RQ |
38 | compatible = "ti,dwc3"; |
39 | ti,hwmods = "usb_otg_ss4"; | |
40 | reg = <0x48940000 0x10000>; | |
41 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | |
42 | #address-cells = <1>; | |
43 | #size-cells = <1>; | |
44 | utmi-mode = <2>; | |
45 | ranges; | |
46 | status = "disabled"; | |
47 | usb4: usb@48950000 { | |
48 | compatible = "snps,dwc3"; | |
49 | reg = <0x48950000 0x17000>; | |
964927f3 RQ |
50 | interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
51 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
52 | <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | |
53 | interrupt-names = "peripheral", | |
54 | "host", | |
55 | "otg"; | |
6b14eb47 RQ |
56 | maximum-speed = "high-speed"; |
57 | dr_mode = "otg"; | |
58 | }; | |
59 | }; | |
63c7ecd7 SA |
60 | |
61 | mmu0_dsp2: mmu@41501000 { | |
62 | compatible = "ti,dra7-dsp-iommu"; | |
63 | reg = <0x41501000 0x100>; | |
64 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
65 | ti,hwmods = "mmu0_dsp2"; | |
66 | #iommu-cells = <0>; | |
67 | ti,syscon-mmuconfig = <&dsp2_system 0x0>; | |
68 | status = "disabled"; | |
69 | }; | |
70 | ||
71 | mmu1_dsp2: mmu@41502000 { | |
72 | compatible = "ti,dra7-dsp-iommu"; | |
73 | reg = <0x41502000 0x100>; | |
74 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
75 | ti,hwmods = "mmu1_dsp2"; | |
76 | #iommu-cells = <0>; | |
77 | ti,syscon-mmuconfig = <&dsp2_system 0x1>; | |
78 | status = "disabled"; | |
79 | }; | |
6b14eb47 | 80 | }; |
38b248db | 81 | }; |
95c1cd13 TV |
82 | |
83 | &dss { | |
84 | reg = <0x58000000 0x80>, | |
85 | <0x58004054 0x4>, | |
86 | <0x58004300 0x20>, | |
4c88c1c7 TV |
87 | <0x58009054 0x4>, |
88 | <0x58009300 0x20>; | |
95c1cd13 TV |
89 | reg-names = "dss", "pll1_clkctrl", "pll1", |
90 | "pll2_clkctrl", "pll2"; | |
91 | ||
92 | clocks = <&dss_dss_clk>, | |
93 | <&dss_video1_clk>, | |
94 | <&dss_video2_clk>; | |
95 | clock-names = "fck", "video1_clk", "video2_clk"; | |
96 | }; | |
a9c8f117 SA |
97 | |
98 | &mailbox5 { | |
99 | mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { | |
100 | ti,mbox-tx = <6 2 2>; | |
101 | ti,mbox-rx = <4 2 2>; | |
102 | status = "disabled"; | |
103 | }; | |
104 | mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { | |
105 | ti,mbox-tx = <5 2 2>; | |
106 | ti,mbox-rx = <1 2 2>; | |
107 | status = "disabled"; | |
108 | }; | |
109 | }; | |
110 | ||
111 | &mailbox6 { | |
112 | mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { | |
113 | ti,mbox-tx = <6 2 2>; | |
114 | ti,mbox-rx = <4 2 2>; | |
115 | status = "disabled"; | |
116 | }; | |
117 | mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { | |
118 | ti,mbox-tx = <5 2 2>; | |
119 | ti,mbox-rx = <1 2 2>; | |
120 | status = "disabled"; | |
121 | }; | |
122 | }; |