[deliverable/linux.git] / arch / arm / boot / dts / emev2.dtsi

/*
 * Device Tree Source for the EMEV2 SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,emev2";
	interrupt-parent = <&gic>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		i2c0 = &iic0;
		i2c1 = &iic1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <533000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <533000000>;
		};
	};

	gic: interrupt-controller@e0020000 {
		compatible = "arm,pl390";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0xe0028000 0x1000>,
		      <0xe0020000 0x0100>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks@e0110000 {
		compatible = "renesas,emev2-smu";
		reg = <0xe0110000 0x10000>;
		#address-cells = <2>;
		#size-cells = <0>;

		c32ki: c32ki {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};
		iic0_sclkdiv: iic0_sclkdiv@624,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x624 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		iic0_sclk: iic0_sclk@48c,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x48c 1>;
			clocks = <&iic0_sclkdiv>;
			#clock-cells = <0>;
		};
		iic1_sclkdiv: iic1_sclkdiv@624,16 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x624 16>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		iic1_sclk: iic1_sclk@490,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x490 1>;
			clocks = <&iic1_sclkdiv>;
			#clock-cells = <0>;
		};
		pll3_fo: pll3_fo {
			compatible = "fixed-factor-clock";
			clocks = <&c32ki>;
			clock-div = <1>;
			clock-mult = <7000>;
			#clock-cells = <0>;
		};
		usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x610 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x65c 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x65c 16>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x660 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usia_u0_sclk: usia_u0_sclk@4a0,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4a0 1>;
			clocks = <&usia_u0_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u1_sclk: usib_u1_sclk@4b8,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4b8 1>;
			clocks = <&usib_u1_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u2_sclk: usib_u2_sclk@4bc,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4bc 1>;
			clocks = <&usib_u2_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u3_sclk: usib_u3_sclk@4c0,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4c0 1>;
			clocks = <&usib_u3_sclkdiv>;
			#clock-cells = <0>;
		};
		sti_sclk: sti_sclk@528,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x528 1>;
			clocks = <&c32ki>;
			#clock-cells = <0>;
		};
	};

	timer@e0180000 {
		compatible = "renesas,em-sti";
		reg = <0xe0180000 0x54>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sti_sclk>;
		clock-names = "sclk";
	};

	uart0: serial@e1020000 {
		compatible = "renesas,em-uart";
		reg = <0xe1020000 0x38>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usia_u0_sclk>;
		clock-names = "sclk";
	};

	uart1: serial@e1030000 {
		compatible = "renesas,em-uart";
		reg = <0xe1030000 0x38>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u1_sclk>;
		clock-names = "sclk";
	};

	uart2: serial@e1040000 {
		compatible = "renesas,em-uart";
		reg = <0xe1040000 0x38>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u2_sclk>;
		clock-names = "sclk";
	};

	uart3: serial@e1050000 {
		compatible = "renesas,em-uart";
		reg = <0xe1050000 0x38>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u3_sclk>;
		clock-names = "sclk";
	};

	pfc: pfc@e0140200 {
		compatible = "renesas,pfc-emev2";
		reg = <0xe0140200 0x100>;
	};

	gpio0: gpio@e0050000 {
		compatible = "renesas,em-gio";
		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
	gpio1: gpio@e0050080 {
		compatible = "renesas,em-gio";
		reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
	gpio2: gpio@e0050100 {
		compatible = "renesas,em-gio";
		reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
	gpio3: gpio@e0050180 {
		compatible = "renesas,em-gio";
		reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
	gpio4: gpio@e0050200 {
		compatible = "renesas,em-gio";
		reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 31>;
		#gpio-cells = <2>;
		ngpios = <31>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	iic0: i2c@e0070000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-emev2";
		reg = <0xe0070000 0x28>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
		clocks = <&iic0_sclk>;
		clock-names = "sclk";
		status = "disabled";
	};

	iic1: i2c@e10a0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-emev2";
		reg = <0xe10a0000 0x28>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
		clocks = <&iic1_sclk>;
		clock-names = "sclk";
		status = "disabled";
	};
};
Commit	Line	Data
3d5de271 MD	1	/*
	2	* Device Tree Source for the EMEV2 SoC
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
cef20af0	11	#include "skeleton.dtsi"
b14ce232	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
3dc76086	13	#include <dt-bindings/interrupt-controller/irq.h>
3d5de271 MD	14
	15	/ {
	16	compatible = "renesas,emev2";
	17	interrupt-parent = <&gic>;
	18
12d035b1 MD	19	aliases {
	20	gpio0 = &gpio0;
	21	gpio1 = &gpio1;
	22	gpio2 = &gpio2;
	23	gpio3 = &gpio3;
	24	gpio4 = &gpio4;
cd42d042 WS	25	i2c0 = &iic0;
cd42d042 WS	26	i2c1 = &iic1;
12d035b1 MD	27	};
12d035b1 MD	28
3d5de271	29	cpus {
fe681d29 SH	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
3d5de271	33	cpu@0 {
fe681d29	34	device_type = "cpu";
3d5de271	35	compatible = "arm,cortex-a9";
fe681d29	36	reg = <0>;
11f1ca10	37	clock-frequency = <533000000>;
3d5de271 MD	38	};
3d5de271 MD	39	cpu@1 {
fe681d29	40	device_type = "cpu";
3d5de271	41	compatible = "arm,cortex-a9";
fe681d29	42	reg = <1>;
11f1ca10	43	clock-frequency = <533000000>;
3d5de271 MD	44	};
	45	};
	46
	47	gic: interrupt-controller@e0020000 {
c8a5880a	48	compatible = "arm,pl390";
3d5de271 MD	49	interrupt-controller;
	50	#interrupt-cells = <3>;
	51	reg = <0xe0028000 0x1000>,
	52	<0xe0020000 0x0100>;
	53	};
	54
c95ebbb2 MD	55	pmu {
c95ebbb2 MD	56	compatible = "arm,cortex-a9-pmu";
b14ce232 SH	57	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	58	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
c95ebbb2 MD	59	};
c95ebbb2 MD	60
87982b2d	61	clocks@e0110000 {
fdf6fd22 TY	62	compatible = "renesas,emev2-smu";
	63	reg = <0xe0110000 0x10000>;
	64	#address-cells = <2>;
	65	#size-cells = <0>;
	66
	67	c32ki: c32ki {
	68	compatible = "fixed-clock";
	69	clock-frequency = <32768>;
	70	#clock-cells = <0>;
	71	};
33df2753	72	iic0_sclkdiv: iic0_sclkdiv@624,0 {
cd42d042 WS	73	compatible = "renesas,emev2-smu-clkdiv";
	74	reg = <0x624 0>;
	75	clocks = <&pll3_fo>;
	76	#clock-cells = <0>;
	77	};
33df2753	78	iic0_sclk: iic0_sclk@48c,1 {
cd42d042 WS	79	compatible = "renesas,emev2-smu-gclk";
	80	reg = <0x48c 1>;
	81	clocks = <&iic0_sclkdiv>;
	82	#clock-cells = <0>;
	83	};
33df2753	84	iic1_sclkdiv: iic1_sclkdiv@624,16 {
cd42d042 WS	85	compatible = "renesas,emev2-smu-clkdiv";
	86	reg = <0x624 16>;
	87	clocks = <&pll3_fo>;
	88	#clock-cells = <0>;
	89	};
33df2753	90	iic1_sclk: iic1_sclk@490,1 {
cd42d042 WS	91	compatible = "renesas,emev2-smu-gclk";
	92	reg = <0x490 1>;
	93	clocks = <&iic1_sclkdiv>;
	94	#clock-cells = <0>;
	95	};
fdf6fd22 TY	96	pll3_fo: pll3_fo {
	97	compatible = "fixed-factor-clock";
	98	clocks = <&c32ki>;
	99	clock-div = <1>;
	100	clock-mult = <7000>;
	101	#clock-cells = <0>;
	102	};
33df2753	103	usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
fdf6fd22 TY	104	compatible = "renesas,emev2-smu-clkdiv";
	105	reg = <0x610 0>;
	106	clocks = <&pll3_fo>;
	107	#clock-cells = <0>;
	108	};
33df2753	109	usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
fdf6fd22 TY	110	compatible = "renesas,emev2-smu-clkdiv";
	111	reg = <0x65c 0>;
	112	clocks = <&pll3_fo>;
	113	#clock-cells = <0>;
	114	};
33df2753	115	usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
fdf6fd22 TY	116	compatible = "renesas,emev2-smu-clkdiv";
	117	reg = <0x65c 16>;
	118	clocks = <&pll3_fo>;
	119	#clock-cells = <0>;
	120	};
33df2753	121	usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
fdf6fd22 TY	122	compatible = "renesas,emev2-smu-clkdiv";
	123	reg = <0x660 0>;
	124	clocks = <&pll3_fo>;
	125	#clock-cells = <0>;
	126	};
33df2753	127	usia_u0_sclk: usia_u0_sclk@4a0,1 {
fdf6fd22 TY	128	compatible = "renesas,emev2-smu-gclk";
	129	reg = <0x4a0 1>;
	130	clocks = <&usia_u0_sclkdiv>;
	131	#clock-cells = <0>;
	132	};
33df2753	133	usib_u1_sclk: usib_u1_sclk@4b8,1 {
fdf6fd22 TY	134	compatible = "renesas,emev2-smu-gclk";
	135	reg = <0x4b8 1>;
	136	clocks = <&usib_u1_sclkdiv>;
	137	#clock-cells = <0>;
	138	};
33df2753	139	usib_u2_sclk: usib_u2_sclk@4bc,1 {
fdf6fd22 TY	140	compatible = "renesas,emev2-smu-gclk";
	141	reg = <0x4bc 1>;
	142	clocks = <&usib_u2_sclkdiv>;
	143	#clock-cells = <0>;
	144	};
33df2753	145	usib_u3_sclk: usib_u3_sclk@4c0,1 {
fdf6fd22 TY	146	compatible = "renesas,emev2-smu-gclk";
	147	reg = <0x4c0 1>;
	148	clocks = <&usib_u3_sclkdiv>;
	149	#clock-cells = <0>;
	150	};
33df2753	151	sti_sclk: sti_sclk@528,1 {
fdf6fd22 TY	152	compatible = "renesas,emev2-smu-gclk";
	153	reg = <0x528 1>;
	154	clocks = <&c32ki>;
	155	#clock-cells = <0>;
	156	};
	157	};
	158
87982b2d	159	timer@e0180000 {
3d5de271 MD	160	compatible = "renesas,em-sti";
3d5de271 MD	161	reg = <0xe0180000 0x54>;
b14ce232	162	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
fdf6fd22 TY	163	clocks = <&sti_sclk>;
fdf6fd22 TY	164	clock-names = "sclk";
3d5de271 MD	165	};
3d5de271 MD	166
e87aabaf	167	uart0: serial@e1020000 {
3d5de271 MD	168	compatible = "renesas,em-uart";
3d5de271 MD	169	reg = <0xe1020000 0x38>;
b14ce232	170	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
fdf6fd22 TY	171	clocks = <&usia_u0_sclk>;
fdf6fd22 TY	172	clock-names = "sclk";
3d5de271 MD	173	};
3d5de271 MD	174
e87aabaf	175	uart1: serial@e1030000 {
3d5de271 MD	176	compatible = "renesas,em-uart";
3d5de271 MD	177	reg = <0xe1030000 0x38>;
b14ce232	178	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
fdf6fd22 TY	179	clocks = <&usib_u1_sclk>;
fdf6fd22 TY	180	clock-names = "sclk";
3d5de271 MD	181	};
3d5de271 MD	182
e87aabaf	183	uart2: serial@e1040000 {
3d5de271 MD	184	compatible = "renesas,em-uart";
3d5de271 MD	185	reg = <0xe1040000 0x38>;
b14ce232	186	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
fdf6fd22 TY	187	clocks = <&usib_u2_sclk>;
fdf6fd22 TY	188	clock-names = "sclk";
3d5de271 MD	189	};
3d5de271 MD	190
e87aabaf	191	uart3: serial@e1050000 {
3d5de271 MD	192	compatible = "renesas,em-uart";
3d5de271 MD	193	reg = <0xe1050000 0x38>;
b14ce232	194	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
fdf6fd22 TY	195	clocks = <&usib_u3_sclk>;
fdf6fd22 TY	196	clock-names = "sclk";
3d5de271	197	};
12d035b1	198
e7cdf791 NS	199	pfc: pfc@e0140200 {
	200	compatible = "renesas,pfc-emev2";
	201	reg = <0xe0140200 0x100>;
	202	};
	203
12d035b1 MD	204	gpio0: gpio@e0050000 {
	205	compatible = "renesas,em-gio";
	206	reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
b14ce232 SH	207	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	208	<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
12d035b1	209	gpio-controller;
e7cdf791	210	gpio-ranges = <&pfc 0 0 32>;
12d035b1 MD	211	#gpio-cells = <2>;
	212	ngpios = <32>;
	213	interrupt-controller;
	214	#interrupt-cells = <2>;
	215	};
	216	gpio1: gpio@e0050080 {
	217	compatible = "renesas,em-gio";
	218	reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
b14ce232 SH	219	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	220	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
12d035b1	221	gpio-controller;
e7cdf791	222	gpio-ranges = <&pfc 0 32 32>;
12d035b1 MD	223	#gpio-cells = <2>;
	224	ngpios = <32>;
	225	interrupt-controller;
	226	#interrupt-cells = <2>;
	227	};
	228	gpio2: gpio@e0050100 {
	229	compatible = "renesas,em-gio";
	230	reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
b14ce232 SH	231	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	232	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
12d035b1	233	gpio-controller;
e7cdf791	234	gpio-ranges = <&pfc 0 64 32>;
12d035b1 MD	235	#gpio-cells = <2>;
	236	ngpios = <32>;
	237	interrupt-controller;
	238	#interrupt-cells = <2>;
	239	};
	240	gpio3: gpio@e0050180 {
	241	compatible = "renesas,em-gio";
	242	reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
b14ce232 SH	243	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	244	<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
12d035b1	245	gpio-controller;
e7cdf791	246	gpio-ranges = <&pfc 0 96 32>;
12d035b1 MD	247	#gpio-cells = <2>;
	248	ngpios = <32>;
	249	interrupt-controller;
	250	#interrupt-cells = <2>;
	251	};
	252	gpio4: gpio@e0050200 {
	253	compatible = "renesas,em-gio";
	254	reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
b14ce232 SH	255	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
b14ce232 SH	256	<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
12d035b1	257	gpio-controller;
e7cdf791	258	gpio-ranges = <&pfc 0 128 31>;
12d035b1 MD	259	#gpio-cells = <2>;
	260	ngpios = <31>;
	261	interrupt-controller;
	262	#interrupt-cells = <2>;
	263	};
cd42d042 WS	264
	265	iic0: i2c@e0070000 {
	266	#address-cells = <1>;
	267	#size-cells = <0>;
	268	compatible = "renesas,iic-emev2";
	269	reg = <0xe0070000 0x28>;
b14ce232	270	interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
cd42d042 WS	271	clocks = <&iic0_sclk>;
	272	clock-names = "sclk";
	273	status = "disabled";
	274	};
	275
	276	iic1: i2c@e10a0000 {
	277	#address-cells = <1>;
	278	#size-cells = <0>;
	279	compatible = "renesas,iic-emev2";
	280	reg = <0xe10a0000 0x28>;
b14ce232	281	interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
cd42d042 WS	282	clocks = <&iic1_sclk>;
	283	clock-names = "sclk";
	284	status = "disabled";
	285	};
3d5de271	286	};