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3d5de271 MD |
1 | /* |
2 | * Device Tree Source for the EMEV2 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
cef20af0 | 11 | #include "skeleton.dtsi" |
3dc76086 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
3d5de271 MD |
13 | |
14 | / { | |
15 | compatible = "renesas,emev2"; | |
16 | interrupt-parent = <&gic>; | |
17 | ||
12d035b1 MD |
18 | aliases { |
19 | gpio0 = &gpio0; | |
20 | gpio1 = &gpio1; | |
21 | gpio2 = &gpio2; | |
22 | gpio3 = &gpio3; | |
23 | gpio4 = &gpio4; | |
24 | }; | |
25 | ||
3d5de271 | 26 | cpus { |
fe681d29 SH |
27 | #address-cells = <1>; |
28 | #size-cells = <0>; | |
29 | ||
3d5de271 | 30 | cpu@0 { |
fe681d29 | 31 | device_type = "cpu"; |
3d5de271 | 32 | compatible = "arm,cortex-a9"; |
fe681d29 | 33 | reg = <0>; |
3d5de271 MD |
34 | }; |
35 | cpu@1 { | |
fe681d29 | 36 | device_type = "cpu"; |
3d5de271 | 37 | compatible = "arm,cortex-a9"; |
fe681d29 | 38 | reg = <1>; |
3d5de271 MD |
39 | }; |
40 | }; | |
41 | ||
42 | gic: interrupt-controller@e0020000 { | |
43 | compatible = "arm,cortex-a9-gic"; | |
44 | interrupt-controller; | |
45 | #interrupt-cells = <3>; | |
46 | reg = <0xe0028000 0x1000>, | |
47 | <0xe0020000 0x0100>; | |
48 | }; | |
49 | ||
c95ebbb2 MD |
50 | pmu { |
51 | compatible = "arm,cortex-a9-pmu"; | |
3dc76086 LP |
52 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, |
53 | <0 121 IRQ_TYPE_LEVEL_HIGH>; | |
c95ebbb2 MD |
54 | }; |
55 | ||
fdf6fd22 TY |
56 | smu@e0110000 { |
57 | compatible = "renesas,emev2-smu"; | |
58 | reg = <0xe0110000 0x10000>; | |
59 | #address-cells = <2>; | |
60 | #size-cells = <0>; | |
61 | ||
62 | c32ki: c32ki { | |
63 | compatible = "fixed-clock"; | |
64 | clock-frequency = <32768>; | |
65 | #clock-cells = <0>; | |
66 | }; | |
67 | pll3_fo: pll3_fo { | |
68 | compatible = "fixed-factor-clock"; | |
69 | clocks = <&c32ki>; | |
70 | clock-div = <1>; | |
71 | clock-mult = <7000>; | |
72 | #clock-cells = <0>; | |
73 | }; | |
74 | usia_u0_sclkdiv: usia_u0_sclkdiv { | |
75 | compatible = "renesas,emev2-smu-clkdiv"; | |
76 | reg = <0x610 0>; | |
77 | clocks = <&pll3_fo>; | |
78 | #clock-cells = <0>; | |
79 | }; | |
80 | usib_u1_sclkdiv: usib_u1_sclkdiv { | |
81 | compatible = "renesas,emev2-smu-clkdiv"; | |
82 | reg = <0x65c 0>; | |
83 | clocks = <&pll3_fo>; | |
84 | #clock-cells = <0>; | |
85 | }; | |
86 | usib_u2_sclkdiv: usib_u2_sclkdiv { | |
87 | compatible = "renesas,emev2-smu-clkdiv"; | |
88 | reg = <0x65c 16>; | |
89 | clocks = <&pll3_fo>; | |
90 | #clock-cells = <0>; | |
91 | }; | |
92 | usib_u3_sclkdiv: usib_u3_sclkdiv { | |
93 | compatible = "renesas,emev2-smu-clkdiv"; | |
94 | reg = <0x660 0>; | |
95 | clocks = <&pll3_fo>; | |
96 | #clock-cells = <0>; | |
97 | }; | |
98 | usia_u0_sclk: usia_u0_sclk { | |
99 | compatible = "renesas,emev2-smu-gclk"; | |
100 | reg = <0x4a0 1>; | |
101 | clocks = <&usia_u0_sclkdiv>; | |
102 | #clock-cells = <0>; | |
103 | }; | |
104 | usib_u1_sclk: usib_u1_sclk { | |
105 | compatible = "renesas,emev2-smu-gclk"; | |
106 | reg = <0x4b8 1>; | |
107 | clocks = <&usib_u1_sclkdiv>; | |
108 | #clock-cells = <0>; | |
109 | }; | |
110 | usib_u2_sclk: usib_u2_sclk { | |
111 | compatible = "renesas,emev2-smu-gclk"; | |
112 | reg = <0x4bc 1>; | |
113 | clocks = <&usib_u2_sclkdiv>; | |
114 | #clock-cells = <0>; | |
115 | }; | |
116 | usib_u3_sclk: usib_u3_sclk { | |
117 | compatible = "renesas,emev2-smu-gclk"; | |
118 | reg = <0x4c0 1>; | |
119 | clocks = <&usib_u3_sclkdiv>; | |
120 | #clock-cells = <0>; | |
121 | }; | |
122 | sti_sclk: sti_sclk { | |
123 | compatible = "renesas,emev2-smu-gclk"; | |
124 | reg = <0x528 1>; | |
125 | clocks = <&c32ki>; | |
126 | #clock-cells = <0>; | |
127 | }; | |
128 | }; | |
129 | ||
3d5de271 MD |
130 | sti@e0180000 { |
131 | compatible = "renesas,em-sti"; | |
132 | reg = <0xe0180000 0x54>; | |
e05ab0bb | 133 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
134 | clocks = <&sti_sclk>; |
135 | clock-names = "sclk"; | |
3d5de271 MD |
136 | }; |
137 | ||
138 | uart@e1020000 { | |
139 | compatible = "renesas,em-uart"; | |
140 | reg = <0xe1020000 0x38>; | |
e05ab0bb | 141 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
142 | clocks = <&usia_u0_sclk>; |
143 | clock-names = "sclk"; | |
3d5de271 MD |
144 | }; |
145 | ||
146 | uart@e1030000 { | |
147 | compatible = "renesas,em-uart"; | |
148 | reg = <0xe1030000 0x38>; | |
e05ab0bb | 149 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
150 | clocks = <&usib_u1_sclk>; |
151 | clock-names = "sclk"; | |
3d5de271 MD |
152 | }; |
153 | ||
154 | uart@e1040000 { | |
155 | compatible = "renesas,em-uart"; | |
156 | reg = <0xe1040000 0x38>; | |
e05ab0bb | 157 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
158 | clocks = <&usib_u2_sclk>; |
159 | clock-names = "sclk"; | |
3d5de271 MD |
160 | }; |
161 | ||
162 | uart@e1050000 { | |
163 | compatible = "renesas,em-uart"; | |
164 | reg = <0xe1050000 0x38>; | |
e05ab0bb | 165 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
166 | clocks = <&usib_u3_sclk>; |
167 | clock-names = "sclk"; | |
3d5de271 | 168 | }; |
12d035b1 MD |
169 | |
170 | gpio0: gpio@e0050000 { | |
171 | compatible = "renesas,em-gio"; | |
172 | reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; | |
e05ab0bb LP |
173 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, |
174 | <0 68 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 MD |
175 | gpio-controller; |
176 | #gpio-cells = <2>; | |
177 | ngpios = <32>; | |
178 | interrupt-controller; | |
179 | #interrupt-cells = <2>; | |
180 | }; | |
181 | gpio1: gpio@e0050080 { | |
182 | compatible = "renesas,em-gio"; | |
183 | reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; | |
e05ab0bb LP |
184 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, |
185 | <0 70 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 MD |
186 | gpio-controller; |
187 | #gpio-cells = <2>; | |
188 | ngpios = <32>; | |
189 | interrupt-controller; | |
190 | #interrupt-cells = <2>; | |
191 | }; | |
192 | gpio2: gpio@e0050100 { | |
193 | compatible = "renesas,em-gio"; | |
194 | reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; | |
e05ab0bb LP |
195 | interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, |
196 | <0 72 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 MD |
197 | gpio-controller; |
198 | #gpio-cells = <2>; | |
199 | ngpios = <32>; | |
200 | interrupt-controller; | |
201 | #interrupt-cells = <2>; | |
202 | }; | |
203 | gpio3: gpio@e0050180 { | |
204 | compatible = "renesas,em-gio"; | |
205 | reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; | |
e05ab0bb LP |
206 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, |
207 | <0 74 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 MD |
208 | gpio-controller; |
209 | #gpio-cells = <2>; | |
210 | ngpios = <32>; | |
211 | interrupt-controller; | |
212 | #interrupt-cells = <2>; | |
213 | }; | |
214 | gpio4: gpio@e0050200 { | |
215 | compatible = "renesas,em-gio"; | |
216 | reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; | |
e05ab0bb LP |
217 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, |
218 | <0 76 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 MD |
219 | gpio-controller; |
220 | #gpio-cells = <2>; | |
221 | ngpios = <31>; | |
222 | interrupt-controller; | |
223 | #interrupt-cells = <2>; | |
224 | }; | |
3d5de271 | 225 | }; |