[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi

/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include "exynos4-cpu-thermal.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		serial0 = &serial_0;
		serial1 = &serial_1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cmu CLK_ARM_CLK>;
			clock-names = "cpu";
			#cooling-cells = <2>;

			operating-points = <
				1000000 1150000
				900000  1112500
				800000  1075000
				700000  1037500
				600000  1000000
				500000  962500
				400000  925000
				300000  887500
				200000  850000
				100000  850000
			>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos3250-pmu", "syscon";
			reg = <0x10020000 0x4000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
		};

		poweroff: syscon-poweroff {
			compatible = "syscon-poweroff";
			regmap = <&pmu_system_controller>;
			offset = <0x330C>; /* PS_HOLD_CONTROL */
			mask = <0x5200>; /* Reset value */
		};

		reboot: syscon-reboot {
			compatible = "syscon-reboot";
			regmap = <&pmu_system_controller>;
			offset = <0x0400>; /* SWRESET */
			mask = <0x1>;
		};

		mipi_phy: video-phy@10020710 {
			compatible = "samsung,s5pv210-mipi-video-phy";
			#phy-cells = <1>;
			syscon = <&pmu_system_controller>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
			#power-domain-cells = <0>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
			#power-domain-cells = <0>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
			#power-domain-cells = <0>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
			#power-domain-cells = <0>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
			#power-domain-cells = <0>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x20000>;
			#clock-cells = <1>;
			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
					  <&cmu CLK_MOUT_ACLK_266_SUB>;
			assigned-clock-parents = <&cmu CLK_FIN_PLL>,
						 <&cmu CLK_FIN_PLL>;
		};

		cmu_dmc: clock-controller@105C0000 {
			compatible = "samsung,exynos3250-cmu-dmc";
			reg = <0x105C0000 0x2000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			interrupt-parent = <&pmu_system_controller>;
			status = "disabled";
		};

		tmu: tmu@100C0000 {
			compatible = "samsung,exynos3250-tmu";
			reg = <0x100C0000 0x100>;
			interrupts = <0 216 0>;
			clocks = <&cmu CLK_TMU_APBIF>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		jpeg: codec@11830000 {
			compatible = "samsung,exynos3250-jpeg";
			reg = <0x11830000 0x1000>;
			interrupts = <0 171 0>;
			clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
			clock-names = "jpeg", "sclk";
			power-domains = <&pd_cam>;
			assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
			assigned-clock-rates = <0>, <150000000>;
			assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
			iommus = <&sysmmu_jpeg>;
			status = "disabled";
		};

		sysmmu_jpeg: sysmmu@11A60000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11a60000 0x1000>;
			interrupts = <0 156 0>, <0 161 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
			power-domains = <&pd_cam>;
			#iommu-cells = <0>;
		};

		fimd: fimd@11c00000 {
			compatible = "samsung,exynos3250-fimd";
			reg = <0x11c00000 0x30000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
			clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
			clock-names = "sclk_fimd", "fimd";
			power-domains = <&pd_lcd0>;
			iommus = <&sysmmu_fimd0>;
			samsung,sysreg = <&sys_reg>;
			status = "disabled";
		};

		dsi_0: dsi@11C80000 {
			compatible = "samsung,exynos3250-mipi-dsi";
			reg = <0x11C80000 0x10000>;
			interrupts = <0 83 0>;
			samsung,phy-type = <0>;
			power-domains = <&pd_lcd0>;
			phys = <&mipi_phy 1>;
			phy-names = "dsim";
			clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
			clock-names = "bus_clk", "pll_clk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sysmmu_fimd0: sysmmu@11E20000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11e20000 0x1000>;
			interrupts = <0 80 0>, <0 81 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
			power-domains = <&pd_lcd0>;
			#iommu-cells = <0>;
		};

		hsotg: hsotg@12480000 {
			compatible = "snps,dwc2";
			reg = <0x12480000 0x20000>;
			interrupts = <0 141 0>;
			clocks = <&cmu CLK_USBOTG>;
			clock-names = "otg";
			phys = <&exynos_usbphy 0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5420-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5420-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		exynos_usbphy: exynos-usbphy@125B0000 {
			compatible = "samsung,exynos3250-usb2-phy";
			reg = <0x125B0000 0x100>;
			samsung,pmureg-phandle = <&pmu_system_controller>;
			clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
			clock-names = "phy", "ref";
			#phy-cells = <1>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos3250-adc",
				     "samsung,exynos-adc-v2";
			reg = <0x126C0000 0x100>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			samsung,syscon-phandle = <&pmu_system_controller>;
			status = "disabled";
		};

		mfc: codec@13400000 {
			compatible = "samsung,mfc-v7";
			reg = <0x13400000 0x10000>;
			interrupts = <0 102 0>;
			clock-names = "mfc", "sclk_mfc";
			clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
			power-domains = <&pd_mfc>;
			iommus = <&sysmmu_mfc>;
			status = "disabled";
		};

		sysmmu_mfc: sysmmu@13620000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x13620000 0x1000>;
			interrupts = <0 96 0>, <0 98 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
			power-domains = <&pd_mfc>;
			#iommu-cells = <0>;
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_data &uart0_fctl>;
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_data>;
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		i2s2: i2s@13970000 {
			compatible = "samsung,s3c6410-i2s";
			reg = <0x13970000 0x100>;
			interrupts = <0 126 0>;
			clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0";
			dmas = <&pdma0 14>, <&pdma0 13>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&i2s2_bus>;
			pinctrl-names = "default";
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};

		ppmu_dmc0: ppmu_dmc0@106a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106a0000 0x2000>;
			status = "disabled";
		};

		ppmu_dmc1: ppmu_dmc1@106b0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106b0000 0x2000>;
			status = "disabled";
		};

		ppmu_cpu: ppmu_cpu@106c0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106c0000 0x2000>;
			status = "disabled";
		};

		ppmu_rightbus: ppmu_rightbus@112a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x112a0000 0x2000>;
			clocks = <&cmu CLK_PPMURIGHT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_leftbus: ppmu_leftbus0@116a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x116a0000 0x2000>;
			clocks = <&cmu CLK_PPMULEFT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_camif: ppmu_camif@11ac0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11ac0000 0x2000>;
			clocks = <&cmu CLK_PPMUCAMIF>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_lcd0: ppmu_lcd0@11e40000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11e40000 0x2000>;
			clocks = <&cmu CLK_PPMULCD0>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_fsys: ppmu_fsys@12630000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x12630000 0x2000>;
			clocks = <&cmu CLK_PPMUFILE>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_g3d: ppmu_g3d@13220000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13220000 0x2000>;
			clocks = <&cmu CLK_PPMUG3D>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_mfc: ppmu_mfc@13660000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13660000 0x2000>;
			clocks = <&cmu CLK_PPMUMFC_L>;
			clock-names = "ppmu";
			status = "disabled";
		};
	};
};

#include "exynos3250-pinctrl.dtsi"
Commit	Line	Data
5a992a9c TF	1	/*
	2	* Samsung's Exynos3250 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include "skeleton.dtsi"
9843a223	21	#include "exynos4-cpu-thermal.dtsi"
5a992a9c TF	22	#include <dt-bindings/clock/exynos3250.h>
	23
	24	/ {
	25	compatible = "samsung,exynos3250";
	26	interrupt-parent = <&gic>;
	27
	28	aliases {
	29	pinctrl0 = &pinctrl_0;
	30	pinctrl1 = &pinctrl_1;
	31	mshc0 = &mshc_0;
	32	mshc1 = &mshc_1;
	33	spi0 = &spi_0;
	34	spi1 = &spi_1;
	35	i2c0 = &i2c_0;
	36	i2c1 = &i2c_1;
	37	i2c2 = &i2c_2;
	38	i2c3 = &i2c_3;
	39	i2c4 = &i2c_4;
	40	i2c5 = &i2c_5;
	41	i2c6 = &i2c_6;
	42	i2c7 = &i2c_7;
1e64f48e TF	43	serial0 = &serial_0;
1e64f48e TF	44	serial1 = &serial_1;
5a992a9c TF	45	};
	46
	47	cpus {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
	50
	51	cpu0: cpu@0 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a7";
	54	reg = <0>;
	55	clock-frequency = <1000000000>;
48816aff CC	56	clocks = <&cmu CLK_ARM_CLK>;
48816aff CC	57	clock-names = "cpu";
5600f8cc	58	#cooling-cells = <2>;
48816aff CC	59
	60	operating-points = <
	61	1000000 1150000
	62	900000 1112500
	63	800000 1075000
	64	700000 1037500
	65	600000 1000000
	66	500000 962500
	67	400000 925000
	68	300000 887500
	69	200000 850000
	70	100000 850000
	71	>;
5a992a9c TF	72	};
	73
	74	cpu1: cpu@1 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a7";
	77	reg = <1>;
	78	clock-frequency = <1000000000>;
	79	};
	80	};
	81
	82	soc: soc {
	83	compatible = "simple-bus";
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87
	88	fixed-rate-clocks {
	89	#address-cells = <1>;
	90	#size-cells = <0>;
	91
	92	xusbxti: clock@0 {
	93	compatible = "fixed-clock";
	94	#address-cells = <1>;
	95	#size-cells = <0>;
	96	reg = <0>;
	97	clock-frequency = <0>;
	98	#clock-cells = <0>;
	99	clock-output-names = "xusbxti";
	100	};
	101
	102	xxti: clock@1 {
	103	compatible = "fixed-clock";
	104	reg = <1>;
	105	clock-frequency = <0>;
	106	#clock-cells = <0>;
	107	clock-output-names = "xxti";
	108	};
	109
	110	xtcxo: clock@2 {
	111	compatible = "fixed-clock";
	112	reg = <2>;
	113	clock-frequency = <0>;
	114	#clock-cells = <0>;
	115	clock-output-names = "xtcxo";
	116	};
	117	};
	118
	119	sysram@02020000 {
	120	compatible = "mmio-sram";
	121	reg = <0x02020000 0x40000>;
	122	#address-cells = <1>;
	123	#size-cells = <1>;
	124	ranges = <0 0x02020000 0x40000>;
	125
	126	smp-sysram@0 {
	127	compatible = "samsung,exynos4210-sysram";
	128	reg = <0x0 0x1000>;
	129	};
	130
	131	smp-sysram@3f000 {
	132	compatible = "samsung,exynos4210-sysram-ns";
	133	reg = <0x3f000 0x1000>;
	134	};
	135	};
136
137	chipid@10000000 {
138	compatible = "samsung,exynos4210-chipid";
139	reg = <0x10000000 0x100>;
140	};
141
142	sys_reg: syscon@10010000 {
143	compatible = "samsung,exynos3-sysreg", "syscon";
144	reg = <0x10010000 0x400>;
145	};
146
25023926 CC	147	pmu_system_controller: system-controller@10020000 {
	148	compatible = "samsung,exynos3250-pmu", "syscon";
	149	reg = <0x10020000 0x4000>;
8b283c02 MZ	150	interrupt-controller;
	151	#interrupt-cells = <3>;
	152	interrupt-parent = <&gic>;
25023926 CC	153	};
25023926 CC	154
4fb19672 AA	155	poweroff: syscon-poweroff {
	156	compatible = "syscon-poweroff";
	157	regmap = <&pmu_system_controller>;
	158	offset = <0x330C>; /* PS_HOLD_CONTROL */
	159	mask = <0x5200>; /* Reset value */
	160	};
	161
	162	reboot: syscon-reboot {
	163	compatible = "syscon-reboot";
	164	regmap = <&pmu_system_controller>;
	165	offset = <0x0400>; /* SWRESET */
	166	mask = <0x1>;
	167	};
	168
9fab9d6a ID	169	mipi_phy: video-phy@10020710 {
9fab9d6a ID	170	compatible = "samsung,s5pv210-mipi-video-phy";
9fab9d6a	171	#phy-cells = <1>;
1342ff45	172	syscon = <&pmu_system_controller>;
9fab9d6a ID	173	};
9fab9d6a ID	174
5a992a9c TF	175	pd_cam: cam-power-domain@10023C00 {
	176	compatible = "samsung,exynos4210-pd";
	177	reg = <0x10023C00 0x20>;
0da65870	178	#power-domain-cells = <0>;
5a992a9c TF	179	};
	180
	181	pd_mfc: mfc-power-domain@10023C40 {
	182	compatible = "samsung,exynos4210-pd";
	183	reg = <0x10023C40 0x20>;
0da65870	184	#power-domain-cells = <0>;
5a992a9c TF	185	};
	186
	187	pd_g3d: g3d-power-domain@10023C60 {
	188	compatible = "samsung,exynos4210-pd";
	189	reg = <0x10023C60 0x20>;
0da65870	190	#power-domain-cells = <0>;
5a992a9c TF	191	};
	192
	193	pd_lcd0: lcd0-power-domain@10023C80 {
	194	compatible = "samsung,exynos4210-pd";
	195	reg = <0x10023C80 0x20>;
0da65870	196	#power-domain-cells = <0>;
5a992a9c TF	197	};
	198
	199	pd_isp: isp-power-domain@10023CA0 {
	200	compatible = "samsung,exynos4210-pd";
	201	reg = <0x10023CA0 0x20>;
0da65870	202	#power-domain-cells = <0>;
5a992a9c TF	203	};
	204
	205	cmu: clock-controller@10030000 {
	206	compatible = "samsung,exynos3250-cmu";
	207	reg = <0x10030000 0x20000>;
	208	#clock-cells = <1>;
52005dec BM	209	assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
	210	<&cmu CLK_MOUT_ACLK_266_SUB>;
	211	assigned-clock-parents = <&cmu CLK_FIN_PLL>,
	212	<&cmu CLK_FIN_PLL>;
5a992a9c TF	213	};
5a992a9c TF	214
d0e73eaf KK	215	cmu_dmc: clock-controller@105C0000 {
	216	compatible = "samsung,exynos3250-cmu-dmc";
	217	reg = <0x105C0000 0x2000>;
	218	#clock-cells = <1>;
	219	};
	220
5a992a9c	221	rtc: rtc@10070000 {
062f49c4	222	compatible = "samsung,s3c6410-rtc";
5a992a9c TF	223	reg = <0x10070000 0x100>;
5a992a9c TF	224	interrupts = <0 73 0>, <0 74 0>;
8b283c02	225	interrupt-parent = <&pmu_system_controller>;
5a992a9c TF	226	status = "disabled";
	227	};
	228
9dfb3347 CC	229	tmu: tmu@100C0000 {
	230	compatible = "samsung,exynos3250-tmu";
	231	reg = <0x100C0000 0x100>;
	232	interrupts = <0 216 0>;
	233	clocks = <&cmu CLK_TMU_APBIF>;
	234	clock-names = "tmu_apbif";
9843a223	235	#include "exynos4412-tmu-sensor-conf.dtsi"
9dfb3347 CC	236	status = "disabled";
	237	};
	238
5a992a9c TF	239	gic: interrupt-controller@10481000 {
	240	compatible = "arm,cortex-a15-gic";
	241	#interrupt-cells = <3>;
	242	interrupt-controller;
	243	reg = <0x10481000 0x1000>,
	244	<0x10482000 0x1000>,
	245	<0x10484000 0x2000>,
	246	<0x10486000 0x2000>;
	247	interrupts = <1 9 0xf04>;
	248	};
	249
	250	mct@10050000 {
	251	compatible = "samsung,exynos4210-mct";
	252	reg = <0x10050000 0x800>;
	253	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
	254	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
	255	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
	256	clock-names = "fin_pll", "mct";
	257	};
	258
	259	pinctrl_1: pinctrl@11000000 {
	260	compatible = "samsung,exynos3250-pinctrl";
	261	reg = <0x11000000 0x1000>;
	262	interrupts = <0 225 0>;
	263
	264	wakeup-interrupt-controller {
	265	compatible = "samsung,exynos4210-wakeup-eint";
5a992a9c TF	266	interrupts = <0 48 0>;
	267	};
	268	};
	269
	270	pinctrl_0: pinctrl@11400000 {
	271	compatible = "samsung,exynos3250-pinctrl";
	272	reg = <0x11400000 0x1000>;
	273	interrupts = <0 240 0>;
	274	};
	275
c9c1adfe JA	276	jpeg: codec@11830000 {
	277	compatible = "samsung,exynos3250-jpeg";
	278	reg = <0x11830000 0x1000>;
	279	interrupts = <0 171 0>;
	280	clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
	281	clock-names = "jpeg", "sclk";
	282	power-domains = <&pd_cam>;
	283	assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
	284	assigned-clock-rates = <0>, <150000000>;
	285	assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
f5976ce5	286	iommus = <&sysmmu_jpeg>;
c9c1adfe JA	287	status = "disabled";
	288	};
	289
f5976ce5 MS	290	sysmmu_jpeg: sysmmu@11A60000 {
	291	compatible = "samsung,exynos-sysmmu";
	292	reg = <0x11a60000 0x1000>;
	293	interrupts = <0 156 0>, <0 161 0>;
	294	clock-names = "sysmmu", "master";
	295	clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
	296	power-domains = <&pd_cam>;
	297	#iommu-cells = <0>;
	298	};
	299
03b86c79 ID	300	fimd: fimd@11c00000 {
	301	compatible = "samsung,exynos3250-fimd";
	302	reg = <0x11c00000 0x30000>;
	303	interrupt-names = "fifo", "vsync", "lcd_sys";
	304	interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
	305	clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
	306	clock-names = "sclk_fimd", "fimd";
0da65870	307	power-domains = <&pd_lcd0>;
f5976ce5	308	iommus = <&sysmmu_fimd0>;
03b86c79 ID	309	samsung,sysreg = <&sys_reg>;
	310	status = "disabled";
	311	};
	312
025d8e13 ID	313	dsi_0: dsi@11C80000 {
	314	compatible = "samsung,exynos3250-mipi-dsi";
	315	reg = <0x11C80000 0x10000>;
	316	interrupts = <0 83 0>;
	317	samsung,phy-type = <0>;
0da65870	318	power-domains = <&pd_lcd0>;
025d8e13 ID	319	phys = <&mipi_phy 1>;
	320	phy-names = "dsim";
	321	clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
	322	clock-names = "bus_clk", "pll_clk";
	323	#address-cells = <1>;
	324	#size-cells = <0>;
	325	status = "disabled";
	326	};
	327
f5976ce5 MS	328	sysmmu_fimd0: sysmmu@11E20000 {
	329	compatible = "samsung,exynos-sysmmu";
	330	reg = <0x11e20000 0x1000>;
	331	interrupts = <0 80 0>, <0 81 0>;
	332	clock-names = "sysmmu", "master";
	333	clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
	334	power-domains = <&pd_lcd0>;
	335	#iommu-cells = <0>;
	336	};
	337
e0c6e929 JK	338	hsotg: hsotg@12480000 {
	339	compatible = "snps,dwc2";
	340	reg = <0x12480000 0x20000>;
	341	interrupts = <0 141 0>;
	342	clocks = <&cmu CLK_USBOTG>;
	343	clock-names = "otg";
	344	phys = <&exynos_usbphy 0>;
	345	phy-names = "usb2-phy";
	346	status = "disabled";
	347	};
	348
5a992a9c	349	mshc_0: mshc@12510000 {
b29dd5fa	350	compatible = "samsung,exynos5420-dw-mshc";
5a992a9c TF	351	reg = <0x12510000 0x1000>;
	352	interrupts = <0 142 0>;
	353	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
	354	clock-names = "biu", "ciu";
	355	fifo-depth = <0x80>;
	356	#address-cells = <1>;
	357	#size-cells = <0>;
	358	status = "disabled";
	359	};
	360
	361	mshc_1: mshc@12520000 {
b29dd5fa	362	compatible = "samsung,exynos5420-dw-mshc";
5a992a9c TF	363	reg = <0x12520000 0x1000>;
	364	interrupts = <0 143 0>;
	365	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
	366	clock-names = "biu", "ciu";
	367	fifo-depth = <0x80>;
	368	#address-cells = <1>;
	369	#size-cells = <0>;
	370	status = "disabled";
	371	};
	372
11ab02b8 JK	373	exynos_usbphy: exynos-usbphy@125B0000 {
	374	compatible = "samsung,exynos3250-usb2-phy";
	375	reg = <0x125B0000 0x100>;
	376	samsung,pmureg-phandle = <&pmu_system_controller>;
	377	clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
	378	clock-names = "phy", "ref";
	379	#phy-cells = <1>;
	380	status = "disabled";
	381	};
	382
5a992a9c TF	383	amba {
	384	compatible = "arm,amba-bus";
	385	#address-cells = <1>;
	386	#size-cells = <1>;
5a992a9c TF	387	ranges;
	388
	389	pdma0: pdma@12680000 {
	390	compatible = "arm,pl330", "arm,primecell";
	391	reg = <0x12680000 0x1000>;
	392	interrupts = <0 138 0>;
	393	clocks = <&cmu CLK_PDMA0>;
	394	clock-names = "apb_pclk";
	395	#dma-cells = <1>;
	396	#dma-channels = <8>;
	397	#dma-requests = <32>;
	398	};
	399
	400	pdma1: pdma@12690000 {
	401	compatible = "arm,pl330", "arm,primecell";
	402	reg = <0x12690000 0x1000>;
	403	interrupts = <0 139 0>;
	404	clocks = <&cmu CLK_PDMA1>;
	405	clock-names = "apb_pclk";
	406	#dma-cells = <1>;
	407	#dma-channels = <8>;
	408	#dma-requests = <32>;
	409	};
	410	};
	411
	412	adc: adc@126C0000 {
e6ca2d84 CC	413	compatible = "samsung,exynos3250-adc",
e6ca2d84 CC	414	"samsung,exynos-adc-v2";
db9bf4d6	415	reg = <0x126C0000 0x100>;
5a992a9c	416	interrupts = <0 137 0>;
e6ca2d84	417	clock-names = "adc", "sclk";
5a992a9c TF	418	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
	419	#io-channel-cells = <1>;
	420	io-channel-ranges;
db9bf4d6	421	samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c TF	422	status = "disabled";
	423	};
	424
752d3a23 JA	425	mfc: codec@13400000 {
	426	compatible = "samsung,mfc-v7";
	427	reg = <0x13400000 0x10000>;
	428	interrupts = <0 102 0>;
	429	clock-names = "mfc", "sclk_mfc";
	430	clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0da65870	431	power-domains = <&pd_mfc>;
f5976ce5	432	iommus = <&sysmmu_mfc>;
752d3a23 JA	433	status = "disabled";
	434	};
	435
f5976ce5 MS	436	sysmmu_mfc: sysmmu@13620000 {
	437	compatible = "samsung,exynos-sysmmu";
	438	reg = <0x13620000 0x1000>;
	439	interrupts = <0 96 0>, <0 98 0>;
	440	clock-names = "sysmmu", "master";
	441	clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
	442	power-domains = <&pd_mfc>;
	443	#iommu-cells = <0>;
	444	};
	445
5a992a9c TF	446	serial_0: serial@13800000 {
	447	compatible = "samsung,exynos4210-uart";
	448	reg = <0x13800000 0x100>;
	449	interrupts = <0 109 0>;
	450	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
	451	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	452	pinctrl-names = "default";
a9408a6b CC	453	pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c TF	454	status = "disabled";
	455	};
	456
	457	serial_1: serial@13810000 {
	458	compatible = "samsung,exynos4210-uart";
	459	reg = <0x13810000 0x100>;
	460	interrupts = <0 110 0>;
	461	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
	462	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	463	pinctrl-names = "default";
a9408a6b CC	464	pinctrl-0 = <&uart1_data>;
5a992a9c TF	465	status = "disabled";
	466	};
	467
	468	i2c_0: i2c@13860000 {
	469	#address-cells = <1>;
	470	#size-cells = <0>;
	471	compatible = "samsung,s3c2440-i2c";
	472	reg = <0x13860000 0x100>;
	473	interrupts = <0 113 0>;
	474	clocks = <&cmu CLK_I2C0>;
	475	clock-names = "i2c";
	476	pinctrl-names = "default";
	477	pinctrl-0 = <&i2c0_bus>;
	478	status = "disabled";
	479	};
	480
	481	i2c_1: i2c@13870000 {
	482	#address-cells = <1>;
	483	#size-cells = <0>;
	484	compatible = "samsung,s3c2440-i2c";
	485	reg = <0x13870000 0x100>;
	486	interrupts = <0 114 0>;
	487	clocks = <&cmu CLK_I2C1>;
	488	clock-names = "i2c";
	489	pinctrl-names = "default";
	490	pinctrl-0 = <&i2c1_bus>;
	491	status = "disabled";
	492	};
	493
	494	i2c_2: i2c@13880000 {
	495	#address-cells = <1>;
	496	#size-cells = <0>;
	497	compatible = "samsung,s3c2440-i2c";
	498	reg = <0x13880000 0x100>;
	499	interrupts = <0 115 0>;
	500	clocks = <&cmu CLK_I2C2>;
	501	clock-names = "i2c";
	502	pinctrl-names = "default";
	503	pinctrl-0 = <&i2c2_bus>;
	504	status = "disabled";
	505	};
	506
	507	i2c_3: i2c@13890000 {
	508	#address-cells = <1>;
	509	#size-cells = <0>;
	510	compatible = "samsung,s3c2440-i2c";
	511	reg = <0x13890000 0x100>;
	512	interrupts = <0 116 0>;
	513	clocks = <&cmu CLK_I2C3>;
	514	clock-names = "i2c";
	515	pinctrl-names = "default";
	516	pinctrl-0 = <&i2c3_bus>;
	517	status = "disabled";
	518	};
	519
	520	i2c_4: i2c@138A0000 {
	521	#address-cells = <1>;
	522	#size-cells = <0>;
	523	compatible = "samsung,s3c2440-i2c";
	524	reg = <0x138A0000 0x100>;
	525	interrupts = <0 117 0>;
	526	clocks = <&cmu CLK_I2C4>;
	527	clock-names = "i2c";
	528	pinctrl-names = "default";
529	pinctrl-0 = <&i2c4_bus>;
530	status = "disabled";
531	};
532
533	i2c_5: i2c@138B0000 {
534	#address-cells = <1>;
535	#size-cells = <0>;
536	compatible = "samsung,s3c2440-i2c";
537	reg = <0x138B0000 0x100>;
538	interrupts = <0 118 0>;
539	clocks = <&cmu CLK_I2C5>;
540	clock-names = "i2c";
541	pinctrl-names = "default";
542	pinctrl-0 = <&i2c5_bus>;
543	status = "disabled";
544	};
545
546	i2c_6: i2c@138C0000 {
547	#address-cells = <1>;
548	#size-cells = <0>;
549	compatible = "samsung,s3c2440-i2c";
550	reg = <0x138C0000 0x100>;
551	interrupts = <0 119 0>;
552	clocks = <&cmu CLK_I2C6>;
553	clock-names = "i2c";
554	pinctrl-names = "default";
555	pinctrl-0 = <&i2c6_bus>;
556	status = "disabled";
557	};
558
559	i2c_7: i2c@138D0000 {
560	#address-cells = <1>;
561	#size-cells = <0>;
562	compatible = "samsung,s3c2440-i2c";
563	reg = <0x138D0000 0x100>;
564	interrupts = <0 120 0>;
565	clocks = <&cmu CLK_I2C7>;
566	clock-names = "i2c";
567	pinctrl-names = "default";
568	pinctrl-0 = <&i2c7_bus>;
569	status = "disabled";
570	};
571
572	spi_0: spi@13920000 {
573	compatible = "samsung,exynos4210-spi";
574	reg = <0x13920000 0x100>;
575	interrupts = <0 121 0>;
576	dmas = <&pdma0 7>, <&pdma0 6>;
577	dma-names = "tx", "rx";
578	#address-cells = <1>;
579	#size-cells = <0>;
580	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
581	clock-names = "spi", "spi_busclk0";
582	samsung,spi-src-clk = <0>;
583	pinctrl-names = "default";
584	pinctrl-0 = <&spi0_bus>;
585	status = "disabled";
586	};
587
588	spi_1: spi@13930000 {
589	compatible = "samsung,exynos4210-spi";
590	reg = <0x13930000 0x100>;
591	interrupts = <0 122 0>;
592	dmas = <&pdma1 7>, <&pdma1 6>;
593	dma-names = "tx", "rx";
594	#address-cells = <1>;
595	#size-cells = <0>;
596	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
597	clock-names = "spi", "spi_busclk0";
598	samsung,spi-src-clk = <0>;
599	pinctrl-names = "default";
600	pinctrl-0 = <&spi1_bus>;
601	status = "disabled";
602	};
603
ccaba452 TF	604	i2s2: i2s@13970000 {
	605	compatible = "samsung,s3c6410-i2s";
	606	reg = <0x13970000 0x100>;
	607	interrupts = <0 126 0>;
	608	clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
	609	clock-names = "iis", "i2s_opclk0";
	610	dmas = <&pdma0 14>, <&pdma0 13>;
	611	dma-names = "tx", "rx";
	612	pinctrl-0 = <&i2s2_bus>;
	613	pinctrl-names = "default";
	614	status = "disabled";
	615	};
	616
5a992a9c TF	617	pwm: pwm@139D0000 {
	618	compatible = "samsung,exynos4210-pwm";
	619	reg = <0x139D0000 0x1000>;
	620	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
	621	<0 107 0>, <0 108 0>;
	622	#pwm-cells = <3>;
	623	status = "disabled";
	624	};
	625
	626	pmu {
	627	compatible = "arm,cortex-a7-pmu";
	628	interrupts = <0 18 0>, <0 19 0>;
	629	};
e4502367 CC	630
	631	ppmu_dmc0: ppmu_dmc0@106a0000 {
	632	compatible = "samsung,exynos-ppmu";
	633	reg = <0x106a0000 0x2000>;
	634	status = "disabled";
	635	};
	636
	637	ppmu_dmc1: ppmu_dmc1@106b0000 {
	638	compatible = "samsung,exynos-ppmu";
	639	reg = <0x106b0000 0x2000>;
	640	status = "disabled";
	641	};
	642
	643	ppmu_cpu: ppmu_cpu@106c0000 {
	644	compatible = "samsung,exynos-ppmu";
	645	reg = <0x106c0000 0x2000>;
	646	status = "disabled";
	647	};
	648
	649	ppmu_rightbus: ppmu_rightbus@112a0000 {
	650	compatible = "samsung,exynos-ppmu";
	651	reg = <0x112a0000 0x2000>;
	652	clocks = <&cmu CLK_PPMURIGHT>;
	653	clock-names = "ppmu";
	654	status = "disabled";
	655	};
	656
	657	ppmu_leftbus: ppmu_leftbus0@116a0000 {
	658	compatible = "samsung,exynos-ppmu";
	659	reg = <0x116a0000 0x2000>;
	660	clocks = <&cmu CLK_PPMULEFT>;
	661	clock-names = "ppmu";
	662	status = "disabled";
	663	};
	664
	665	ppmu_camif: ppmu_camif@11ac0000 {
	666	compatible = "samsung,exynos-ppmu";
	667	reg = <0x11ac0000 0x2000>;
	668	clocks = <&cmu CLK_PPMUCAMIF>;
	669	clock-names = "ppmu";
	670	status = "disabled";
	671	};
	672
	673	ppmu_lcd0: ppmu_lcd0@11e40000 {
	674	compatible = "samsung,exynos-ppmu";
	675	reg = <0x11e40000 0x2000>;
	676	clocks = <&cmu CLK_PPMULCD0>;
	677	clock-names = "ppmu";
	678	status = "disabled";
	679	};
	680
	681	ppmu_fsys: ppmu_fsys@12630000 {
	682	compatible = "samsung,exynos-ppmu";
	683	reg = <0x12630000 0x2000>;
	684	clocks = <&cmu CLK_PPMUFILE>;
	685	clock-names = "ppmu";
	686	status = "disabled";
	687	};
	688
	689	ppmu_g3d: ppmu_g3d@13220000 {
	690	compatible = "samsung,exynos-ppmu";
	691	reg = <0x13220000 0x2000>;
	692	clocks = <&cmu CLK_PPMUG3D>;
	693	clock-names = "ppmu";
694	status = "disabled";
695	};
696
697	ppmu_mfc: ppmu_mfc@13660000 {
698	compatible = "samsung,exynos-ppmu";
699	reg = <0x13660000 0x2000>;
700	clocks = <&cmu CLK_PPMUMFC_L>;
701	clock-names = "ppmu";
702	status = "disabled";
703	};
5a992a9c TF	704	};
	705	};
	706
	707	#include "exynos3250-pinctrl.dtsi"