[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi

/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		serial0 = &serial_0;
		serial1 = &serial_1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos3250-pmu", "syscon";
			reg = <0x10020000 0x4000>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x20000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&gic>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos-adc-v3";
			reg = <0x126C0000 0x100>, <0x10020718 0x4>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk_tsadc";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			status = "disabled";
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};
	};
};

#include "exynos3250-pinctrl.dtsi"
Commit	Line	Data
5a992a9c TF	1	/*
	2	* Samsung's Exynos3250 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include "skeleton.dtsi"
	21	#include <dt-bindings/clock/exynos3250.h>
	22
	23	/ {
	24	compatible = "samsung,exynos3250";
	25	interrupt-parent = <&gic>;
	26
	27	aliases {
	28	pinctrl0 = &pinctrl_0;
	29	pinctrl1 = &pinctrl_1;
	30	mshc0 = &mshc_0;
	31	mshc1 = &mshc_1;
	32	spi0 = &spi_0;
	33	spi1 = &spi_1;
	34	i2c0 = &i2c_0;
	35	i2c1 = &i2c_1;
	36	i2c2 = &i2c_2;
	37	i2c3 = &i2c_3;
	38	i2c4 = &i2c_4;
	39	i2c5 = &i2c_5;
	40	i2c6 = &i2c_6;
	41	i2c7 = &i2c_7;
1e64f48e TF	42	serial0 = &serial_0;
1e64f48e TF	43	serial1 = &serial_1;
5a992a9c TF	44	};
	45
	46	cpus {
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
	50	cpu0: cpu@0 {
	51	device_type = "cpu";
	52	compatible = "arm,cortex-a7";
	53	reg = <0>;
	54	clock-frequency = <1000000000>;
	55	};
	56
	57	cpu1: cpu@1 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a7";
	60	reg = <1>;
	61	clock-frequency = <1000000000>;
	62	};
	63	};
	64
	65	soc: soc {
	66	compatible = "simple-bus";
	67	#address-cells = <1>;
	68	#size-cells = <1>;
	69	ranges;
	70
	71	fixed-rate-clocks {
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74
	75	xusbxti: clock@0 {
	76	compatible = "fixed-clock";
	77	#address-cells = <1>;
	78	#size-cells = <0>;
	79	reg = <0>;
	80	clock-frequency = <0>;
	81	#clock-cells = <0>;
	82	clock-output-names = "xusbxti";
	83	};
	84
	85	xxti: clock@1 {
	86	compatible = "fixed-clock";
	87	reg = <1>;
	88	clock-frequency = <0>;
	89	#clock-cells = <0>;
	90	clock-output-names = "xxti";
	91	};
	92
	93	xtcxo: clock@2 {
	94	compatible = "fixed-clock";
	95	reg = <2>;
	96	clock-frequency = <0>;
	97	#clock-cells = <0>;
	98	clock-output-names = "xtcxo";
	99	};
	100	};
	101
	102	sysram@02020000 {
	103	compatible = "mmio-sram";
	104	reg = <0x02020000 0x40000>;
	105	#address-cells = <1>;
	106	#size-cells = <1>;
	107	ranges = <0 0x02020000 0x40000>;
108
109	smp-sysram@0 {
110	compatible = "samsung,exynos4210-sysram";
111	reg = <0x0 0x1000>;
112	};
113
114	smp-sysram@3f000 {
115	compatible = "samsung,exynos4210-sysram-ns";
116	reg = <0x3f000 0x1000>;
117	};
118	};
119
120	chipid@10000000 {
121	compatible = "samsung,exynos4210-chipid";
122	reg = <0x10000000 0x100>;
123	};
124
125	sys_reg: syscon@10010000 {
126	compatible = "samsung,exynos3-sysreg", "syscon";
127	reg = <0x10010000 0x400>;
128	};
129
25023926 CC	130	pmu_system_controller: system-controller@10020000 {
	131	compatible = "samsung,exynos3250-pmu", "syscon";
	132	reg = <0x10020000 0x4000>;
	133	};
	134
5a992a9c TF	135	pd_cam: cam-power-domain@10023C00 {
	136	compatible = "samsung,exynos4210-pd";
	137	reg = <0x10023C00 0x20>;
	138	};
	139
	140	pd_mfc: mfc-power-domain@10023C40 {
	141	compatible = "samsung,exynos4210-pd";
	142	reg = <0x10023C40 0x20>;
	143	};
	144
	145	pd_g3d: g3d-power-domain@10023C60 {
	146	compatible = "samsung,exynos4210-pd";
	147	reg = <0x10023C60 0x20>;
	148	};
	149
	150	pd_lcd0: lcd0-power-domain@10023C80 {
	151	compatible = "samsung,exynos4210-pd";
	152	reg = <0x10023C80 0x20>;
	153	};
	154
	155	pd_isp: isp-power-domain@10023CA0 {
	156	compatible = "samsung,exynos4210-pd";
	157	reg = <0x10023CA0 0x20>;
	158	};
	159
	160	cmu: clock-controller@10030000 {
	161	compatible = "samsung,exynos3250-cmu";
	162	reg = <0x10030000 0x20000>;
	163	#clock-cells = <1>;
	164	};
	165
	166	rtc: rtc@10070000 {
	167	compatible = "samsung,s3c6410-rtc";
	168	reg = <0x10070000 0x100>;
	169	interrupts = <0 73 0>, <0 74 0>;
	170	status = "disabled";
	171	};
	172
	173	gic: interrupt-controller@10481000 {
	174	compatible = "arm,cortex-a15-gic";
	175	#interrupt-cells = <3>;
	176	interrupt-controller;
	177	reg = <0x10481000 0x1000>,
	178	<0x10482000 0x1000>,
	179	<0x10484000 0x2000>,
	180	<0x10486000 0x2000>;
	181	interrupts = <1 9 0xf04>;
	182	};
	183
	184	mct@10050000 {
	185	compatible = "samsung,exynos4210-mct";
	186	reg = <0x10050000 0x800>;
	187	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
	188	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
	189	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
	190	clock-names = "fin_pll", "mct";
	191	};
	192
	193	pinctrl_1: pinctrl@11000000 {
	194	compatible = "samsung,exynos3250-pinctrl";
	195	reg = <0x11000000 0x1000>;
	196	interrupts = <0 225 0>;
	197
	198	wakeup-interrupt-controller {
199	compatible = "samsung,exynos4210-wakeup-eint";
200	interrupt-parent = <&gic>;
201	interrupts = <0 48 0>;
202	};
203	};
204
205	pinctrl_0: pinctrl@11400000 {
206	compatible = "samsung,exynos3250-pinctrl";
207	reg = <0x11400000 0x1000>;
208	interrupts = <0 240 0>;
209	};
210
211	mshc_0: mshc@12510000 {
212	compatible = "samsung,exynos5250-dw-mshc";
213	reg = <0x12510000 0x1000>;
214	interrupts = <0 142 0>;
215	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
216	clock-names = "biu", "ciu";
217	fifo-depth = <0x80>;
218	#address-cells = <1>;
219	#size-cells = <0>;
220	status = "disabled";
221	};
222
223	mshc_1: mshc@12520000 {
224	compatible = "samsung,exynos5250-dw-mshc";
225	reg = <0x12520000 0x1000>;
226	interrupts = <0 143 0>;
227	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
228	clock-names = "biu", "ciu";
229	fifo-depth = <0x80>;
230	#address-cells = <1>;
231	#size-cells = <0>;
232	status = "disabled";
233	};
234
235	amba {
236	compatible = "arm,amba-bus";
237	#address-cells = <1>;
238	#size-cells = <1>;
239	interrupt-parent = <&gic>;
240	ranges;
241
242	pdma0: pdma@12680000 {
243	compatible = "arm,pl330", "arm,primecell";
244	reg = <0x12680000 0x1000>;
245	interrupts = <0 138 0>;
246	clocks = <&cmu CLK_PDMA0>;
247	clock-names = "apb_pclk";
248	#dma-cells = <1>;
249	#dma-channels = <8>;
250	#dma-requests = <32>;
251	};
252
253	pdma1: pdma@12690000 {
254	compatible = "arm,pl330", "arm,primecell";
255	reg = <0x12690000 0x1000>;
256	interrupts = <0 139 0>;
257	clocks = <&cmu CLK_PDMA1>;
258	clock-names = "apb_pclk";
259	#dma-cells = <1>;
260	#dma-channels = <8>;
261	#dma-requests = <32>;
262	};
263	};
264
265	adc: adc@126C0000 {
266	compatible = "samsung,exynos-adc-v3";
267	reg = <0x126C0000 0x100>, <0x10020718 0x4>;
268	interrupts = <0 137 0>;
269	clock-names = "adc", "sclk_tsadc";
270	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
271	#io-channel-cells = <1>;
272	io-channel-ranges;
273	status = "disabled";
274	};
275
276	serial_0: serial@13800000 {
277	compatible = "samsung,exynos4210-uart";
278	reg = <0x13800000 0x100>;
279	interrupts = <0 109 0>;
280	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
281	clock-names = "uart", "clk_uart_baud0";
282	status = "disabled";
283	};
284
285	serial_1: serial@13810000 {
286	compatible = "samsung,exynos4210-uart";
287	reg = <0x13810000 0x100>;
288	interrupts = <0 110 0>;
289	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
290	clock-names = "uart", "clk_uart_baud0";
291	status = "disabled";
292	};
293
294	i2c_0: i2c@13860000 {
295	#address-cells = <1>;
296	#size-cells = <0>;
297	compatible = "samsung,s3c2440-i2c";
298	reg = <0x13860000 0x100>;
299	interrupts = <0 113 0>;
300	clocks = <&cmu CLK_I2C0>;
301	clock-names = "i2c";
302	pinctrl-names = "default";
303	pinctrl-0 = <&i2c0_bus>;
304	status = "disabled";
305	};
306
307	i2c_1: i2c@13870000 {
308	#address-cells = <1>;
309	#size-cells = <0>;
310	compatible = "samsung,s3c2440-i2c";
311	reg = <0x13870000 0x100>;
312	interrupts = <0 114 0>;
313	clocks = <&cmu CLK_I2C1>;
314	clock-names = "i2c";
315	pinctrl-names = "default";
316	pinctrl-0 = <&i2c1_bus>;
317	status = "disabled";
318	};
319
320	i2c_2: i2c@13880000 {
321	#address-cells = <1>;
322	#size-cells = <0>;
323	compatible = "samsung,s3c2440-i2c";
324	reg = <0x13880000 0x100>;
325	interrupts = <0 115 0>;
326	clocks = <&cmu CLK_I2C2>;
327	clock-names = "i2c";
328	pinctrl-names = "default";
329	pinctrl-0 = <&i2c2_bus>;
330	status = "disabled";
331	};
332
333	i2c_3: i2c@13890000 {
334	#address-cells = <1>;
335	#size-cells = <0>;
336	compatible = "samsung,s3c2440-i2c";
337	reg = <0x13890000 0x100>;
338	interrupts = <0 116 0>;
339	clocks = <&cmu CLK_I2C3>;
340	clock-names = "i2c";
341	pinctrl-names = "default";
342	pinctrl-0 = <&i2c3_bus>;
343	status = "disabled";
344	};
345
346	i2c_4: i2c@138A0000 {
347	#address-cells = <1>;
348	#size-cells = <0>;
349	compatible = "samsung,s3c2440-i2c";
350	reg = <0x138A0000 0x100>;
351	interrupts = <0 117 0>;
352	clocks = <&cmu CLK_I2C4>;
353	clock-names = "i2c";
354	pinctrl-names = "default";
355	pinctrl-0 = <&i2c4_bus>;
356	status = "disabled";
357	};
358
359	i2c_5: i2c@138B0000 {
360	#address-cells = <1>;
361	#size-cells = <0>;
362	compatible = "samsung,s3c2440-i2c";
363	reg = <0x138B0000 0x100>;
364	interrupts = <0 118 0>;
365	clocks = <&cmu CLK_I2C5>;
366	clock-names = "i2c";
367	pinctrl-names = "default";
368	pinctrl-0 = <&i2c5_bus>;
369	status = "disabled";
370	};
371
372	i2c_6: i2c@138C0000 {
373	#address-cells = <1>;
374	#size-cells = <0>;
375	compatible = "samsung,s3c2440-i2c";
376	reg = <0x138C0000 0x100>;
377	interrupts = <0 119 0>;
378	clocks = <&cmu CLK_I2C6>;
379	clock-names = "i2c";
380	pinctrl-names = "default";
381	pinctrl-0 = <&i2c6_bus>;
382	status = "disabled";
383	};
384
385	i2c_7: i2c@138D0000 {
386	#address-cells = <1>;
387	#size-cells = <0>;
388	compatible = "samsung,s3c2440-i2c";
389	reg = <0x138D0000 0x100>;
390	interrupts = <0 120 0>;
391	clocks = <&cmu CLK_I2C7>;
392	clock-names = "i2c";
393	pinctrl-names = "default";
394	pinctrl-0 = <&i2c7_bus>;
395	status = "disabled";
396	};
397
398	spi_0: spi@13920000 {
399	compatible = "samsung,exynos4210-spi";
400	reg = <0x13920000 0x100>;
401	interrupts = <0 121 0>;
402	dmas = <&pdma0 7>, <&pdma0 6>;
403	dma-names = "tx", "rx";
404	#address-cells = <1>;
405	#size-cells = <0>;
406	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
407	clock-names = "spi", "spi_busclk0";
408	samsung,spi-src-clk = <0>;
409	pinctrl-names = "default";
410	pinctrl-0 = <&spi0_bus>;
411	status = "disabled";
412	};
413
414	spi_1: spi@13930000 {
415	compatible = "samsung,exynos4210-spi";
416	reg = <0x13930000 0x100>;
417	interrupts = <0 122 0>;
418	dmas = <&pdma1 7>, <&pdma1 6>;
419	dma-names = "tx", "rx";
420	#address-cells = <1>;
421	#size-cells = <0>;
422	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
423	clock-names = "spi", "spi_busclk0";
424	samsung,spi-src-clk = <0>;
425	pinctrl-names = "default";
426	pinctrl-0 = <&spi1_bus>;
427	status = "disabled";
428	};
429
430	pwm: pwm@139D0000 {
431	compatible = "samsung,exynos4210-pwm";
432	reg = <0x139D0000 0x1000>;
433	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
434	<0 107 0>, <0 108 0>;
435	#pwm-cells = <3>;
436	status = "disabled";
437	};
438
439	pmu {
440	compatible = "arm,cortex-a7-pmu";
441	interrupts = <0 18 0>, <0 19 0>;
442	};
443	};
444	};
445
446	#include "exynos3250-pinctrl.dtsi"