Commit | Line | Data |
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0f7238a1 TF |
1 | /* |
2 | * Samsung's Exynos4x12 SoCs device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 | |
8 | * based board files can include this file and provide values for board specfic | |
9 | * bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional | |
13 | * nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
3799279f PV |
20 | #include "exynos4.dtsi" |
21 | #include "exynos4x12-pinctrl.dtsi" | |
9843a223 | 22 | #include "exynos4-cpu-thermal.dtsi" |
0f7238a1 TF |
23 | |
24 | / { | |
64a57434 TF |
25 | aliases { |
26 | pinctrl0 = &pinctrl_0; | |
27 | pinctrl1 = &pinctrl_1; | |
28 | pinctrl2 = &pinctrl_2; | |
29 | pinctrl3 = &pinctrl_3; | |
582435b3 SN |
30 | fimc-lite0 = &fimc_lite_0; |
31 | fimc-lite1 = &fimc_lite_1; | |
56d52bfb | 32 | mshc0 = &mshc_0; |
64a57434 TF |
33 | }; |
34 | ||
b3205dea SK |
35 | sysram@02020000 { |
36 | compatible = "mmio-sram"; | |
37 | reg = <0x02020000 0x40000>; | |
38 | #address-cells = <1>; | |
39 | #size-cells = <1>; | |
40 | ranges = <0 0x02020000 0x40000>; | |
41 | ||
42 | smp-sysram@0 { | |
43 | compatible = "samsung,exynos4210-sysram"; | |
44 | reg = <0x0 0x1000>; | |
45 | }; | |
46 | ||
47 | smp-sysram@2f000 { | |
48 | compatible = "samsung,exynos4210-sysram-ns"; | |
49 | reg = <0x2f000 0x1000>; | |
50 | }; | |
51 | }; | |
52 | ||
2ab9f3c0 SN |
53 | pd_isp: isp-power-domain@10023CA0 { |
54 | compatible = "samsung,exynos4210-pd"; | |
55 | reg = <0x10023CA0 0x20>; | |
0da65870 | 56 | #power-domain-cells = <0>; |
64a57434 TF |
57 | }; |
58 | ||
56b60b8b TF |
59 | l2c: l2-cache-controller@10502000 { |
60 | compatible = "arm,pl310-cache"; | |
61 | reg = <0x10502000 0x1000>; | |
62 | cache-unified; | |
63 | cache-level = <2>; | |
64 | arm,tag-latency = <2 2 1>; | |
65 | arm,data-latency = <3 2 1>; | |
66 | arm,double-linefill = <1>; | |
67 | arm,double-linefill-incr = <0>; | |
68 | arm,double-linefill-wrap = <1>; | |
69 | arm,prefetch-drop = <1>; | |
70 | arm,prefetch-offset = <7>; | |
71 | }; | |
72 | ||
1fd9a015 | 73 | clock: clock-controller@10030000 { |
d8bafc87 TA |
74 | compatible = "samsung,exynos4412-clock"; |
75 | reg = <0x10030000 0x20000>; | |
76 | #clock-cells = <1>; | |
77 | }; | |
78 | ||
39e596f0 TF |
79 | mct@10050000 { |
80 | compatible = "samsung,exynos4412-mct"; | |
81 | reg = <0x10050000 0x800>; | |
82 | interrupt-parent = <&mct_map>; | |
84ee1c15 | 83 | interrupts = <0>, <1>, <2>, <3>, <4>; |
1c75a78a | 84 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
39e596f0 TF |
85 | clock-names = "fin_pll", "mct"; |
86 | ||
87 | mct_map: mct-map { | |
84ee1c15 | 88 | #interrupt-cells = <1>; |
39e596f0 TF |
89 | #address-cells = <0>; |
90 | #size-cells = <0>; | |
84ee1c15 TF |
91 | interrupt-map = <0 &gic 0 57 0>, |
92 | <1 &combiner 12 5>, | |
93 | <2 &combiner 12 6>, | |
94 | <3 &combiner 12 7>, | |
95 | <4 &gic 1 12 0>; | |
39e596f0 TF |
96 | }; |
97 | }; | |
98 | ||
8bdfa203 CC |
99 | combiner: interrupt-controller@10440000 { |
100 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | |
101 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
102 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
103 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | |
104 | <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; | |
105 | }; | |
106 | ||
64a57434 | 107 | pinctrl_0: pinctrl@11400000 { |
b533c868 | 108 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
109 | reg = <0x11400000 0x1000>; |
110 | interrupts = <0 47 0>; | |
111 | }; | |
112 | ||
113 | pinctrl_1: pinctrl@11000000 { | |
b533c868 | 114 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
115 | reg = <0x11000000 0x1000>; |
116 | interrupts = <0 46 0>; | |
117 | ||
118 | wakup_eint: wakeup-interrupt-controller { | |
119 | compatible = "samsung,exynos4210-wakeup-eint"; | |
120 | interrupt-parent = <&gic>; | |
121 | interrupts = <0 32 0>; | |
122 | }; | |
123 | }; | |
124 | ||
c63c5743 CC |
125 | adc: adc@126C0000 { |
126 | compatible = "samsung,exynos-adc-v1"; | |
db9bf4d6 | 127 | reg = <0x126C0000 0x100>; |
c63c5743 CC |
128 | interrupt-parent = <&combiner>; |
129 | interrupts = <10 3>; | |
130 | clocks = <&clock CLK_TSADC>; | |
131 | clock-names = "adc"; | |
132 | #io-channel-cells = <1>; | |
133 | io-channel-ranges; | |
db9bf4d6 | 134 | samsung,syscon-phandle = <&pmu_system_controller>; |
c63c5743 CC |
135 | status = "disabled"; |
136 | }; | |
137 | ||
64a57434 | 138 | pinctrl_2: pinctrl@03860000 { |
b533c868 | 139 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
140 | reg = <0x03860000 0x1000>; |
141 | interrupt-parent = <&combiner>; | |
142 | interrupts = <10 0>; | |
143 | }; | |
144 | ||
145 | pinctrl_3: pinctrl@106E0000 { | |
b533c868 | 146 | compatible = "samsung,exynos4x12-pinctrl"; |
64a57434 TF |
147 | reg = <0x106E0000 0x1000>; |
148 | interrupts = <0 72 0>; | |
149 | }; | |
3a0d48f6 | 150 | |
7b9613ac CP |
151 | pmu_system_controller: system-controller@10020000 { |
152 | compatible = "samsung,exynos4212-pmu", "syscon"; | |
d19bb397 TF |
153 | clock-names = "clkout0", "clkout1", "clkout2", "clkout3", |
154 | "clkout4", "clkout8", "clkout9"; | |
155 | clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, | |
156 | <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, | |
157 | <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, | |
158 | <&clock CLK_XUSBXTI>; | |
159 | #clock-cells = <1>; | |
7b9613ac CP |
160 | }; |
161 | ||
3a0d48f6 SK |
162 | g2d@10800000 { |
163 | compatible = "samsung,exynos4212-g2d"; | |
164 | reg = <0x10800000 0x1000>; | |
165 | interrupts = <0 89 0>; | |
1c75a78a | 166 | clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; |
cfc5652d | 167 | clock-names = "sclk_fimg2d", "fimg2d"; |
3a0d48f6 SK |
168 | status = "disabled"; |
169 | }; | |
582435b3 SN |
170 | |
171 | camera { | |
1c75a78a AH |
172 | clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, |
173 | <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; | |
582435b3 SN |
174 | clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; |
175 | ||
176 | fimc_0: fimc@11800000 { | |
177 | compatible = "samsung,exynos4212-fimc"; | |
178 | samsung,pix-limits = <4224 8192 1920 4224>; | |
179 | samsung,mainscaler-ext; | |
180 | samsung,isp-wb; | |
181 | samsung,cam-if; | |
182 | }; | |
183 | ||
184 | fimc_1: fimc@11810000 { | |
185 | compatible = "samsung,exynos4212-fimc"; | |
186 | samsung,pix-limits = <4224 8192 1920 4224>; | |
187 | samsung,mainscaler-ext; | |
188 | samsung,isp-wb; | |
189 | samsung,cam-if; | |
190 | }; | |
191 | ||
192 | fimc_2: fimc@11820000 { | |
193 | compatible = "samsung,exynos4212-fimc"; | |
194 | samsung,pix-limits = <4224 8192 1920 4224>; | |
195 | samsung,mainscaler-ext; | |
196 | samsung,isp-wb; | |
197 | samsung,lcd-wb; | |
198 | samsung,cam-if; | |
199 | }; | |
200 | ||
201 | fimc_3: fimc@11830000 { | |
202 | compatible = "samsung,exynos4212-fimc"; | |
203 | samsung,pix-limits = <1920 8192 1366 1920>; | |
204 | samsung,rotators = <0>; | |
205 | samsung,mainscaler-ext; | |
206 | samsung,isp-wb; | |
207 | samsung,lcd-wb; | |
208 | }; | |
209 | ||
210 | fimc_lite_0: fimc-lite@12390000 { | |
211 | compatible = "samsung,exynos4212-fimc-lite"; | |
212 | reg = <0x12390000 0x1000>; | |
213 | interrupts = <0 105 0>; | |
0da65870 | 214 | power-domains = <&pd_isp>; |
1c75a78a | 215 | clocks = <&clock CLK_FIMC_LITE0>; |
582435b3 SN |
216 | clock-names = "flite"; |
217 | status = "disabled"; | |
218 | }; | |
219 | ||
220 | fimc_lite_1: fimc-lite@123A0000 { | |
221 | compatible = "samsung,exynos4212-fimc-lite"; | |
222 | reg = <0x123A0000 0x1000>; | |
223 | interrupts = <0 106 0>; | |
0da65870 | 224 | power-domains = <&pd_isp>; |
1c75a78a | 225 | clocks = <&clock CLK_FIMC_LITE1>; |
582435b3 SN |
226 | clock-names = "flite"; |
227 | status = "disabled"; | |
228 | }; | |
229 | ||
230 | fimc_is: fimc-is@12000000 { | |
231 | compatible = "samsung,exynos4212-fimc-is", "simple-bus"; | |
232 | reg = <0x12000000 0x260000>; | |
233 | interrupts = <0 90 0>, <0 95 0>; | |
0da65870 | 234 | power-domains = <&pd_isp>; |
1c75a78a AH |
235 | clocks = <&clock CLK_FIMC_LITE0>, |
236 | <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, | |
237 | <&clock CLK_PPMUISPMX>, | |
238 | <&clock CLK_MOUT_MPLL_USER_T>, | |
239 | <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, | |
240 | <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, | |
241 | <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, | |
242 | <&clock CLK_DIV_MCUISP0>, | |
243 | <&clock CLK_DIV_MCUISP1>, | |
79f3c37c | 244 | <&clock CLK_UART_ISP_SCLK>, |
1c75a78a AH |
245 | <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, |
246 | <&clock CLK_ACLK400_MCUISP>, | |
247 | <&clock CLK_DIV_ACLK400_MCUISP>; | |
582435b3 SN |
248 | clock-names = "lite0", "lite1", "ppmuispx", |
249 | "ppmuispmx", "mpll", "isp", | |
250 | "drc", "fd", "mcuisp", | |
251 | "ispdiv0", "ispdiv1", "mcuispdiv0", | |
252 | "mcuispdiv1", "uart", "aclk200", | |
253 | "div_aclk200", "aclk400mcuisp", | |
254 | "div_aclk400mcuisp"; | |
255 | #address-cells = <1>; | |
256 | #size-cells = <1>; | |
257 | ranges; | |
258 | status = "disabled"; | |
259 | ||
260 | pmu { | |
261 | reg = <0x10020000 0x3000>; | |
262 | }; | |
263 | ||
264 | i2c1_isp: i2c-isp@12140000 { | |
265 | compatible = "samsung,exynos4212-i2c-isp"; | |
266 | reg = <0x12140000 0x100>; | |
1c75a78a | 267 | clocks = <&clock CLK_I2C1_ISP>; |
582435b3 SN |
268 | clock-names = "i2c_isp"; |
269 | #address-cells = <1>; | |
270 | #size-cells = <0>; | |
271 | }; | |
272 | }; | |
273 | }; | |
56d52bfb TF |
274 | |
275 | mshc_0: mmc@12550000 { | |
276 | compatible = "samsung,exynos4412-dw-mshc"; | |
277 | reg = <0x12550000 0x1000>; | |
278 | interrupts = <0 77 0>; | |
279 | #address-cells = <1>; | |
280 | #size-cells = <0>; | |
281 | fifo-depth = <0x80>; | |
1c75a78a | 282 | clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; |
56d52bfb TF |
283 | clock-names = "biu", "ciu"; |
284 | status = "disabled"; | |
285 | }; | |
26bbd41f CP |
286 | |
287 | exynos-usbphy@125B0000 { | |
288 | compatible = "samsung,exynos4x12-usb2-phy"; | |
289 | samsung,sysreg-phandle = <&sys_reg>; | |
290 | }; | |
bf61eed9 LM |
291 | |
292 | tmu@100C0000 { | |
293 | compatible = "samsung,exynos4412-tmu"; | |
294 | interrupt-parent = <&combiner>; | |
295 | interrupts = <2 4>; | |
296 | reg = <0x100C0000 0x100>; | |
297 | clocks = <&clock 383>; | |
298 | clock-names = "tmu_apbif"; | |
299 | status = "disabled"; | |
300 | }; | |
0f7238a1 | 301 | }; |