[deliverable/linux.git] / arch / arm / boot / dts / exynos4x12.dtsi

/*
 * Samsung's Exynos4x12 SoCs device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4x12-pinctrl.dtsi"
#include "exynos4-cpu-thermal.dtsi"

/ {
	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		fimc-lite0 = &fimc_lite_0;
		fimc-lite1 = &fimc_lite_1;
		mshc0 = &mshc_0;
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x40000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x40000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@2f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x2f000 0x1000>;
		};
	};

	pd_isp: isp-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
		#power-domain-cells = <0>;
	};

	l2c: l2-cache-controller@10502000 {
		compatible = "arm,pl310-cache";
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <3 2 1>;
		arm,double-linefill = <1>;
		arm,double-linefill-incr = <0>;
		arm,double-linefill-wrap = <1>;
		arm,prefetch-drop = <1>;
		arm,prefetch-offset = <7>;
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4412-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	mct@10050000 {
		compatible = "samsung,exynos4412-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 0>,
					<1 &combiner 12 5>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 1 12 0>;
		};
	};

	adc: adc@126C0000 {
		compatible = "samsung,exynos-adc-v1";
		reg = <0x126C0000 0x100>;
		interrupt-parent = <&combiner>;
		interrupts = <10 3>;
		clocks = <&clock CLK_TSADC>;
		clock-names = "adc";
		#io-channel-cells = <1>;
		io-channel-ranges;
		samsung,syscon-phandle = <&pmu_system_controller>;
		status = "disabled";
	};

	g2d: g2d@10800000 {
		compatible = "samsung,exynos4212-g2d";
		reg = <0x10800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		status = "disabled";
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		/* fimc_[0-3] are configured outside, under phandles */
		fimc_lite_0: fimc-lite@12390000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x12390000 0x1000>;
			interrupts = <0 105 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE0>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_lite_1: fimc-lite@123A0000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x123A0000 0x1000>;
			interrupts = <0 106 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE1>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_is: fimc-is@12000000 {
			compatible = "samsung,exynos4212-fimc-is", "simple-bus";
			reg = <0x12000000 0x260000>;
			interrupts = <0 90 0>, <0 95 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE0>,
				 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
				 <&clock CLK_PPMUISPMX>,
				 <&clock CLK_MOUT_MPLL_USER_T>,
				 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
				 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
				 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
				 <&clock CLK_DIV_MCUISP0>,
				 <&clock CLK_DIV_MCUISP1>,
				 <&clock CLK_UART_ISP_SCLK>,
				 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
				 <&clock CLK_ACLK400_MCUISP>,
				 <&clock CLK_DIV_ACLK400_MCUISP>;
			clock-names = "lite0", "lite1", "ppmuispx",
				      "ppmuispmx", "mpll", "isp",
				      "drc", "fd", "mcuisp",
				      "ispdiv0", "ispdiv1", "mcuispdiv0",
				      "mcuispdiv1", "uart", "aclk200",
				      "div_aclk200", "aclk400mcuisp",
				      "div_aclk400mcuisp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			pmu {
				reg = <0x10020000 0x3000>;
			};

			i2c1_isp: i2c-isp@12140000 {
				compatible = "samsung,exynos4212-i2c-isp";
				reg = <0x12140000 0x100>;
				clocks = <&clock CLK_I2C1_ISP>;
				clock-names = "i2c_isp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};

	mshc_0: mmc@12550000 {
		compatible = "samsung,exynos4412-dw-mshc";
		reg = <0x12550000 0x1000>;
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		fifo-depth = <0x80>;
		clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
		clock-names = "biu", "ciu";
		status = "disabled";
	};
};

&combiner {
	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
		     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
		     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
		     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
		     <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};

&exynos_usbphy {
	compatible = "samsung,exynos4x12-usb2-phy";
	samsung,sysreg-phandle = <&sys_reg>;
};

&fimc_0 {
	compatible = "samsung,exynos4212-fimc";
	samsung,pix-limits = <4224 8192 1920 4224>;
	samsung,mainscaler-ext;
	samsung,isp-wb;
	samsung,cam-if;
};

&fimc_1 {
	compatible = "samsung,exynos4212-fimc";
	samsung,pix-limits = <4224 8192 1920 4224>;
	samsung,mainscaler-ext;
	samsung,isp-wb;
	samsung,cam-if;
};

&fimc_2 {
	compatible = "samsung,exynos4212-fimc";
	samsung,pix-limits = <4224 8192 1920 4224>;
	samsung,mainscaler-ext;
	samsung,isp-wb;
	samsung,lcd-wb;
	samsung,cam-if;
};

&fimc_3 {
	compatible = "samsung,exynos4212-fimc";
	samsung,pix-limits = <1920 8192 1366 1920>;
	samsung,rotators = <0>;
	samsung,mainscaler-ext;
	samsung,isp-wb;
	samsung,lcd-wb;
};

&hdmi {
	compatible = "samsung,exynos4212-hdmi";
};

&jpeg_codec {
	compatible = "samsung,exynos4212-jpeg";
};

&mixer {
	compatible = "samsung,exynos4212-mixer";
	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
};

&pinctrl_0 {
	compatible = "samsung,exynos4x12-pinctrl";
	reg = <0x11400000 0x1000>;
	interrupts = <0 47 0>;
};

&pinctrl_1 {
	compatible = "samsung,exynos4x12-pinctrl";
	reg = <0x11000000 0x1000>;
	interrupts = <0 46 0>;

	wakup_eint: wakeup-interrupt-controller {
		compatible = "samsung,exynos4210-wakeup-eint";
		interrupt-parent = <&gic>;
		interrupts = <0 32 0>;
	};
};

&pinctrl_2 {
	compatible = "samsung,exynos4x12-pinctrl";
	reg = <0x03860000 0x1000>;
	interrupt-parent = <&combiner>;
	interrupts = <10 0>;
};

&pinctrl_3 {
	compatible = "samsung,exynos4x12-pinctrl";
	reg = <0x106E0000 0x1000>;
	interrupts = <0 72 0>;
};

&pmu_system_controller {
	compatible = "samsung,exynos4212-pmu", "syscon";
	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
			"clkout4", "clkout8", "clkout9";
	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
	#clock-cells = <1>;
};

&tmu {
	compatible = "samsung,exynos4412-tmu";
	interrupt-parent = <&combiner>;
	interrupts = <2 4>;
	reg = <0x100C0000 0x100>;
	clocks = <&clock 383>;
	clock-names = "tmu_apbif";
	status = "disabled";
};
Commit	Line	Data
0f7238a1 TF	1	/*
	2	* Samsung's Exynos4x12 SoCs device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
3799279f PV	20	#include "exynos4.dtsi"
3799279f PV	21	#include "exynos4x12-pinctrl.dtsi"
9843a223	22	#include "exynos4-cpu-thermal.dtsi"
0f7238a1 TF	23
0f7238a1 TF	24	/ {
64a57434 TF	25	aliases {
	26	pinctrl0 = &pinctrl_0;
	27	pinctrl1 = &pinctrl_1;
	28	pinctrl2 = &pinctrl_2;
	29	pinctrl3 = &pinctrl_3;
582435b3 SN	30	fimc-lite0 = &fimc_lite_0;
582435b3 SN	31	fimc-lite1 = &fimc_lite_1;
56d52bfb	32	mshc0 = &mshc_0;
64a57434 TF	33	};
64a57434 TF	34
b3205dea SK	35	sysram@02020000 {
	36	compatible = "mmio-sram";
	37	reg = <0x02020000 0x40000>;
	38	#address-cells = <1>;
	39	#size-cells = <1>;
	40	ranges = <0 0x02020000 0x40000>;
	41
	42	smp-sysram@0 {
	43	compatible = "samsung,exynos4210-sysram";
	44	reg = <0x0 0x1000>;
	45	};
	46
	47	smp-sysram@2f000 {
	48	compatible = "samsung,exynos4210-sysram-ns";
	49	reg = <0x2f000 0x1000>;
	50	};
	51	};
	52
2ab9f3c0 SN	53	pd_isp: isp-power-domain@10023CA0 {
	54	compatible = "samsung,exynos4210-pd";
	55	reg = <0x10023CA0 0x20>;
0da65870	56	#power-domain-cells = <0>;
64a57434 TF	57	};
64a57434 TF	58
56b60b8b TF	59	l2c: l2-cache-controller@10502000 {
	60	compatible = "arm,pl310-cache";
	61	reg = <0x10502000 0x1000>;
	62	cache-unified;
	63	cache-level = <2>;
	64	arm,tag-latency = <2 2 1>;
	65	arm,data-latency = <3 2 1>;
	66	arm,double-linefill = <1>;
	67	arm,double-linefill-incr = <0>;
	68	arm,double-linefill-wrap = <1>;
	69	arm,prefetch-drop = <1>;
	70	arm,prefetch-offset = <7>;
	71	};
	72
1fd9a015	73	clock: clock-controller@10030000 {
d8bafc87 TA	74	compatible = "samsung,exynos4412-clock";
	75	reg = <0x10030000 0x20000>;
	76	#clock-cells = <1>;
	77	};
	78
39e596f0 TF	79	mct@10050000 {
	80	compatible = "samsung,exynos4412-mct";
	81	reg = <0x10050000 0x800>;
	82	interrupt-parent = <&mct_map>;
84ee1c15	83	interrupts = <0>, <1>, <2>, <3>, <4>;
1c75a78a	84	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
39e596f0 TF	85	clock-names = "fin_pll", "mct";
	86
	87	mct_map: mct-map {
84ee1c15	88	#interrupt-cells = <1>;
39e596f0 TF	89	#address-cells = <0>;
39e596f0 TF	90	#size-cells = <0>;
84ee1c15 TF	91	interrupt-map = <0 &gic 0 57 0>,
	92	<1 &combiner 12 5>,
	93	<2 &combiner 12 6>,
	94	<3 &combiner 12 7>,
	95	<4 &gic 1 12 0>;
39e596f0 TF	96	};
	97	};
	98
c63c5743 CC	99	adc: adc@126C0000 {
c63c5743 CC	100	compatible = "samsung,exynos-adc-v1";
db9bf4d6	101	reg = <0x126C0000 0x100>;
c63c5743 CC	102	interrupt-parent = <&combiner>;
	103	interrupts = <10 3>;
	104	clocks = <&clock CLK_TSADC>;
	105	clock-names = "adc";
	106	#io-channel-cells = <1>;
	107	io-channel-ranges;
db9bf4d6	108	samsung,syscon-phandle = <&pmu_system_controller>;
c63c5743 CC	109	status = "disabled";
	110	};
	111
9c41221e	112	g2d: g2d@10800000 {
3a0d48f6 SK	113	compatible = "samsung,exynos4212-g2d";
	114	reg = <0x10800000 0x1000>;
	115	interrupts = <0 89 0>;
1c75a78a	116	clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
cfc5652d	117	clock-names = "sclk_fimg2d", "fimg2d";
3a0d48f6 SK	118	status = "disabled";
3a0d48f6 SK	119	};
582435b3 SN	120
582435b3 SN	121	camera {
1c75a78a AH	122	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
1c75a78a AH	123	<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
582435b3 SN	124	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
582435b3 SN	125
13a866d4	126	/* fimc_[0-3] are configured outside, under phandles */
582435b3 SN	127	fimc_lite_0: fimc-lite@12390000 {
	128	compatible = "samsung,exynos4212-fimc-lite";
	129	reg = <0x12390000 0x1000>;
	130	interrupts = <0 105 0>;
0da65870	131	power-domains = <&pd_isp>;
1c75a78a	132	clocks = <&clock CLK_FIMC_LITE0>;
582435b3 SN	133	clock-names = "flite";
	134	status = "disabled";
	135	};
	136
	137	fimc_lite_1: fimc-lite@123A0000 {
	138	compatible = "samsung,exynos4212-fimc-lite";
	139	reg = <0x123A0000 0x1000>;
	140	interrupts = <0 106 0>;
0da65870	141	power-domains = <&pd_isp>;
1c75a78a	142	clocks = <&clock CLK_FIMC_LITE1>;
582435b3 SN	143	clock-names = "flite";
	144	status = "disabled";
	145	};
	146
	147	fimc_is: fimc-is@12000000 {
	148	compatible = "samsung,exynos4212-fimc-is", "simple-bus";
	149	reg = <0x12000000 0x260000>;
	150	interrupts = <0 90 0>, <0 95 0>;
0da65870	151	power-domains = <&pd_isp>;
1c75a78a AH	152	clocks = <&clock CLK_FIMC_LITE0>,
	153	<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
	154	<&clock CLK_PPMUISPMX>,
	155	<&clock CLK_MOUT_MPLL_USER_T>,
	156	<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
	157	<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
	158	<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
	159	<&clock CLK_DIV_MCUISP0>,
	160	<&clock CLK_DIV_MCUISP1>,
79f3c37c	161	<&clock CLK_UART_ISP_SCLK>,
1c75a78a AH	162	<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
	163	<&clock CLK_ACLK400_MCUISP>,
	164	<&clock CLK_DIV_ACLK400_MCUISP>;
582435b3 SN	165	clock-names = "lite0", "lite1", "ppmuispx",
	166	"ppmuispmx", "mpll", "isp",
	167	"drc", "fd", "mcuisp",
	168	"ispdiv0", "ispdiv1", "mcuispdiv0",
	169	"mcuispdiv1", "uart", "aclk200",
	170	"div_aclk200", "aclk400mcuisp",
	171	"div_aclk400mcuisp";
	172	#address-cells = <1>;
	173	#size-cells = <1>;
	174	ranges;
	175	status = "disabled";
	176
	177	pmu {
	178	reg = <0x10020000 0x3000>;
	179	};
	180
	181	i2c1_isp: i2c-isp@12140000 {
	182	compatible = "samsung,exynos4212-i2c-isp";
	183	reg = <0x12140000 0x100>;
1c75a78a	184	clocks = <&clock CLK_I2C1_ISP>;
582435b3 SN	185	clock-names = "i2c_isp";
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	};
	189	};
	190	};
56d52bfb TF	191
	192	mshc_0: mmc@12550000 {
	193	compatible = "samsung,exynos4412-dw-mshc";
	194	reg = <0x12550000 0x1000>;
	195	interrupts = <0 77 0>;
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198	fifo-depth = <0x80>;
1c75a78a	199	clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
56d52bfb TF	200	clock-names = "biu", "ciu";
	201	status = "disabled";
	202	};
13a866d4	203	};
26bbd41f	204
13a866d4 KK	205	&combiner {
	206	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
	207	<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
	208	<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
	209	<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
	210	<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
	211	};
bf61eed9	212
13a866d4 KK	213	&exynos_usbphy {
	214	compatible = "samsung,exynos4x12-usb2-phy";
	215	samsung,sysreg-phandle = <&sys_reg>;
	216	};
ed80d4ca	217
13a866d4 KK	218	&fimc_0 {
	219	compatible = "samsung,exynos4212-fimc";
	220	samsung,pix-limits = <4224 8192 1920 4224>;
	221	samsung,mainscaler-ext;
	222	samsung,isp-wb;
	223	samsung,cam-if;
	224	};
f470b859	225
13a866d4 KK	226	&fimc_1 {
	227	compatible = "samsung,exynos4212-fimc";
	228	samsung,pix-limits = <4224 8192 1920 4224>;
	229	samsung,mainscaler-ext;
	230	samsung,isp-wb;
	231	samsung,cam-if;
	232	};
	233
	234	&fimc_2 {
	235	compatible = "samsung,exynos4212-fimc";
	236	samsung,pix-limits = <4224 8192 1920 4224>;
	237	samsung,mainscaler-ext;
	238	samsung,isp-wb;
	239	samsung,lcd-wb;
	240	samsung,cam-if;
	241	};
	242
	243	&fimc_3 {
	244	compatible = "samsung,exynos4212-fimc";
	245	samsung,pix-limits = <1920 8192 1366 1920>;
	246	samsung,rotators = <0>;
	247	samsung,mainscaler-ext;
	248	samsung,isp-wb;
	249	samsung,lcd-wb;
	250	};
	251
	252	&hdmi {
	253	compatible = "samsung,exynos4212-hdmi";
	254	};
	255
	256	&jpeg_codec {
	257	compatible = "samsung,exynos4212-jpeg";
	258	};
	259
	260	&mixer {
	261	compatible = "samsung,exynos4212-mixer";
	262	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
	263	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
	264	<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
	265	};
ed80d4ca	266
13a866d4 KK	267	&pinctrl_0 {
	268	compatible = "samsung,exynos4x12-pinctrl";
	269	reg = <0x11400000 0x1000>;
	270	interrupts = <0 47 0>;
	271	};
	272
	273	&pinctrl_1 {
	274	compatible = "samsung,exynos4x12-pinctrl";
	275	reg = <0x11000000 0x1000>;
	276	interrupts = <0 46 0>;
	277
	278	wakup_eint: wakeup-interrupt-controller {
	279	compatible = "samsung,exynos4210-wakeup-eint";
	280	interrupt-parent = <&gic>;
	281	interrupts = <0 32 0>;
ed80d4ca	282	};
0f7238a1	283	};
13a866d4 KK	284
	285	&pinctrl_2 {
	286	compatible = "samsung,exynos4x12-pinctrl";
	287	reg = <0x03860000 0x1000>;
	288	interrupt-parent = <&combiner>;
	289	interrupts = <10 0>;
	290	};
	291
	292	&pinctrl_3 {
	293	compatible = "samsung,exynos4x12-pinctrl";
	294	reg = <0x106E0000 0x1000>;
	295	interrupts = <0 72 0>;
	296	};
	297
	298	&pmu_system_controller {
	299	compatible = "samsung,exynos4212-pmu", "syscon";
	300	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
	301	"clkout4", "clkout8", "clkout9";
	302	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
	303	<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
	304	<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
	305	#clock-cells = <1>;
	306	};
	307
	308	&tmu {
	309	compatible = "samsung,exynos4412-tmu";
	310	interrupt-parent = <&combiner>;
	311	interrupts = <2 4>;
	312	reg = <0x100C0000 0x100>;
	313	clocks = <&clock 383>;
	314	clock-names = "tmu_apbif";
	315	status = "disabled";
	316	};