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1 | /* |
2 | * Samsung's Exynos5 SoC series common device tree source | |
3 | * | |
4 | * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular | |
8 | * SoCs from Exynos5 series can include this file and provide values for SoCs | |
9 | * specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
1462b137 | 16 | #include "exynos-syscon-restart.dtsi" |
e6c21cba CK |
17 | |
18 | / { | |
19 | interrupt-parent = <&gic>; | |
12676ee1 JMC |
20 | #address-cells = <1>; |
21 | #size-cells = <1>; | |
e6c21cba | 22 | |
1e64f48e | 23 | aliases { |
5a124fe0 KK |
24 | i2c0 = &i2c_0; |
25 | i2c1 = &i2c_1; | |
26 | i2c2 = &i2c_2; | |
27 | i2c3 = &i2c_3; | |
1e64f48e TF |
28 | serial0 = &serial_0; |
29 | serial1 = &serial_1; | |
30 | serial2 = &serial_2; | |
31 | serial3 = &serial_3; | |
32 | }; | |
33 | ||
5d99cc59 KK |
34 | soc: soc { |
35 | compatible = "simple-bus"; | |
77899d53 | 36 | #address-cells = <1>; |
5d99cc59 KK |
37 | #size-cells = <1>; |
38 | ranges; | |
39 | ||
40 | chipid@10000000 { | |
41 | compatible = "samsung,exynos4210-chipid"; | |
42 | reg = <0x10000000 0x100>; | |
43 | }; | |
44 | ||
45 | sromc: memory-controller@12250000 { | |
46 | compatible = "samsung,exynos4210-srom"; | |
47 | reg = <0x12250000 0x14>; | |
48 | }; | |
49 | ||
50 | combiner: interrupt-controller@10440000 { | |
51 | compatible = "samsung,exynos4210-combiner"; | |
52 | #interrupt-cells = <2>; | |
53 | interrupt-controller; | |
54 | samsung,combiner-nr = <32>; | |
55 | reg = <0x10440000 0x1000>; | |
56 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | |
57 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
58 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
59 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | |
60 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | |
61 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, | |
62 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, | |
63 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | |
64 | }; | |
65 | ||
66 | gic: interrupt-controller@10481000 { | |
67 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
68 | #interrupt-cells = <3>; | |
69 | interrupt-controller; | |
70 | reg = <0x10481000 0x1000>, | |
71 | <0x10482000 0x1000>, | |
72 | <0x10484000 0x2000>, | |
73 | <0x10486000 0x2000>; | |
74 | interrupts = <1 9 0xf04>; | |
75 | }; | |
76 | ||
77 | sysreg_system_controller: syscon@10050000 { | |
78 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
79 | reg = <0x10050000 0x5000>; | |
80 | }; | |
81 | ||
82 | serial_0: serial@12C00000 { | |
83 | compatible = "samsung,exynos4210-uart"; | |
84 | reg = <0x12C00000 0x100>; | |
85 | interrupts = <0 51 0>; | |
86 | }; | |
87 | ||
88 | serial_1: serial@12C10000 { | |
89 | compatible = "samsung,exynos4210-uart"; | |
90 | reg = <0x12C10000 0x100>; | |
91 | interrupts = <0 52 0>; | |
92 | }; | |
93 | ||
94 | serial_2: serial@12C20000 { | |
95 | compatible = "samsung,exynos4210-uart"; | |
96 | reg = <0x12C20000 0x100>; | |
97 | interrupts = <0 53 0>; | |
98 | }; | |
99 | ||
100 | serial_3: serial@12C30000 { | |
101 | compatible = "samsung,exynos4210-uart"; | |
102 | reg = <0x12C30000 0x100>; | |
103 | interrupts = <0 54 0>; | |
104 | }; | |
105 | ||
106 | i2c_0: i2c@12C60000 { | |
107 | compatible = "samsung,s3c2440-i2c"; | |
108 | reg = <0x12C60000 0x100>; | |
109 | interrupts = <0 56 0>; | |
110 | #address-cells = <1>; | |
111 | #size-cells = <0>; | |
112 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
113 | status = "disabled"; | |
114 | }; | |
115 | ||
116 | i2c_1: i2c@12C70000 { | |
117 | compatible = "samsung,s3c2440-i2c"; | |
118 | reg = <0x12C70000 0x100>; | |
119 | interrupts = <0 57 0>; | |
120 | #address-cells = <1>; | |
121 | #size-cells = <0>; | |
122 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | i2c_2: i2c@12C80000 { | |
127 | compatible = "samsung,s3c2440-i2c"; | |
128 | reg = <0x12C80000 0x100>; | |
129 | interrupts = <0 58 0>; | |
130 | #address-cells = <1>; | |
131 | #size-cells = <0>; | |
132 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
133 | status = "disabled"; | |
134 | }; | |
135 | ||
136 | i2c_3: i2c@12C90000 { | |
137 | compatible = "samsung,s3c2440-i2c"; | |
138 | reg = <0x12C90000 0x100>; | |
139 | interrupts = <0 59 0>; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <0>; | |
142 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
143 | status = "disabled"; | |
144 | }; | |
145 | ||
146 | pwm: pwm@12DD0000 { | |
147 | compatible = "samsung,exynos4210-pwm"; | |
148 | reg = <0x12DD0000 0x100>; | |
149 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
150 | #pwm-cells = <3>; | |
151 | }; | |
152 | ||
153 | rtc: rtc@101E0000 { | |
154 | compatible = "samsung,s3c6410-rtc"; | |
155 | reg = <0x101E0000 0x100>; | |
156 | interrupts = <0 43 0>, <0 44 0>; | |
157 | status = "disabled"; | |
158 | }; | |
159 | ||
160 | fimd: fimd@14400000 { | |
161 | compatible = "samsung,exynos5250-fimd"; | |
162 | interrupt-parent = <&combiner>; | |
163 | reg = <0x14400000 0x40000>; | |
164 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
165 | interrupts = <18 4>, <18 5>, <18 6>; | |
166 | samsung,sysreg = <&sysreg_system_controller>; | |
167 | status = "disabled"; | |
168 | }; | |
169 | ||
170 | dp: dp-controller@145B0000 { | |
171 | compatible = "samsung,exynos5-dp"; | |
172 | reg = <0x145B0000 0x1000>; | |
173 | interrupts = <10 3>; | |
174 | interrupt-parent = <&combiner>; | |
175 | #address-cells = <1>; | |
176 | #size-cells = <0>; | |
177 | status = "disabled"; | |
178 | }; | |
77899d53 | 179 | }; |
e6c21cba | 180 | }; |