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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
9843a223 | 22 | #include "exynos4-cpu-thermal.dtsi" |
602408e3 | 23 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
24 | |
25 | / { | |
8bdb31b4 | 26 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 27 | |
79989ba3 TA |
28 | aliases { |
29 | spi0 = &spi_0; | |
30 | spi1 = &spi_1; | |
31 | spi2 = &spi_2; | |
1128658a SAB |
32 | gsc0 = &gsc_0; |
33 | gsc1 = &gsc_1; | |
34 | gsc2 = &gsc_2; | |
35 | gsc3 = &gsc_3; | |
c8149df0 YK |
36 | mshc0 = &mmc_0; |
37 | mshc1 = &mmc_1; | |
38 | mshc2 = &mmc_2; | |
39 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
40 | i2c0 = &i2c_0; |
41 | i2c1 = &i2c_1; | |
42 | i2c2 = &i2c_2; | |
43 | i2c3 = &i2c_3; | |
44 | i2c4 = &i2c_4; | |
45 | i2c5 = &i2c_5; | |
46 | i2c6 = &i2c_6; | |
47 | i2c7 = &i2c_7; | |
48 | i2c8 = &i2c_8; | |
ba0d7ed3 | 49 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
50 | pinctrl0 = &pinctrl_0; |
51 | pinctrl1 = &pinctrl_1; | |
52 | pinctrl2 = &pinctrl_2; | |
53 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
54 | }; |
55 | ||
1897d2f3 CK |
56 | cpus { |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | ||
bf4a0bed | 60 | cpu0: cpu@0 { |
1897d2f3 CK |
61 | device_type = "cpu"; |
62 | compatible = "arm,cortex-a15"; | |
63 | reg = <0>; | |
0da80563 | 64 | clock-frequency = <1700000000>; |
846c5300 TA |
65 | clocks = <&clock CLK_ARM_CLK>; |
66 | clock-names = "cpu"; | |
67 | clock-latency = <140000>; | |
68 | ||
69 | operating-points = < | |
70 | 1700000 1300000 | |
71 | 1600000 1250000 | |
72 | 1500000 1225000 | |
73 | 1400000 1200000 | |
74 | 1300000 1150000 | |
75 | 1200000 1125000 | |
76 | 1100000 1100000 | |
77 | 1000000 1075000 | |
78 | 900000 1050000 | |
79 | 800000 1025000 | |
80 | 700000 1012500 | |
81 | 600000 1000000 | |
82 | 500000 975000 | |
83 | 400000 950000 | |
84 | 300000 937500 | |
85 | 200000 925000 | |
86 | >; | |
bf4a0bed LM |
87 | cooling-min-level = <15>; |
88 | cooling-max-level = <9>; | |
89 | #cooling-cells = <2>; /* min followed by max */ | |
1897d2f3 CK |
90 | }; |
91 | cpu@1 { | |
92 | device_type = "cpu"; | |
93 | compatible = "arm,cortex-a15"; | |
94 | reg = <1>; | |
0da80563 | 95 | clock-frequency = <1700000000>; |
1897d2f3 | 96 | }; |
79989ba3 TA |
97 | }; |
98 | ||
b3205dea SK |
99 | sysram@02020000 { |
100 | compatible = "mmio-sram"; | |
101 | reg = <0x02020000 0x30000>; | |
102 | #address-cells = <1>; | |
103 | #size-cells = <1>; | |
104 | ranges = <0 0x02020000 0x30000>; | |
105 | ||
106 | smp-sysram@0 { | |
107 | compatible = "samsung,exynos4210-sysram"; | |
108 | reg = <0x0 0x1000>; | |
109 | }; | |
110 | ||
111 | smp-sysram@2f000 { | |
112 | compatible = "samsung,exynos4210-sysram-ns"; | |
113 | reg = <0x2f000 0x1000>; | |
114 | }; | |
115 | }; | |
116 | ||
c31f566d | 117 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
118 | compatible = "samsung,exynos4210-pd"; |
119 | reg = <0x10044000 0x20>; | |
0da65870 | 120 | #power-domain-cells = <0>; |
6f9e95e6 PK |
121 | }; |
122 | ||
c31f566d | 123 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
124 | compatible = "samsung,exynos4210-pd"; |
125 | reg = <0x10044040 0x20>; | |
0da65870 | 126 | #power-domain-cells = <0>; |
6f9e95e6 PK |
127 | }; |
128 | ||
2d2c9a8d AH |
129 | pd_disp1: disp1-power-domain@100440A0 { |
130 | compatible = "samsung,exynos4210-pd"; | |
131 | reg = <0x100440A0 0x20>; | |
132 | #power-domain-cells = <0>; | |
69636a85 TV |
133 | clocks = <&clock CLK_FIN_PLL>, |
134 | <&clock CLK_MOUT_ACLK200_DISP1_SUB>, | |
135 | <&clock CLK_MOUT_ACLK300_DISP1_SUB>; | |
136 | clock-names = "oscclk", "clk0", "clk1"; | |
2d2c9a8d AH |
137 | }; |
138 | ||
c31f566d | 139 | clock: clock-controller@10010000 { |
d8bafc87 TA |
140 | compatible = "samsung,exynos5250-clock"; |
141 | reg = <0x10010000 0x30000>; | |
142 | #clock-cells = <1>; | |
143 | }; | |
144 | ||
bba23d95 PV |
145 | clock_audss: audss-clock-controller@3810000 { |
146 | compatible = "samsung,exynos5250-audss-clock"; | |
147 | reg = <0x03810000 0x0C>; | |
148 | #clock-cells = <1>; | |
fe273c3e AH |
149 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
150 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 151 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
152 | }; |
153 | ||
2b7da988 AG |
154 | timer { |
155 | compatible = "arm,armv7-timer"; | |
156 | interrupts = <1 13 0xf08>, | |
157 | <1 14 0xf08>, | |
158 | <1 11 0xf08>, | |
159 | <1 10 0xf08>; | |
4d594dd3 YK |
160 | /* Unfortunately we need this since some versions of U-Boot |
161 | * on Exynos don't set the CNTFRQ register, so we need the | |
162 | * value from DT. | |
163 | */ | |
164 | clock-frequency = <24000000>; | |
b074abb7 KK |
165 | }; |
166 | ||
bbd9700a TA |
167 | mct@101C0000 { |
168 | compatible = "samsung,exynos4210-mct"; | |
169 | reg = <0x101C0000 0x800>; | |
170 | interrupt-controller; | |
f27b9075 | 171 | #interrupt-cells = <2>; |
bbd9700a TA |
172 | interrupt-parent = <&mct_map>; |
173 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
174 | <4 0>, <5 0>; | |
fe273c3e | 175 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 176 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
177 | |
178 | mct_map: mct-map { | |
179 | #interrupt-cells = <2>; | |
180 | #address-cells = <0>; | |
181 | #size-cells = <0>; | |
182 | interrupt-map = <0x0 0 &combiner 23 3>, | |
183 | <0x1 0 &combiner 23 4>, | |
184 | <0x2 0 &combiner 25 2>, | |
185 | <0x3 0 &combiner 25 3>, | |
186 | <0x4 0 &gic 0 120 0>, | |
187 | <0x5 0 &gic 0 121 0>; | |
188 | }; | |
189 | }; | |
190 | ||
4f801e59 CP |
191 | pmu { |
192 | compatible = "arm,cortex-a15-pmu"; | |
193 | interrupt-parent = <&combiner>; | |
194 | interrupts = <1 2>, <22 4>; | |
195 | }; | |
196 | ||
f8bfe2b0 TA |
197 | pinctrl_0: pinctrl@11400000 { |
198 | compatible = "samsung,exynos5250-pinctrl"; | |
199 | reg = <0x11400000 0x1000>; | |
200 | interrupts = <0 46 0>; | |
201 | ||
202 | wakup_eint: wakeup-interrupt-controller { | |
203 | compatible = "samsung,exynos4210-wakeup-eint"; | |
204 | interrupt-parent = <&gic>; | |
205 | interrupts = <0 32 0>; | |
206 | }; | |
207 | }; | |
208 | ||
209 | pinctrl_1: pinctrl@13400000 { | |
210 | compatible = "samsung,exynos5250-pinctrl"; | |
211 | reg = <0x13400000 0x1000>; | |
212 | interrupts = <0 45 0>; | |
213 | }; | |
214 | ||
215 | pinctrl_2: pinctrl@10d10000 { | |
216 | compatible = "samsung,exynos5250-pinctrl"; | |
217 | reg = <0x10d10000 0x1000>; | |
218 | interrupts = <0 50 0>; | |
219 | }; | |
220 | ||
0abb6aea | 221 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 222 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 223 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
224 | interrupts = <0 47 0>; |
225 | }; | |
226 | ||
c680036a LKA |
227 | pmu_system_controller: system-controller@10040000 { |
228 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
229 | reg = <0x10040000 0x5000>; | |
d19bb397 TF |
230 | clock-names = "clkout16"; |
231 | clocks = <&clock CLK_FIN_PLL>; | |
232 | #clock-cells = <1>; | |
8b283c02 MZ |
233 | interrupt-controller; |
234 | #interrupt-cells = <3>; | |
235 | interrupt-parent = <&gic>; | |
c680036a LKA |
236 | }; |
237 | ||
dfbbdbf4 VG |
238 | sysreg_system_controller: syscon@10050000 { |
239 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
240 | reg = <0x10050000 0x5000>; | |
241 | }; | |
242 | ||
1d287620 LKA |
243 | watchdog@101D0000 { |
244 | compatible = "samsung,exynos5250-wdt"; | |
245 | reg = <0x101D0000 0x100>; | |
246 | interrupts = <0 42 0>; | |
fe273c3e | 247 | clocks = <&clock CLK_WDT>; |
2de6847c | 248 | clock-names = "watchdog"; |
1d287620 | 249 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
250 | }; |
251 | ||
21aa5217 SK |
252 | g2d@10850000 { |
253 | compatible = "samsung,exynos5250-g2d"; | |
254 | reg = <0x10850000 0x1000>; | |
255 | interrupts = <0 91 0>; | |
fe273c3e | 256 | clocks = <&clock CLK_G2D>; |
21aa5217 | 257 | clock-names = "fimg2d"; |
6cbfdd73 | 258 | iommus = <&sysmmu_g2d>; |
21aa5217 SK |
259 | }; |
260 | ||
19fd45bf | 261 | mfc: codec@11000000 { |
2eae613b AK |
262 | compatible = "samsung,mfc-v6"; |
263 | reg = <0x11000000 0x10000>; | |
264 | interrupts = <0 96 0>; | |
0da65870 | 265 | power-domains = <&pd_mfc>; |
fe273c3e | 266 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 267 | clock-names = "mfc"; |
6cbfdd73 MS |
268 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; |
269 | iommu-names = "left", "right"; | |
2eae613b AK |
270 | }; |
271 | ||
9843a223 | 272 | tmu: tmu@10060000 { |
ef405e04 ADK |
273 | compatible = "samsung,exynos5250-tmu"; |
274 | reg = <0x10060000 0x100>; | |
275 | interrupts = <0 65 0>; | |
fe273c3e | 276 | clocks = <&clock CLK_TMU>; |
2de6847c | 277 | clock-names = "tmu_apbif"; |
9843a223 | 278 | #include "exynos4412-tmu-sensor-conf.dtsi" |
ef405e04 ADK |
279 | }; |
280 | ||
bf4a0bed LM |
281 | thermal-zones { |
282 | cpu_thermal: cpu-thermal { | |
9843a223 LM |
283 | polling-delay-passive = <0>; |
284 | polling-delay = <0>; | |
285 | thermal-sensors = <&tmu 0>; | |
286 | ||
bf4a0bed LM |
287 | cooling-maps { |
288 | map0 { | |
289 | /* Corresponds to 800MHz at freq_table */ | |
290 | cooling-device = <&cpu0 9 9>; | |
291 | }; | |
292 | map1 { | |
293 | /* Corresponds to 200MHz at freq_table */ | |
294 | cooling-device = <&cpu0 15 15>; | |
295 | }; | |
296 | }; | |
297 | }; | |
298 | }; | |
299 | ||
19fd45bf | 300 | sata: sata@122F0000 { |
ba0d7ed3 YK |
301 | compatible = "snps,dwc-ahci"; |
302 | samsung,sata-freq = <66>; | |
c47d244a VA |
303 | reg = <0x122F0000 0x1ff>; |
304 | interrupts = <0 115 0>; | |
fe273c3e | 305 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 306 | clock-names = "sata", "sclk_sata"; |
ba0d7ed3 YK |
307 | phys = <&sata_phy>; |
308 | phy-names = "sata-phy"; | |
309 | status = "disabled"; | |
c47d244a VA |
310 | }; |
311 | ||
ba0d7ed3 YK |
312 | sata_phy: sata-phy@12170000 { |
313 | compatible = "samsung,exynos5250-sata-phy"; | |
c47d244a | 314 | reg = <0x12170000 0x1ff>; |
e06e1067 | 315 | clocks = <&clock CLK_SATA_PHYCTRL>; |
ba0d7ed3 YK |
316 | clock-names = "sata_phyctrl"; |
317 | #phy-cells = <0>; | |
318 | samsung,syscon-phandle = <&pmu_system_controller>; | |
319 | status = "disabled"; | |
c47d244a VA |
320 | }; |
321 | ||
b9fa3e7b | 322 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
323 | compatible = "samsung,s3c2440-i2c"; |
324 | reg = <0x12C60000 0x100>; | |
325 | interrupts = <0 56 0>; | |
009f7c9f TA |
326 | #address-cells = <1>; |
327 | #size-cells = <0>; | |
fe273c3e | 328 | clocks = <&clock CLK_I2C0>; |
2de6847c | 329 | clock-names = "i2c"; |
f8bfe2b0 TA |
330 | pinctrl-names = "default"; |
331 | pinctrl-0 = <&i2c0_bus>; | |
1888eb75 | 332 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 333 | status = "disabled"; |
b074abb7 KK |
334 | }; |
335 | ||
b9fa3e7b | 336 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
337 | compatible = "samsung,s3c2440-i2c"; |
338 | reg = <0x12C70000 0x100>; | |
339 | interrupts = <0 57 0>; | |
009f7c9f TA |
340 | #address-cells = <1>; |
341 | #size-cells = <0>; | |
fe273c3e | 342 | clocks = <&clock CLK_I2C1>; |
2de6847c | 343 | clock-names = "i2c"; |
f8bfe2b0 TA |
344 | pinctrl-names = "default"; |
345 | pinctrl-0 = <&i2c1_bus>; | |
1888eb75 | 346 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 347 | status = "disabled"; |
b074abb7 KK |
348 | }; |
349 | ||
b9fa3e7b | 350 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
351 | compatible = "samsung,s3c2440-i2c"; |
352 | reg = <0x12C80000 0x100>; | |
353 | interrupts = <0 58 0>; | |
009f7c9f TA |
354 | #address-cells = <1>; |
355 | #size-cells = <0>; | |
fe273c3e | 356 | clocks = <&clock CLK_I2C2>; |
2de6847c | 357 | clock-names = "i2c"; |
f8bfe2b0 TA |
358 | pinctrl-names = "default"; |
359 | pinctrl-0 = <&i2c2_bus>; | |
1888eb75 | 360 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 361 | status = "disabled"; |
b074abb7 KK |
362 | }; |
363 | ||
b9fa3e7b | 364 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
365 | compatible = "samsung,s3c2440-i2c"; |
366 | reg = <0x12C90000 0x100>; | |
367 | interrupts = <0 59 0>; | |
009f7c9f TA |
368 | #address-cells = <1>; |
369 | #size-cells = <0>; | |
fe273c3e | 370 | clocks = <&clock CLK_I2C3>; |
2de6847c | 371 | clock-names = "i2c"; |
f8bfe2b0 TA |
372 | pinctrl-names = "default"; |
373 | pinctrl-0 = <&i2c3_bus>; | |
1888eb75 | 374 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
6ad8ebff | 375 | status = "disabled"; |
b074abb7 KK |
376 | }; |
377 | ||
b9fa3e7b | 378 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
379 | compatible = "samsung,s3c2440-i2c"; |
380 | reg = <0x12CA0000 0x100>; | |
381 | interrupts = <0 60 0>; | |
009f7c9f TA |
382 | #address-cells = <1>; |
383 | #size-cells = <0>; | |
fe273c3e | 384 | clocks = <&clock CLK_I2C4>; |
2de6847c | 385 | clock-names = "i2c"; |
f8bfe2b0 TA |
386 | pinctrl-names = "default"; |
387 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 388 | status = "disabled"; |
b074abb7 KK |
389 | }; |
390 | ||
b9fa3e7b | 391 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
392 | compatible = "samsung,s3c2440-i2c"; |
393 | reg = <0x12CB0000 0x100>; | |
394 | interrupts = <0 61 0>; | |
009f7c9f TA |
395 | #address-cells = <1>; |
396 | #size-cells = <0>; | |
fe273c3e | 397 | clocks = <&clock CLK_I2C5>; |
2de6847c | 398 | clock-names = "i2c"; |
f8bfe2b0 TA |
399 | pinctrl-names = "default"; |
400 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 401 | status = "disabled"; |
b074abb7 KK |
402 | }; |
403 | ||
b9fa3e7b | 404 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
405 | compatible = "samsung,s3c2440-i2c"; |
406 | reg = <0x12CC0000 0x100>; | |
407 | interrupts = <0 62 0>; | |
009f7c9f TA |
408 | #address-cells = <1>; |
409 | #size-cells = <0>; | |
fe273c3e | 410 | clocks = <&clock CLK_I2C6>; |
2de6847c | 411 | clock-names = "i2c"; |
f8bfe2b0 TA |
412 | pinctrl-names = "default"; |
413 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 414 | status = "disabled"; |
b074abb7 KK |
415 | }; |
416 | ||
b9fa3e7b | 417 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
418 | compatible = "samsung,s3c2440-i2c"; |
419 | reg = <0x12CD0000 0x100>; | |
420 | interrupts = <0 63 0>; | |
009f7c9f TA |
421 | #address-cells = <1>; |
422 | #size-cells = <0>; | |
fe273c3e | 423 | clocks = <&clock CLK_I2C7>; |
2de6847c | 424 | clock-names = "i2c"; |
f8bfe2b0 TA |
425 | pinctrl-names = "default"; |
426 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 427 | status = "disabled"; |
3e3e9ce4 RS |
428 | }; |
429 | ||
b9fa3e7b | 430 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
431 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
432 | reg = <0x12CE0000 0x1000>; | |
433 | interrupts = <0 64 0>; | |
434 | #address-cells = <1>; | |
435 | #size-cells = <0>; | |
fe273c3e | 436 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 437 | clock-names = "i2c"; |
6ad8ebff | 438 | status = "disabled"; |
24025f6f OJ |
439 | }; |
440 | ||
ba0d7ed3 | 441 | i2c_9: i2c@121D0000 { |
c47d244a VA |
442 | compatible = "samsung,exynos5-sata-phy-i2c"; |
443 | reg = <0x121D0000 0x100>; | |
444 | #address-cells = <1>; | |
445 | #size-cells = <0>; | |
fe273c3e | 446 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 447 | clock-names = "i2c"; |
6ad8ebff | 448 | status = "disabled"; |
b074abb7 KK |
449 | }; |
450 | ||
79989ba3 TA |
451 | spi_0: spi@12d20000 { |
452 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 453 | status = "disabled"; |
79989ba3 TA |
454 | reg = <0x12d20000 0x100>; |
455 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
456 | dmas = <&pdma0 5 |
457 | &pdma0 4>; | |
458 | dma-names = "tx", "rx"; | |
79989ba3 TA |
459 | #address-cells = <1>; |
460 | #size-cells = <0>; | |
fe273c3e | 461 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 462 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
463 | pinctrl-names = "default"; |
464 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
465 | }; |
466 | ||
467 | spi_1: spi@12d30000 { | |
468 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 469 | status = "disabled"; |
79989ba3 TA |
470 | reg = <0x12d30000 0x100>; |
471 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
472 | dmas = <&pdma1 5 |
473 | &pdma1 4>; | |
474 | dma-names = "tx", "rx"; | |
79989ba3 TA |
475 | #address-cells = <1>; |
476 | #size-cells = <0>; | |
fe273c3e | 477 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 478 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
479 | pinctrl-names = "default"; |
480 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
481 | }; |
482 | ||
483 | spi_2: spi@12d40000 { | |
484 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 485 | status = "disabled"; |
79989ba3 TA |
486 | reg = <0x12d40000 0x100>; |
487 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
488 | dmas = <&pdma0 7 |
489 | &pdma0 6>; | |
490 | dma-names = "tx", "rx"; | |
79989ba3 TA |
491 | #address-cells = <1>; |
492 | #size-cells = <0>; | |
fe273c3e | 493 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 494 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
495 | pinctrl-names = "default"; |
496 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
497 | }; |
498 | ||
c8149df0 | 499 | mmc_0: mmc@12200000 { |
906fd84e YK |
500 | compatible = "samsung,exynos5250-dw-mshc"; |
501 | interrupts = <0 75 0>; | |
502 | #address-cells = <1>; | |
503 | #size-cells = <0>; | |
84bd48a0 | 504 | reg = <0x12200000 0x1000>; |
fe273c3e | 505 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 506 | clock-names = "biu", "ciu"; |
46285a90 | 507 | fifo-depth = <0x80>; |
e908d5c5 | 508 | status = "disabled"; |
84bd48a0 TA |
509 | }; |
510 | ||
c8149df0 | 511 | mmc_1: mmc@12210000 { |
906fd84e YK |
512 | compatible = "samsung,exynos5250-dw-mshc"; |
513 | interrupts = <0 76 0>; | |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
84bd48a0 | 516 | reg = <0x12210000 0x1000>; |
fe273c3e | 517 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 518 | clock-names = "biu", "ciu"; |
46285a90 | 519 | fifo-depth = <0x80>; |
e908d5c5 | 520 | status = "disabled"; |
84bd48a0 TA |
521 | }; |
522 | ||
c8149df0 | 523 | mmc_2: mmc@12220000 { |
906fd84e YK |
524 | compatible = "samsung,exynos5250-dw-mshc"; |
525 | interrupts = <0 77 0>; | |
526 | #address-cells = <1>; | |
527 | #size-cells = <0>; | |
84bd48a0 | 528 | reg = <0x12220000 0x1000>; |
fe273c3e | 529 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 530 | clock-names = "biu", "ciu"; |
46285a90 | 531 | fifo-depth = <0x80>; |
e908d5c5 | 532 | status = "disabled"; |
84bd48a0 TA |
533 | }; |
534 | ||
c8149df0 | 535 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
536 | compatible = "samsung,exynos5250-dw-mshc"; |
537 | reg = <0x12230000 0x1000>; | |
538 | interrupts = <0 78 0>; | |
539 | #address-cells = <1>; | |
540 | #size-cells = <0>; | |
fe273c3e | 541 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 542 | clock-names = "biu", "ciu"; |
46285a90 | 543 | fifo-depth = <0x80>; |
e908d5c5 | 544 | status = "disabled"; |
84bd48a0 TA |
545 | }; |
546 | ||
28a48058 | 547 | i2s0: i2s@03830000 { |
64183656 | 548 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 549 | status = "disabled"; |
a0b5f81e | 550 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
551 | dmas = <&pdma0 10 |
552 | &pdma0 9 | |
553 | &pdma0 8>; | |
554 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
555 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
556 | <&clock_audss EXYNOS_I2S_BUS>, | |
557 | <&clock_audss EXYNOS_SCLK_I2S>; | |
558 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 559 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
560 | pinctrl-names = "default"; |
561 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
562 | }; |
563 | ||
28a48058 | 564 | i2s1: i2s@12D60000 { |
64183656 | 565 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 566 | status = "disabled"; |
a0b5f81e MB |
567 | reg = <0x12D60000 0x100>; |
568 | dmas = <&pdma1 12 | |
569 | &pdma1 11>; | |
570 | dma-names = "tx", "rx"; | |
fe273c3e | 571 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 572 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
573 | pinctrl-names = "default"; |
574 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
575 | }; |
576 | ||
28a48058 | 577 | i2s2: i2s@12D70000 { |
64183656 | 578 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 579 | status = "disabled"; |
a0b5f81e MB |
580 | reg = <0x12D70000 0x100>; |
581 | dmas = <&pdma0 12 | |
582 | &pdma0 11>; | |
583 | dma-names = "tx", "rx"; | |
fe273c3e | 584 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 585 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
586 | pinctrl-names = "default"; |
587 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
588 | }; |
589 | ||
0b3dc97e VG |
590 | usb@12000000 { |
591 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 592 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
593 | clock-names = "usbdrd30"; |
594 | #address-cells = <1>; | |
595 | #size-cells = <1>; | |
596 | ranges; | |
597 | ||
0526f276 | 598 | usbdrd_dwc3: dwc3 { |
0b3dc97e VG |
599 | compatible = "synopsys,dwc3"; |
600 | reg = <0x12000000 0x10000>; | |
601 | interrupts = <0 72 0>; | |
7a4cf0fd VG |
602 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
603 | phy-names = "usb2-phy", "usb3-phy"; | |
896db3b3 VG |
604 | }; |
605 | }; | |
606 | ||
517083f4 VG |
607 | usbdrd_phy: phy@12100000 { |
608 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
609 | reg = <0x12100000 0x100>; | |
610 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
611 | clock-names = "phy", "ref"; | |
612 | samsung,pmu-syscon = <&pmu_system_controller>; | |
613 | #phy-cells = <1>; | |
614 | }; | |
615 | ||
19fd45bf | 616 | ehci: usb@12110000 { |
13cbd1e3 VG |
617 | compatible = "samsung,exynos4210-ehci"; |
618 | reg = <0x12110000 0x100>; | |
619 | interrupts = <0 71 0>; | |
b3cd7d87 | 620 | |
fe273c3e | 621 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 622 | clock-names = "usbhost"; |
dba2f058 KD |
623 | #address-cells = <1>; |
624 | #size-cells = <0>; | |
625 | port@0 { | |
626 | reg = <0>; | |
627 | phys = <&usb2_phy_gen 1>; | |
628 | }; | |
13cbd1e3 VG |
629 | }; |
630 | ||
19fd45bf | 631 | ohci: usb@12120000 { |
7d40d867 VG |
632 | compatible = "samsung,exynos4210-ohci"; |
633 | reg = <0x12120000 0x100>; | |
634 | interrupts = <0 71 0>; | |
b3cd7d87 | 635 | |
fe273c3e | 636 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 637 | clock-names = "usbhost"; |
dba2f058 KD |
638 | #address-cells = <1>; |
639 | #size-cells = <0>; | |
640 | port@0 { | |
641 | reg = <0>; | |
642 | phys = <&usb2_phy_gen 1>; | |
643 | }; | |
7d40d867 VG |
644 | }; |
645 | ||
dba2f058 KD |
646 | usb2_phy_gen: phy@12130000 { |
647 | compatible = "samsung,exynos5250-usb2-phy"; | |
648 | reg = <0x12130000 0x100>; | |
649 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
650 | clock-names = "phy", "ref"; | |
651 | #phy-cells = <1>; | |
652 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
653 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
654 | }; | |
655 | ||
022cf308 LKA |
656 | pwm: pwm@12dd0000 { |
657 | compatible = "samsung,exynos4210-pwm"; | |
658 | reg = <0x12dd0000 0x100>; | |
659 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
660 | #pwm-cells = <3>; | |
fe273c3e | 661 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
662 | clock-names = "timers"; |
663 | }; | |
664 | ||
b074abb7 KK |
665 | amba { |
666 | #address-cells = <1>; | |
667 | #size-cells = <1>; | |
668 | compatible = "arm,amba-bus"; | |
669 | interrupt-parent = <&gic>; | |
670 | ranges; | |
671 | ||
672 | pdma0: pdma@121A0000 { | |
673 | compatible = "arm,pl330", "arm,primecell"; | |
674 | reg = <0x121A0000 0x1000>; | |
675 | interrupts = <0 34 0>; | |
fe273c3e | 676 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 677 | clock-names = "apb_pclk"; |
42cf2098 PV |
678 | #dma-cells = <1>; |
679 | #dma-channels = <8>; | |
680 | #dma-requests = <32>; | |
b074abb7 KK |
681 | }; |
682 | ||
683 | pdma1: pdma@121B0000 { | |
684 | compatible = "arm,pl330", "arm,primecell"; | |
685 | reg = <0x121B0000 0x1000>; | |
686 | interrupts = <0 35 0>; | |
fe273c3e | 687 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 688 | clock-names = "apb_pclk"; |
42cf2098 PV |
689 | #dma-cells = <1>; |
690 | #dma-channels = <8>; | |
691 | #dma-requests = <32>; | |
b074abb7 KK |
692 | }; |
693 | ||
009f7c9f | 694 | mdma0: mdma@10800000 { |
b074abb7 KK |
695 | compatible = "arm,pl330", "arm,primecell"; |
696 | reg = <0x10800000 0x1000>; | |
697 | interrupts = <0 33 0>; | |
fe273c3e | 698 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 699 | clock-names = "apb_pclk"; |
42cf2098 PV |
700 | #dma-cells = <1>; |
701 | #dma-channels = <8>; | |
702 | #dma-requests = <1>; | |
b074abb7 KK |
703 | }; |
704 | ||
009f7c9f | 705 | mdma1: mdma@11C10000 { |
b074abb7 KK |
706 | compatible = "arm,pl330", "arm,primecell"; |
707 | reg = <0x11C10000 0x1000>; | |
708 | interrupts = <0 124 0>; | |
fe273c3e | 709 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 710 | clock-names = "apb_pclk"; |
42cf2098 PV |
711 | #dma-cells = <1>; |
712 | #dma-channels = <8>; | |
713 | #dma-requests = <1>; | |
b074abb7 KK |
714 | }; |
715 | }; | |
716 | ||
c31f566d | 717 | gsc_0: gsc@13e00000 { |
1128658a SAB |
718 | compatible = "samsung,exynos5-gsc"; |
719 | reg = <0x13e00000 0x1000>; | |
720 | interrupts = <0 85 0>; | |
0da65870 | 721 | power-domains = <&pd_gsc>; |
fe273c3e | 722 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 723 | clock-names = "gscl"; |
6cbfdd73 | 724 | iommu = <&sysmmu_gsc0>; |
1128658a SAB |
725 | }; |
726 | ||
c31f566d | 727 | gsc_1: gsc@13e10000 { |
1128658a SAB |
728 | compatible = "samsung,exynos5-gsc"; |
729 | reg = <0x13e10000 0x1000>; | |
730 | interrupts = <0 86 0>; | |
0da65870 | 731 | power-domains = <&pd_gsc>; |
fe273c3e | 732 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 733 | clock-names = "gscl"; |
6cbfdd73 | 734 | iommu = <&sysmmu_gsc1>; |
1128658a SAB |
735 | }; |
736 | ||
c31f566d | 737 | gsc_2: gsc@13e20000 { |
1128658a SAB |
738 | compatible = "samsung,exynos5-gsc"; |
739 | reg = <0x13e20000 0x1000>; | |
740 | interrupts = <0 87 0>; | |
0da65870 | 741 | power-domains = <&pd_gsc>; |
fe273c3e | 742 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 743 | clock-names = "gscl"; |
6cbfdd73 | 744 | iommu = <&sysmmu_gsc2>; |
1128658a SAB |
745 | }; |
746 | ||
c31f566d | 747 | gsc_3: gsc@13e30000 { |
1128658a SAB |
748 | compatible = "samsung,exynos5-gsc"; |
749 | reg = <0x13e30000 0x1000>; | |
750 | interrupts = <0 88 0>; | |
0da65870 | 751 | power-domains = <&pd_gsc>; |
fe273c3e | 752 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 753 | clock-names = "gscl"; |
6cbfdd73 | 754 | iommu = <&sysmmu_gsc3>; |
1128658a | 755 | }; |
566cf8ee | 756 | |
19fd45bf | 757 | hdmi: hdmi { |
0d1fc829 | 758 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 759 | reg = <0x14530000 0x70000>; |
2d2c9a8d | 760 | power-domains = <&pd_disp1>; |
566cf8ee | 761 | interrupts = <0 95 0>; |
fe273c3e AH |
762 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
763 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
764 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 765 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 766 | "sclk_hdmiphy", "mout_hdmi"; |
e54d90ec | 767 | samsung,syscon-phandle = <&pmu_system_controller>; |
566cf8ee | 768 | }; |
5af0d8a3 RS |
769 | |
770 | mixer { | |
0d1fc829 | 771 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 | 772 | reg = <0x14450000 0x10000>; |
2d2c9a8d | 773 | power-domains = <&pd_disp1>; |
5af0d8a3 | 774 | interrupts = <0 94 0>; |
c950ea68 MS |
775 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
776 | <&clock CLK_SCLK_HDMI>; | |
777 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
6cbfdd73 | 778 | iommus = <&sysmmu_tv>; |
5af0d8a3 | 779 | }; |
ad4aebe1 | 780 | |
77899d53 VS |
781 | dp_phy: video-phy@10040720 { |
782 | compatible = "samsung,exynos5250-dp-video-phy"; | |
e93e5454 | 783 | samsung,pmu-syscon = <&pmu_system_controller>; |
77899d53 VS |
784 | #phy-cells = <0>; |
785 | }; | |
786 | ||
f408f9db NKC |
787 | adc: adc@12D10000 { |
788 | compatible = "samsung,exynos-adc-v1"; | |
db9bf4d6 | 789 | reg = <0x12D10000 0x100>; |
f408f9db | 790 | interrupts = <0 106 0>; |
fe273c3e | 791 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
792 | clock-names = "adc"; |
793 | #io-channel-cells = <1>; | |
794 | io-channel-ranges; | |
db9bf4d6 | 795 | samsung,syscon-phandle = <&pmu_system_controller>; |
f408f9db NKC |
796 | status = "disabled"; |
797 | }; | |
183af252 NKC |
798 | |
799 | sss@10830000 { | |
800 | compatible = "samsung,exynos4210-secss"; | |
801 | reg = <0x10830000 0x10000>; | |
802 | interrupts = <0 112 0>; | |
e06e1067 | 803 | clocks = <&clock CLK_SSS>; |
183af252 NKC |
804 | clock-names = "secss"; |
805 | }; | |
6cbfdd73 MS |
806 | |
807 | sysmmu_g2d: sysmmu@10A60000 { | |
808 | compatible = "samsung,exynos-sysmmu"; | |
809 | reg = <0x10A60000 0x1000>; | |
810 | interrupt-parent = <&combiner>; | |
811 | interrupts = <24 5>; | |
812 | clock-names = "sysmmu", "master"; | |
813 | clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; | |
814 | #iommu-cells = <0>; | |
815 | }; | |
816 | ||
817 | sysmmu_mfc_r: sysmmu@11200000 { | |
818 | compatible = "samsung,exynos-sysmmu"; | |
819 | reg = <0x11200000 0x1000>; | |
820 | interrupt-parent = <&combiner>; | |
821 | interrupts = <6 2>; | |
822 | power-domains = <&pd_mfc>; | |
823 | clock-names = "sysmmu", "master"; | |
824 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
825 | #iommu-cells = <0>; | |
826 | }; | |
827 | ||
828 | sysmmu_mfc_l: sysmmu@11210000 { | |
829 | compatible = "samsung,exynos-sysmmu"; | |
830 | reg = <0x11210000 0x1000>; | |
831 | interrupt-parent = <&combiner>; | |
832 | interrupts = <8 5>; | |
833 | power-domains = <&pd_mfc>; | |
834 | clock-names = "sysmmu", "master"; | |
835 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
836 | #iommu-cells = <0>; | |
837 | }; | |
838 | ||
839 | sysmmu_rotator: sysmmu@11D40000 { | |
840 | compatible = "samsung,exynos-sysmmu"; | |
841 | reg = <0x11D40000 0x1000>; | |
842 | interrupt-parent = <&combiner>; | |
843 | interrupts = <4 0>; | |
844 | clock-names = "sysmmu", "master"; | |
845 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
846 | #iommu-cells = <0>; | |
847 | }; | |
848 | ||
849 | sysmmu_jpeg: sysmmu@11F20000 { | |
850 | compatible = "samsung,exynos-sysmmu"; | |
851 | reg = <0x11F20000 0x1000>; | |
852 | interrupt-parent = <&combiner>; | |
853 | interrupts = <4 2>; | |
854 | power-domains = <&pd_gsc>; | |
855 | clock-names = "sysmmu", "master"; | |
856 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
857 | #iommu-cells = <0>; | |
858 | }; | |
859 | ||
860 | sysmmu_fimc_isp: sysmmu@13260000 { | |
861 | compatible = "samsung,exynos-sysmmu"; | |
862 | reg = <0x13260000 0x1000>; | |
863 | interrupt-parent = <&combiner>; | |
864 | interrupts = <10 6>; | |
865 | clock-names = "sysmmu"; | |
866 | clocks = <&clock CLK_SMMU_FIMC_ISP>; | |
867 | #iommu-cells = <0>; | |
868 | }; | |
869 | ||
870 | sysmmu_fimc_drc: sysmmu@13270000 { | |
871 | compatible = "samsung,exynos-sysmmu"; | |
872 | reg = <0x13270000 0x1000>; | |
873 | interrupt-parent = <&combiner>; | |
874 | interrupts = <11 6>; | |
875 | clock-names = "sysmmu"; | |
876 | clocks = <&clock CLK_SMMU_FIMC_DRC>; | |
877 | #iommu-cells = <0>; | |
878 | }; | |
879 | ||
880 | sysmmu_fimc_fd: sysmmu@132A0000 { | |
881 | compatible = "samsung,exynos-sysmmu"; | |
882 | reg = <0x132A0000 0x1000>; | |
883 | interrupt-parent = <&combiner>; | |
884 | interrupts = <5 0>; | |
885 | clock-names = "sysmmu"; | |
886 | clocks = <&clock CLK_SMMU_FIMC_FD>; | |
887 | #iommu-cells = <0>; | |
888 | }; | |
889 | ||
890 | sysmmu_fimc_scc: sysmmu@13280000 { | |
891 | compatible = "samsung,exynos-sysmmu"; | |
892 | reg = <0x13280000 0x1000>; | |
893 | interrupt-parent = <&combiner>; | |
894 | interrupts = <5 2>; | |
895 | clock-names = "sysmmu"; | |
896 | clocks = <&clock CLK_SMMU_FIMC_SCC>; | |
897 | #iommu-cells = <0>; | |
898 | }; | |
899 | ||
900 | sysmmu_fimc_scp: sysmmu@13290000 { | |
901 | compatible = "samsung,exynos-sysmmu"; | |
902 | reg = <0x13290000 0x1000>; | |
903 | interrupt-parent = <&combiner>; | |
904 | interrupts = <3 6>; | |
905 | clock-names = "sysmmu"; | |
906 | clocks = <&clock CLK_SMMU_FIMC_SCP>; | |
907 | #iommu-cells = <0>; | |
908 | }; | |
909 | ||
910 | sysmmu_fimc_mcuctl: sysmmu@132B0000 { | |
911 | compatible = "samsung,exynos-sysmmu"; | |
912 | reg = <0x132B0000 0x1000>; | |
913 | interrupt-parent = <&combiner>; | |
914 | interrupts = <5 4>; | |
915 | clock-names = "sysmmu"; | |
916 | clocks = <&clock CLK_SMMU_FIMC_MCU>; | |
917 | #iommu-cells = <0>; | |
918 | }; | |
919 | ||
920 | sysmmu_fimc_odc: sysmmu@132C0000 { | |
921 | compatible = "samsung,exynos-sysmmu"; | |
922 | reg = <0x132C0000 0x1000>; | |
923 | interrupt-parent = <&combiner>; | |
924 | interrupts = <11 0>; | |
925 | clock-names = "sysmmu"; | |
926 | clocks = <&clock CLK_SMMU_FIMC_ODC>; | |
927 | #iommu-cells = <0>; | |
928 | }; | |
929 | ||
930 | sysmmu_fimc_dis0: sysmmu@132D0000 { | |
931 | compatible = "samsung,exynos-sysmmu"; | |
932 | reg = <0x132D0000 0x1000>; | |
933 | interrupt-parent = <&combiner>; | |
934 | interrupts = <10 4>; | |
935 | clock-names = "sysmmu"; | |
936 | clocks = <&clock CLK_SMMU_FIMC_DIS0>; | |
937 | #iommu-cells = <0>; | |
938 | }; | |
939 | ||
940 | sysmmu_fimc_dis1: sysmmu@132E0000{ | |
941 | compatible = "samsung,exynos-sysmmu"; | |
942 | reg = <0x132E0000 0x1000>; | |
943 | interrupt-parent = <&combiner>; | |
944 | interrupts = <9 4>; | |
945 | clock-names = "sysmmu"; | |
946 | clocks = <&clock CLK_SMMU_FIMC_DIS1>; | |
947 | #iommu-cells = <0>; | |
948 | }; | |
949 | ||
950 | sysmmu_fimc_3dnr: sysmmu@132F0000 { | |
951 | compatible = "samsung,exynos-sysmmu"; | |
952 | reg = <0x132F0000 0x1000>; | |
953 | interrupt-parent = <&combiner>; | |
954 | interrupts = <5 6>; | |
955 | clock-names = "sysmmu"; | |
956 | clocks = <&clock CLK_SMMU_FIMC_3DNR>; | |
957 | #iommu-cells = <0>; | |
958 | }; | |
959 | ||
960 | sysmmu_fimc_lite0: sysmmu@13C40000 { | |
961 | compatible = "samsung,exynos-sysmmu"; | |
962 | reg = <0x13C40000 0x1000>; | |
963 | interrupt-parent = <&combiner>; | |
964 | interrupts = <3 4>; | |
965 | power-domains = <&pd_gsc>; | |
966 | clock-names = "sysmmu", "master"; | |
967 | clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; | |
968 | #iommu-cells = <0>; | |
969 | }; | |
970 | ||
971 | sysmmu_fimc_lite1: sysmmu@13C50000 { | |
972 | compatible = "samsung,exynos-sysmmu"; | |
973 | reg = <0x13C50000 0x1000>; | |
974 | interrupt-parent = <&combiner>; | |
975 | interrupts = <24 1>; | |
976 | power-domains = <&pd_gsc>; | |
977 | clock-names = "sysmmu", "master"; | |
978 | clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; | |
979 | #iommu-cells = <0>; | |
980 | }; | |
981 | ||
982 | sysmmu_gsc0: sysmmu@13E80000 { | |
983 | compatible = "samsung,exynos-sysmmu"; | |
984 | reg = <0x13E80000 0x1000>; | |
985 | interrupt-parent = <&combiner>; | |
986 | interrupts = <2 0>; | |
987 | power-domains = <&pd_gsc>; | |
988 | clock-names = "sysmmu", "master"; | |
989 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | |
990 | #iommu-cells = <0>; | |
991 | }; | |
992 | ||
993 | sysmmu_gsc1: sysmmu@13E90000 { | |
994 | compatible = "samsung,exynos-sysmmu"; | |
995 | reg = <0x13E90000 0x1000>; | |
996 | interrupt-parent = <&combiner>; | |
997 | interrupts = <2 2>; | |
998 | power-domains = <&pd_gsc>; | |
999 | clock-names = "sysmmu", "master"; | |
1000 | clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; | |
1001 | #iommu-cells = <0>; | |
1002 | }; | |
1003 | ||
1004 | sysmmu_gsc2: sysmmu@13EA0000 { | |
1005 | compatible = "samsung,exynos-sysmmu"; | |
1006 | reg = <0x13EA0000 0x1000>; | |
1007 | interrupt-parent = <&combiner>; | |
1008 | interrupts = <2 4>; | |
1009 | power-domains = <&pd_gsc>; | |
1010 | clock-names = "sysmmu", "master"; | |
1011 | clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; | |
1012 | #iommu-cells = <0>; | |
1013 | }; | |
1014 | ||
1015 | sysmmu_gsc3: sysmmu@13EB0000 { | |
1016 | compatible = "samsung,exynos-sysmmu"; | |
1017 | reg = <0x13EB0000 0x1000>; | |
1018 | interrupt-parent = <&combiner>; | |
1019 | interrupts = <2 6>; | |
1020 | power-domains = <&pd_gsc>; | |
1021 | clock-names = "sysmmu", "master"; | |
1022 | clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; | |
1023 | #iommu-cells = <0>; | |
1024 | }; | |
1025 | ||
1026 | sysmmu_fimd1: sysmmu@14640000 { | |
1027 | compatible = "samsung,exynos-sysmmu"; | |
1028 | reg = <0x14640000 0x1000>; | |
1029 | interrupt-parent = <&combiner>; | |
1030 | interrupts = <3 2>; | |
1031 | power-domains = <&pd_disp1>; | |
1032 | clock-names = "sysmmu", "master"; | |
1033 | clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; | |
1034 | #iommu-cells = <0>; | |
1035 | }; | |
1036 | ||
1037 | sysmmu_tv: sysmmu@14650000 { | |
1038 | compatible = "samsung,exynos-sysmmu"; | |
1039 | reg = <0x14650000 0x1000>; | |
1040 | interrupt-parent = <&combiner>; | |
1041 | interrupts = <7 4>; | |
1042 | power-domains = <&pd_disp1>; | |
1043 | clock-names = "sysmmu", "master"; | |
1044 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
1045 | #iommu-cells = <0>; | |
1046 | }; | |
b074abb7 | 1047 | }; |
e9a2f409 KK |
1048 | |
1049 | &dp { | |
1050 | power-domains = <&pd_disp1>; | |
1051 | clocks = <&clock CLK_DP>; | |
1052 | clock-names = "dp"; | |
1053 | phys = <&dp_phy>; | |
1054 | phy-names = "dp"; | |
1055 | }; | |
1056 | ||
1057 | &fimd { | |
1058 | power-domains = <&pd_disp1>; | |
1059 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | |
1060 | clock-names = "sclk_fimd", "fimd"; | |
6cbfdd73 | 1061 | iommus = <&sysmmu_fimd1>; |
e9a2f409 KK |
1062 | }; |
1063 | ||
1064 | &rtc { | |
1065 | clocks = <&clock CLK_RTC>; | |
1066 | clock-names = "rtc"; | |
1067 | interrupt-parent = <&pmu_system_controller>; | |
1068 | status = "disabled"; | |
1069 | }; | |
1070 | ||
1071 | &serial_0 { | |
1072 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
1073 | clock-names = "uart", "clk_uart_baud0"; | |
1074 | }; | |
1075 | ||
1076 | &serial_1 { | |
1077 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
1078 | clock-names = "uart", "clk_uart_baud0"; | |
1079 | }; | |
1080 | ||
1081 | &serial_2 { | |
1082 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
1083 | clock-names = "uart", "clk_uart_baud0"; | |
1084 | }; | |
1085 | ||
1086 | &serial_3 { | |
1087 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
1088 | clock-names = "uart", "clk_uart_baud0"; | |
1089 | }; | |
dc561797 JMC |
1090 | |
1091 | #include "exynos5250-pinctrl.dtsi" |