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Merge remote-tracking branches 'asoc/topic/jack', 'asoc/topic/max98357a', 'asoc/topic...
[deliverable/linux.git] / arch / arm / boot / dts / exynos5250.dtsi
CommitLineData
b074abb7
KK		 1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
fe273c3e 20#include <dt-bindings/clock/exynos5250.h>
e6c21cba 21#include "exynos5.dtsi"
3799279f 22#include "exynos5250-pinctrl.dtsi"
b074abb7 23
602408e3 24#include <dt-bindings/clock/exynos-audss-clk.h>
b074abb7
KK		 25
26/ {
8bdb31b4 27 compatible = "samsung,exynos5250", "samsung,exynos5";
b074abb7 28
79989ba3
TA		 29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
1128658a
SAB		 33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 gsc2 = &gsc_2;
36 gsc3 = &gsc_3;
c8149df0
YK		 37 mshc0 = &mmc_0;
38 mshc1 = &mmc_1;
39 mshc2 = &mmc_2;
40 mshc3 = &mmc_3;
b9fa3e7b
AK		 41 i2c0 = &i2c_0;
42 i2c1 = &i2c_1;
43 i2c2 = &i2c_2;
44 i2c3 = &i2c_3;
45 i2c4 = &i2c_4;
46 i2c5 = &i2c_5;
47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8;
ba0d7ed3 50 i2c9 = &i2c_9;
f8bfe2b0
TA		 51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
79989ba3
TA		 55 };
56
1897d2f3
CK		 57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0>;
0da80563 65 clock-frequency = <1700000000>;
1897d2f3
CK		 66 };
67 cpu@1 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a15";
70 reg = <1>;
0da80563 71 clock-frequency = <1700000000>;
1897d2f3 72 };
79989ba3
TA		 73 };
74
b3205dea
SK		 75 sysram@02020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x30000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x30000>;
81
82 smp-sysram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sysram@2f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x2f000 0x1000>;
90 };
91 };
92
c31f566d 93 pd_gsc: gsc-power-domain@10044000 {
6f9e95e6
PK		 94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10044000 0x20>;
0da65870 96 #power-domain-cells = <0>;
6f9e95e6
PK		 97 };
98
c31f566d 99 pd_mfc: mfc-power-domain@10044040 {
6f9e95e6
PK		 100 compatible = "samsung,exynos4210-pd";
101 reg = <0x10044040 0x20>;
0da65870 102 #power-domain-cells = <0>;
6f9e95e6
PK		 103 };
104
c31f566d 105 clock: clock-controller@10010000 {
d8bafc87
TA		 106 compatible = "samsung,exynos5250-clock";
107 reg = <0x10010000 0x30000>;
108 #clock-cells = <1>;
109 };
110
bba23d95
PV		 111 clock_audss: audss-clock-controller@3810000 {
112 compatible = "samsung,exynos5250-audss-clock";
113 reg = <0x03810000 0x0C>;
114 #clock-cells = <1>;
fe273c3e
AH		 115 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
116 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
c08ceea3 117 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
bba23d95
PV		 118 };
119
2b7da988
AG		 120 timer {
121 compatible = "arm,armv7-timer";
122 interrupts = <1 13 0xf08>,
123 <1 14 0xf08>,
124 <1 11 0xf08>,
125 <1 10 0xf08>;
4d594dd3
YK		 126 /* Unfortunately we need this since some versions of U-Boot
127 * on Exynos don't set the CNTFRQ register, so we need the
128 * value from DT.
129 */
130 clock-frequency = <24000000>;
b074abb7
KK		 131 };
132
bbd9700a
TA		 133 mct@101C0000 {
134 compatible = "samsung,exynos4210-mct";
135 reg = <0x101C0000 0x800>;
136 interrupt-controller;
137 #interrups-cells = <2>;
138 interrupt-parent = <&mct_map>;
139 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
140 <4 0>, <5 0>;
fe273c3e 141 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
2de6847c 142 clock-names = "fin_pll", "mct";
bbd9700a
TA		 143
144 mct_map: mct-map {
145 #interrupt-cells = <2>;
146 #address-cells = <0>;
147 #size-cells = <0>;
148 interrupt-map = <0x0 0 &combiner 23 3>,
149 <0x1 0 &combiner 23 4>,
150 <0x2 0 &combiner 25 2>,
151 <0x3 0 &combiner 25 3>,
152 <0x4 0 &gic 0 120 0>,
153 <0x5 0 &gic 0 121 0>;
154 };
155 };
156
4f801e59
CP		 157 pmu {
158 compatible = "arm,cortex-a15-pmu";
159 interrupt-parent = <&combiner>;
160 interrupts = <1 2>, <22 4>;
161 };
162
f8bfe2b0
TA		 163 pinctrl_0: pinctrl@11400000 {
164 compatible = "samsung,exynos5250-pinctrl";
165 reg = <0x11400000 0x1000>;
166 interrupts = <0 46 0>;
167
168 wakup_eint: wakeup-interrupt-controller {
169 compatible = "samsung,exynos4210-wakeup-eint";
170 interrupt-parent = <&gic>;
171 interrupts = <0 32 0>;
172 };
173 };
174
175 pinctrl_1: pinctrl@13400000 {
176 compatible = "samsung,exynos5250-pinctrl";
177 reg = <0x13400000 0x1000>;
178 interrupts = <0 45 0>;
179 };
180
181 pinctrl_2: pinctrl@10d10000 {
182 compatible = "samsung,exynos5250-pinctrl";
183 reg = <0x10d10000 0x1000>;
184 interrupts = <0 50 0>;
185 };
186
0abb6aea 187 pinctrl_3: pinctrl@03860000 {
f8bfe2b0 188 compatible = "samsung,exynos5250-pinctrl";
0abb6aea 189 reg = <0x03860000 0x1000>;
f8bfe2b0
TA		 190 interrupts = <0 47 0>;
191 };
192
c680036a
LKA		 193 pmu_system_controller: system-controller@10040000 {
194 compatible = "samsung,exynos5250-pmu", "syscon";
195 reg = <0x10040000 0x5000>;
d19bb397
TF		 196 clock-names = "clkout16";
197 clocks = <&clock CLK_FIN_PLL>;
198 #clock-cells = <1>;
c680036a
LKA		 199 };
200
dfbbdbf4
VG		 201 sysreg_system_controller: syscon@10050000 {
202 compatible = "samsung,exynos5-sysreg", "syscon";
203 reg = <0x10050000 0x5000>;
204 };
205
1d287620
LKA		 206 watchdog@101D0000 {
207 compatible = "samsung,exynos5250-wdt";
208 reg = <0x101D0000 0x100>;
209 interrupts = <0 42 0>;
fe273c3e 210 clocks = <&clock CLK_WDT>;
2de6847c 211 clock-names = "watchdog";
1d287620 212 samsung,syscon-phandle = <&pmu_system_controller>;
b074abb7
KK		 213 };
214
21aa5217
SK		 215 g2d@10850000 {
216 compatible = "samsung,exynos5250-g2d";
217 reg = <0x10850000 0x1000>;
218 interrupts = <0 91 0>;
fe273c3e 219 clocks = <&clock CLK_G2D>;
21aa5217
SK		 220 clock-names = "fimg2d";
221 };
222
19fd45bf 223 mfc: codec@11000000 {
2eae613b
AK		 224 compatible = "samsung,mfc-v6";
225 reg = <0x11000000 0x10000>;
226 interrupts = <0 96 0>;
0da65870 227 power-domains = <&pd_mfc>;
fe273c3e 228 clocks = <&clock CLK_MFC>;
8b6bea33 229 clock-names = "mfc";
2eae613b
AK		 230 };
231
19fd45bf 232 rtc: rtc@101E0000 {
fe273c3e 233 clocks = <&clock CLK_RTC>;
2de6847c 234 clock-names = "rtc";
65cedf0e 235 status = "disabled";
b074abb7
KK		 236 };
237
ef405e04
ADK		 238 tmu@10060000 {
239 compatible = "samsung,exynos5250-tmu";
240 reg = <0x10060000 0x100>;
241 interrupts = <0 65 0>;
fe273c3e 242 clocks = <&clock CLK_TMU>;
2de6847c 243 clock-names = "tmu_apbif";
ef405e04
ADK		 244 };
245
b074abb7 246 serial@12C00000 {
fe273c3e 247 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
2de6847c 248 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 249 };
250
251 serial@12C10000 {
fe273c3e 252 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
2de6847c 253 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 254 };
255
256 serial@12C20000 {
fe273c3e 257 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
2de6847c 258 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 259 };
260
261 serial@12C30000 {
fe273c3e 262 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
2de6847c 263 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 264 };
265
19fd45bf 266 sata: sata@122F0000 {
ba0d7ed3
YK		 267 compatible = "snps,dwc-ahci";
268 samsung,sata-freq = <66>;
c47d244a
VA		 269 reg = <0x122F0000 0x1ff>;
270 interrupts = <0 115 0>;
fe273c3e 271 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
2de6847c 272 clock-names = "sata", "sclk_sata";
ba0d7ed3
YK		 273 phys = <&sata_phy>;
274 phy-names = "sata-phy";
275 status = "disabled";
c47d244a
VA		 276 };
277
ba0d7ed3
YK		 278 sata_phy: sata-phy@12170000 {
279 compatible = "samsung,exynos5250-sata-phy";
c47d244a 280 reg = <0x12170000 0x1ff>;
e06e1067 281 clocks = <&clock CLK_SATA_PHYCTRL>;
ba0d7ed3
YK		 282 clock-names = "sata_phyctrl";
283 #phy-cells = <0>;
284 samsung,syscon-phandle = <&pmu_system_controller>;
285 status = "disabled";
c47d244a
VA		 286 };
287
b9fa3e7b 288 i2c_0: i2c@12C60000 {
b074abb7
KK		 289 compatible = "samsung,s3c2440-i2c";
290 reg = <0x12C60000 0x100>;
291 interrupts = <0 56 0>;
009f7c9f
TA		 292 #address-cells = <1>;
293 #size-cells = <0>;
fe273c3e 294 clocks = <&clock CLK_I2C0>;
2de6847c 295 clock-names = "i2c";
f8bfe2b0
TA		 296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c0_bus>;
1888eb75 298 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 299 status = "disabled";
b074abb7
KK		 300 };
301
b9fa3e7b 302 i2c_1: i2c@12C70000 {
b074abb7
KK		 303 compatible = "samsung,s3c2440-i2c";
304 reg = <0x12C70000 0x100>;
305 interrupts = <0 57 0>;
009f7c9f
TA		 306 #address-cells = <1>;
307 #size-cells = <0>;
fe273c3e 308 clocks = <&clock CLK_I2C1>;
2de6847c 309 clock-names = "i2c";
f8bfe2b0
TA		 310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c1_bus>;
1888eb75 312 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 313 status = "disabled";
b074abb7
KK		 314 };
315
b9fa3e7b 316 i2c_2: i2c@12C80000 {
b074abb7
KK		 317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x12C80000 0x100>;
319 interrupts = <0 58 0>;
009f7c9f
TA		 320 #address-cells = <1>;
321 #size-cells = <0>;
fe273c3e 322 clocks = <&clock CLK_I2C2>;
2de6847c 323 clock-names = "i2c";
f8bfe2b0
TA		 324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_bus>;
1888eb75 326 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 327 status = "disabled";
b074abb7
KK		 328 };
329
b9fa3e7b 330 i2c_3: i2c@12C90000 {
b074abb7
KK		 331 compatible = "samsung,s3c2440-i2c";
332 reg = <0x12C90000 0x100>;
333 interrupts = <0 59 0>;
009f7c9f
TA		 334 #address-cells = <1>;
335 #size-cells = <0>;
fe273c3e 336 clocks = <&clock CLK_I2C3>;
2de6847c 337 clock-names = "i2c";
f8bfe2b0
TA		 338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c3_bus>;
1888eb75 340 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 341 status = "disabled";
b074abb7
KK		 342 };
343
b9fa3e7b 344 i2c_4: i2c@12CA0000 {
b074abb7
KK		 345 compatible = "samsung,s3c2440-i2c";
346 reg = <0x12CA0000 0x100>;
347 interrupts = <0 60 0>;
009f7c9f
TA		 348 #address-cells = <1>;
349 #size-cells = <0>;
fe273c3e 350 clocks = <&clock CLK_I2C4>;
2de6847c 351 clock-names = "i2c";
f8bfe2b0
TA		 352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c4_bus>;
6ad8ebff 354 status = "disabled";
b074abb7
KK		 355 };
356
b9fa3e7b 357 i2c_5: i2c@12CB0000 {
b074abb7
KK		 358 compatible = "samsung,s3c2440-i2c";
359 reg = <0x12CB0000 0x100>;
360 interrupts = <0 61 0>;
009f7c9f
TA		 361 #address-cells = <1>;
362 #size-cells = <0>;
fe273c3e 363 clocks = <&clock CLK_I2C5>;
2de6847c 364 clock-names = "i2c";
f8bfe2b0
TA		 365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c5_bus>;
6ad8ebff 367 status = "disabled";
b074abb7
KK		 368 };
369
b9fa3e7b 370 i2c_6: i2c@12CC0000 {
b074abb7
KK		 371 compatible = "samsung,s3c2440-i2c";
372 reg = <0x12CC0000 0x100>;
373 interrupts = <0 62 0>;
009f7c9f
TA		 374 #address-cells = <1>;
375 #size-cells = <0>;
fe273c3e 376 clocks = <&clock CLK_I2C6>;
2de6847c 377 clock-names = "i2c";
f8bfe2b0
TA		 378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c6_bus>;
6ad8ebff 380 status = "disabled";
b074abb7
KK		 381 };
382
b9fa3e7b 383 i2c_7: i2c@12CD0000 {
b074abb7
KK		 384 compatible = "samsung,s3c2440-i2c";
385 reg = <0x12CD0000 0x100>;
386 interrupts = <0 63 0>;
009f7c9f
TA		 387 #address-cells = <1>;
388 #size-cells = <0>;
fe273c3e 389 clocks = <&clock CLK_I2C7>;
2de6847c 390 clock-names = "i2c";
f8bfe2b0
TA		 391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c7_bus>;
6ad8ebff 393 status = "disabled";
3e3e9ce4
RS		 394 };
395
b9fa3e7b 396 i2c_8: i2c@12CE0000 {
3e3e9ce4
RS		 397 compatible = "samsung,s3c2440-hdmiphy-i2c";
398 reg = <0x12CE0000 0x1000>;
399 interrupts = <0 64 0>;
400 #address-cells = <1>;
401 #size-cells = <0>;
fe273c3e 402 clocks = <&clock CLK_I2C_HDMI>;
2de6847c 403 clock-names = "i2c";
6ad8ebff 404 status = "disabled";
24025f6f
OJ		 405 };
406
ba0d7ed3 407 i2c_9: i2c@121D0000 {
c47d244a
VA		 408 compatible = "samsung,exynos5-sata-phy-i2c";
409 reg = <0x121D0000 0x100>;
410 #address-cells = <1>;
411 #size-cells = <0>;
fe273c3e 412 clocks = <&clock CLK_SATA_PHYI2C>;
2de6847c 413 clock-names = "i2c";
6ad8ebff 414 status = "disabled";
b074abb7
KK		 415 };
416
79989ba3
TA		 417 spi_0: spi@12d20000 {
418 compatible = "samsung,exynos4210-spi";
fae93f7c 419 status = "disabled";
79989ba3
TA		 420 reg = <0x12d20000 0x100>;
421 interrupts = <0 66 0>;
a4a8a9d3
PV		 422 dmas = <&pdma0 5
423 &pdma0 4>;
424 dma-names = "tx", "rx";
79989ba3
TA		 425 #address-cells = <1>;
426 #size-cells = <0>;
fe273c3e 427 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
2de6847c 428 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 429 pinctrl-names = "default";
430 pinctrl-0 = <&spi0_bus>;
79989ba3
TA		 431 };
432
433 spi_1: spi@12d30000 {
434 compatible = "samsung,exynos4210-spi";
fae93f7c 435 status = "disabled";
79989ba3
TA		 436 reg = <0x12d30000 0x100>;
437 interrupts = <0 67 0>;
a4a8a9d3
PV		 438 dmas = <&pdma1 5
439 &pdma1 4>;
440 dma-names = "tx", "rx";
79989ba3
TA		 441 #address-cells = <1>;
442 #size-cells = <0>;
fe273c3e 443 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
2de6847c 444 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 445 pinctrl-names = "default";
446 pinctrl-0 = <&spi1_bus>;
79989ba3
TA		 447 };
448
449 spi_2: spi@12d40000 {
450 compatible = "samsung,exynos4210-spi";
fae93f7c 451 status = "disabled";
79989ba3
TA		 452 reg = <0x12d40000 0x100>;
453 interrupts = <0 68 0>;
a4a8a9d3
PV		 454 dmas = <&pdma0 7
455 &pdma0 6>;
456 dma-names = "tx", "rx";
79989ba3
TA		 457 #address-cells = <1>;
458 #size-cells = <0>;
fe273c3e 459 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
2de6847c 460 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 461 pinctrl-names = "default";
462 pinctrl-0 = <&spi2_bus>;
79989ba3
TA		 463 };
464
c8149df0 465 mmc_0: mmc@12200000 {
906fd84e
YK		 466 compatible = "samsung,exynos5250-dw-mshc";
467 interrupts = <0 75 0>;
468 #address-cells = <1>;
469 #size-cells = <0>;
84bd48a0 470 reg = <0x12200000 0x1000>;
fe273c3e 471 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
2de6847c 472 clock-names = "biu", "ciu";
46285a90 473 fifo-depth = <0x80>;
e908d5c5 474 status = "disabled";
84bd48a0
TA		 475 };
476
c8149df0 477 mmc_1: mmc@12210000 {
906fd84e
YK		 478 compatible = "samsung,exynos5250-dw-mshc";
479 interrupts = <0 76 0>;
480 #address-cells = <1>;
481 #size-cells = <0>;
84bd48a0 482 reg = <0x12210000 0x1000>;
fe273c3e 483 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
2de6847c 484 clock-names = "biu", "ciu";
46285a90 485 fifo-depth = <0x80>;
e908d5c5 486 status = "disabled";
84bd48a0
TA		 487 };
488
c8149df0 489 mmc_2: mmc@12220000 {
906fd84e
YK		 490 compatible = "samsung,exynos5250-dw-mshc";
491 interrupts = <0 77 0>;
492 #address-cells = <1>;
493 #size-cells = <0>;
84bd48a0 494 reg = <0x12220000 0x1000>;
fe273c3e 495 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
2de6847c 496 clock-names = "biu", "ciu";
46285a90 497 fifo-depth = <0x80>;
e908d5c5 498 status = "disabled";
84bd48a0
TA		 499 };
500
c8149df0 501 mmc_3: mmc@12230000 {
84bd48a0
TA		 502 compatible = "samsung,exynos5250-dw-mshc";
503 reg = <0x12230000 0x1000>;
504 interrupts = <0 78 0>;
505 #address-cells = <1>;
506 #size-cells = <0>;
fe273c3e 507 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
2de6847c 508 clock-names = "biu", "ciu";
46285a90 509 fifo-depth = <0x80>;
e908d5c5 510 status = "disabled";
84bd48a0
TA		 511 };
512
28a48058 513 i2s0: i2s@03830000 {
64183656 514 compatible = "samsung,s5pv210-i2s";
328aee4b 515 status = "disabled";
a0b5f81e 516 reg = <0x03830000 0x100>;
4c4c7463
PV		 517 dmas = <&pdma0 10
518 &pdma0 9
519 &pdma0 8>;
520 dma-names = "tx", "rx", "tx-sec";
916ec47e
PV		 521 clocks = <&clock_audss EXYNOS_I2S_BUS>,
522 <&clock_audss EXYNOS_I2S_BUS>,
523 <&clock_audss EXYNOS_SCLK_I2S>;
524 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
a0b5f81e 525 samsung,idma-addr = <0x03000000>;
f8bfe2b0
TA		 526 pinctrl-names = "default";
527 pinctrl-0 = <&i2s0_bus>;
4c4c7463
PV		 528 };
529
28a48058 530 i2s1: i2s@12D60000 {
64183656 531 compatible = "samsung,s3c6410-i2s";
328aee4b 532 status = "disabled";
a0b5f81e
MB		 533 reg = <0x12D60000 0x100>;
534 dmas = <&pdma1 12
535 &pdma1 11>;
536 dma-names = "tx", "rx";
fe273c3e 537 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
916ec47e 538 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 539 pinctrl-names = "default";
540 pinctrl-0 = <&i2s1_bus>;
4c4c7463
PV		 541 };
542
28a48058 543 i2s2: i2s@12D70000 {
64183656 544 compatible = "samsung,s3c6410-i2s";
328aee4b 545 status = "disabled";
a0b5f81e
MB		 546 reg = <0x12D70000 0x100>;
547 dmas = <&pdma0 12
548 &pdma0 11>;
549 dma-names = "tx", "rx";
fe273c3e 550 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
916ec47e 551 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 552 pinctrl-names = "default";
553 pinctrl-0 = <&i2s2_bus>;
4c4c7463
PV		 554 };
555
0b3dc97e
VG		 556 usb@12000000 {
557 compatible = "samsung,exynos5250-dwusb3";
fe273c3e 558 clocks = <&clock CLK_USB3>;
0b3dc97e
VG		 559 clock-names = "usbdrd30";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges;
563
0526f276 564 usbdrd_dwc3: dwc3 {
0b3dc97e
VG		 565 compatible = "synopsys,dwc3";
566 reg = <0x12000000 0x10000>;
567 interrupts = <0 72 0>;
7a4cf0fd
VG		 568 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
569 phy-names = "usb2-phy", "usb3-phy";
896db3b3
VG		 570 };
571 };
572
517083f4
VG		 573 usbdrd_phy: phy@12100000 {
574 compatible = "samsung,exynos5250-usbdrd-phy";
575 reg = <0x12100000 0x100>;
576 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
577 clock-names = "phy", "ref";
578 samsung,pmu-syscon = <&pmu_system_controller>;
579 #phy-cells = <1>;
580 };
581
19fd45bf 582 ehci: usb@12110000 {
13cbd1e3
VG		 583 compatible = "samsung,exynos4210-ehci";
584 reg = <0x12110000 0x100>;
585 interrupts = <0 71 0>;
b3cd7d87 586
fe273c3e 587 clocks = <&clock CLK_USB2>;
b3cd7d87 588 clock-names = "usbhost";
dba2f058
KD		 589 #address-cells = <1>;
590 #size-cells = <0>;
591 port@0 {
592 reg = <0>;
593 phys = <&usb2_phy_gen 1>;
594 };
13cbd1e3
VG		 595 };
596
19fd45bf 597 ohci: usb@12120000 {
7d40d867
VG		 598 compatible = "samsung,exynos4210-ohci";
599 reg = <0x12120000 0x100>;
600 interrupts = <0 71 0>;
b3cd7d87 601
fe273c3e 602 clocks = <&clock CLK_USB2>;
b3cd7d87 603 clock-names = "usbhost";
dba2f058
KD		 604 #address-cells = <1>;
605 #size-cells = <0>;
606 port@0 {
607 reg = <0>;
608 phys = <&usb2_phy_gen 1>;
609 };
7d40d867
VG		 610 };
611
dba2f058
KD		 612 usb2_phy_gen: phy@12130000 {
613 compatible = "samsung,exynos5250-usb2-phy";
614 reg = <0x12130000 0x100>;
615 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
616 clock-names = "phy", "ref";
617 #phy-cells = <1>;
618 samsung,sysreg-phandle = <&sysreg_system_controller>;
619 samsung,pmureg-phandle = <&pmu_system_controller>;
620 };
621
022cf308
LKA		 622 pwm: pwm@12dd0000 {
623 compatible = "samsung,exynos4210-pwm";
624 reg = <0x12dd0000 0x100>;
625 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
626 #pwm-cells = <3>;
fe273c3e 627 clocks = <&clock CLK_PWM>;
022cf308
LKA		 628 clock-names = "timers";
629 };
630
b074abb7
KK		 631 amba {
632 #address-cells = <1>;
633 #size-cells = <1>;
634 compatible = "arm,amba-bus";
635 interrupt-parent = <&gic>;
636 ranges;
637
638 pdma0: pdma@121A0000 {
639 compatible = "arm,pl330", "arm,primecell";
640 reg = <0x121A0000 0x1000>;
641 interrupts = <0 34 0>;
fe273c3e 642 clocks = <&clock CLK_PDMA0>;
2de6847c 643 clock-names = "apb_pclk";
42cf2098
PV		 644 #dma-cells = <1>;
645 #dma-channels = <8>;
646 #dma-requests = <32>;
b074abb7
KK		 647 };
648
649 pdma1: pdma@121B0000 {
650 compatible = "arm,pl330", "arm,primecell";
651 reg = <0x121B0000 0x1000>;
652 interrupts = <0 35 0>;
fe273c3e 653 clocks = <&clock CLK_PDMA1>;
2de6847c 654 clock-names = "apb_pclk";
42cf2098
PV		 655 #dma-cells = <1>;
656 #dma-channels = <8>;
657 #dma-requests = <32>;
b074abb7
KK		 658 };
659
009f7c9f 660 mdma0: mdma@10800000 {
b074abb7
KK		 661 compatible = "arm,pl330", "arm,primecell";
662 reg = <0x10800000 0x1000>;
663 interrupts = <0 33 0>;
fe273c3e 664 clocks = <&clock CLK_MDMA0>;
2de6847c 665 clock-names = "apb_pclk";
42cf2098
PV		 666 #dma-cells = <1>;
667 #dma-channels = <8>;
668 #dma-requests = <1>;
b074abb7
KK		 669 };
670
009f7c9f 671 mdma1: mdma@11C10000 {
b074abb7
KK		 672 compatible = "arm,pl330", "arm,primecell";
673 reg = <0x11C10000 0x1000>;
674 interrupts = <0 124 0>;
fe273c3e 675 clocks = <&clock CLK_MDMA1>;
2de6847c 676 clock-names = "apb_pclk";
42cf2098
PV		 677 #dma-cells = <1>;
678 #dma-channels = <8>;
679 #dma-requests = <1>;
b074abb7
KK		 680 };
681 };
682
c31f566d 683 gsc_0: gsc@13e00000 {
1128658a
SAB		 684 compatible = "samsung,exynos5-gsc";
685 reg = <0x13e00000 0x1000>;
686 interrupts = <0 85 0>;
0da65870 687 power-domains = <&pd_gsc>;
fe273c3e 688 clocks = <&clock CLK_GSCL0>;
2de6847c 689 clock-names = "gscl";
1128658a
SAB		 690 };
691
c31f566d 692 gsc_1: gsc@13e10000 {
1128658a
SAB		 693 compatible = "samsung,exynos5-gsc";
694 reg = <0x13e10000 0x1000>;
695 interrupts = <0 86 0>;
0da65870 696 power-domains = <&pd_gsc>;
fe273c3e 697 clocks = <&clock CLK_GSCL1>;
2de6847c 698 clock-names = "gscl";
1128658a
SAB		 699 };
700
c31f566d 701 gsc_2: gsc@13e20000 {
1128658a
SAB		 702 compatible = "samsung,exynos5-gsc";
703 reg = <0x13e20000 0x1000>;
704 interrupts = <0 87 0>;
0da65870 705 power-domains = <&pd_gsc>;
fe273c3e 706 clocks = <&clock CLK_GSCL2>;
2de6847c 707 clock-names = "gscl";
1128658a
SAB		 708 };
709
c31f566d 710 gsc_3: gsc@13e30000 {
1128658a
SAB		 711 compatible = "samsung,exynos5-gsc";
712 reg = <0x13e30000 0x1000>;
713 interrupts = <0 88 0>;
0da65870 714 power-domains = <&pd_gsc>;
fe273c3e 715 clocks = <&clock CLK_GSCL3>;
2de6847c 716 clock-names = "gscl";
1128658a 717 };
566cf8ee 718
19fd45bf 719 hdmi: hdmi {
0d1fc829 720 compatible = "samsung,exynos4212-hdmi";
101250ce 721 reg = <0x14530000 0x70000>;
566cf8ee 722 interrupts = <0 95 0>;
fe273c3e
AH		 723 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
724 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
725 <&clock CLK_MOUT_HDMI>;
2de6847c 726 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
27c16d19 727 "sclk_hdmiphy", "mout_hdmi";
e54d90ec 728 samsung,syscon-phandle = <&pmu_system_controller>;
566cf8ee 729 };
5af0d8a3
RS		 730
731 mixer {
0d1fc829 732 compatible = "samsung,exynos5250-mixer";
5af0d8a3
RS		 733 reg = <0x14450000 0x10000>;
734 interrupts = <0 94 0>;
fe273c3e 735 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
18fe6ef0 736 clock-names = "mixer", "sclk_hdmi";
5af0d8a3 737 };
ad4aebe1 738
77899d53
VS		 739 dp_phy: video-phy@10040720 {
740 compatible = "samsung,exynos5250-dp-video-phy";
e93e5454 741 samsung,pmu-syscon = <&pmu_system_controller>;
77899d53
VS		 742 #phy-cells = <0>;
743 };
744
19fd45bf 745 dp: dp-controller@145B0000 {
fe273c3e 746 clocks = <&clock CLK_DP>;
0f72a9ec 747 clock-names = "dp";
77899d53
VS		 748 phys = <&dp_phy>;
749 phy-names = "dp";
ad4aebe1 750 };
a7389cb1 751
19fd45bf 752 fimd: fimd@14400000 {
fe273c3e 753 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
a7389cb1
LKA		 754 clock-names = "sclk_fimd", "fimd";
755 };
f408f9db
NKC		 756
757 adc: adc@12D10000 {
758 compatible = "samsung,exynos-adc-v1";
db9bf4d6 759 reg = <0x12D10000 0x100>;
f408f9db 760 interrupts = <0 106 0>;
fe273c3e 761 clocks = <&clock CLK_ADC>;
f408f9db
NKC		 762 clock-names = "adc";
763 #io-channel-cells = <1>;
764 io-channel-ranges;
db9bf4d6 765 samsung,syscon-phandle = <&pmu_system_controller>;
f408f9db
NKC		 766 status = "disabled";
767 };
183af252
NKC		 768
769 sss@10830000 {
770 compatible = "samsung,exynos4210-secss";
771 reg = <0x10830000 0x10000>;
772 interrupts = <0 112 0>;
e06e1067 773 clocks = <&clock CLK_SSS>;
183af252
NKC		 774 clock-names = "secss";
775 };
b074abb7 776};
Linux kernel - Deliverables
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