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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
e6c21cba | 21 | #include "exynos5.dtsi" |
3799279f | 22 | #include "exynos5250-pinctrl.dtsi" |
b074abb7 | 23 | |
602408e3 | 24 | #include <dt-bindings/clock/exynos-audss-clk.h> |
b074abb7 KK |
25 | |
26 | / { | |
8bdb31b4 | 27 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
b074abb7 | 28 | |
79989ba3 TA |
29 | aliases { |
30 | spi0 = &spi_0; | |
31 | spi1 = &spi_1; | |
32 | spi2 = &spi_2; | |
1128658a SAB |
33 | gsc0 = &gsc_0; |
34 | gsc1 = &gsc_1; | |
35 | gsc2 = &gsc_2; | |
36 | gsc3 = &gsc_3; | |
c8149df0 YK |
37 | mshc0 = &mmc_0; |
38 | mshc1 = &mmc_1; | |
39 | mshc2 = &mmc_2; | |
40 | mshc3 = &mmc_3; | |
b9fa3e7b AK |
41 | i2c0 = &i2c_0; |
42 | i2c1 = &i2c_1; | |
43 | i2c2 = &i2c_2; | |
44 | i2c3 = &i2c_3; | |
45 | i2c4 = &i2c_4; | |
46 | i2c5 = &i2c_5; | |
47 | i2c6 = &i2c_6; | |
48 | i2c7 = &i2c_7; | |
49 | i2c8 = &i2c_8; | |
ba0d7ed3 | 50 | i2c9 = &i2c_9; |
f8bfe2b0 TA |
51 | pinctrl0 = &pinctrl_0; |
52 | pinctrl1 = &pinctrl_1; | |
53 | pinctrl2 = &pinctrl_2; | |
54 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
55 | }; |
56 | ||
1897d2f3 CK |
57 | cpus { |
58 | #address-cells = <1>; | |
59 | #size-cells = <0>; | |
60 | ||
61 | cpu@0 { | |
62 | device_type = "cpu"; | |
63 | compatible = "arm,cortex-a15"; | |
64 | reg = <0>; | |
0da80563 | 65 | clock-frequency = <1700000000>; |
1897d2f3 CK |
66 | }; |
67 | cpu@1 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a15"; | |
70 | reg = <1>; | |
0da80563 | 71 | clock-frequency = <1700000000>; |
1897d2f3 | 72 | }; |
79989ba3 TA |
73 | }; |
74 | ||
b3205dea SK |
75 | sysram@02020000 { |
76 | compatible = "mmio-sram"; | |
77 | reg = <0x02020000 0x30000>; | |
78 | #address-cells = <1>; | |
79 | #size-cells = <1>; | |
80 | ranges = <0 0x02020000 0x30000>; | |
81 | ||
82 | smp-sysram@0 { | |
83 | compatible = "samsung,exynos4210-sysram"; | |
84 | reg = <0x0 0x1000>; | |
85 | }; | |
86 | ||
87 | smp-sysram@2f000 { | |
88 | compatible = "samsung,exynos4210-sysram-ns"; | |
89 | reg = <0x2f000 0x1000>; | |
90 | }; | |
91 | }; | |
92 | ||
c31f566d | 93 | pd_gsc: gsc-power-domain@10044000 { |
6f9e95e6 PK |
94 | compatible = "samsung,exynos4210-pd"; |
95 | reg = <0x10044000 0x20>; | |
96 | }; | |
97 | ||
c31f566d | 98 | pd_mfc: mfc-power-domain@10044040 { |
6f9e95e6 PK |
99 | compatible = "samsung,exynos4210-pd"; |
100 | reg = <0x10044040 0x20>; | |
101 | }; | |
102 | ||
c31f566d | 103 | clock: clock-controller@10010000 { |
d8bafc87 TA |
104 | compatible = "samsung,exynos5250-clock"; |
105 | reg = <0x10010000 0x30000>; | |
106 | #clock-cells = <1>; | |
107 | }; | |
108 | ||
bba23d95 PV |
109 | clock_audss: audss-clock-controller@3810000 { |
110 | compatible = "samsung,exynos5250-audss-clock"; | |
111 | reg = <0x03810000 0x0C>; | |
112 | #clock-cells = <1>; | |
fe273c3e AH |
113 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
114 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
c08ceea3 | 115 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
bba23d95 PV |
116 | }; |
117 | ||
2b7da988 AG |
118 | timer { |
119 | compatible = "arm,armv7-timer"; | |
120 | interrupts = <1 13 0xf08>, | |
121 | <1 14 0xf08>, | |
122 | <1 11 0xf08>, | |
123 | <1 10 0xf08>; | |
4d594dd3 YK |
124 | /* Unfortunately we need this since some versions of U-Boot |
125 | * on Exynos don't set the CNTFRQ register, so we need the | |
126 | * value from DT. | |
127 | */ | |
128 | clock-frequency = <24000000>; | |
b074abb7 KK |
129 | }; |
130 | ||
bbd9700a TA |
131 | mct@101C0000 { |
132 | compatible = "samsung,exynos4210-mct"; | |
133 | reg = <0x101C0000 0x800>; | |
134 | interrupt-controller; | |
135 | #interrups-cells = <2>; | |
136 | interrupt-parent = <&mct_map>; | |
137 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
138 | <4 0>, <5 0>; | |
fe273c3e | 139 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
2de6847c | 140 | clock-names = "fin_pll", "mct"; |
bbd9700a TA |
141 | |
142 | mct_map: mct-map { | |
143 | #interrupt-cells = <2>; | |
144 | #address-cells = <0>; | |
145 | #size-cells = <0>; | |
146 | interrupt-map = <0x0 0 &combiner 23 3>, | |
147 | <0x1 0 &combiner 23 4>, | |
148 | <0x2 0 &combiner 25 2>, | |
149 | <0x3 0 &combiner 25 3>, | |
150 | <0x4 0 &gic 0 120 0>, | |
151 | <0x5 0 &gic 0 121 0>; | |
152 | }; | |
153 | }; | |
154 | ||
4f801e59 CP |
155 | pmu { |
156 | compatible = "arm,cortex-a15-pmu"; | |
157 | interrupt-parent = <&combiner>; | |
158 | interrupts = <1 2>, <22 4>; | |
159 | }; | |
160 | ||
f8bfe2b0 TA |
161 | pinctrl_0: pinctrl@11400000 { |
162 | compatible = "samsung,exynos5250-pinctrl"; | |
163 | reg = <0x11400000 0x1000>; | |
164 | interrupts = <0 46 0>; | |
165 | ||
166 | wakup_eint: wakeup-interrupt-controller { | |
167 | compatible = "samsung,exynos4210-wakeup-eint"; | |
168 | interrupt-parent = <&gic>; | |
169 | interrupts = <0 32 0>; | |
170 | }; | |
171 | }; | |
172 | ||
173 | pinctrl_1: pinctrl@13400000 { | |
174 | compatible = "samsung,exynos5250-pinctrl"; | |
175 | reg = <0x13400000 0x1000>; | |
176 | interrupts = <0 45 0>; | |
177 | }; | |
178 | ||
179 | pinctrl_2: pinctrl@10d10000 { | |
180 | compatible = "samsung,exynos5250-pinctrl"; | |
181 | reg = <0x10d10000 0x1000>; | |
182 | interrupts = <0 50 0>; | |
183 | }; | |
184 | ||
0abb6aea | 185 | pinctrl_3: pinctrl@03860000 { |
f8bfe2b0 | 186 | compatible = "samsung,exynos5250-pinctrl"; |
0abb6aea | 187 | reg = <0x03860000 0x1000>; |
f8bfe2b0 TA |
188 | interrupts = <0 47 0>; |
189 | }; | |
190 | ||
c680036a LKA |
191 | pmu_system_controller: system-controller@10040000 { |
192 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
193 | reg = <0x10040000 0x5000>; | |
d19bb397 TF |
194 | clock-names = "clkout16"; |
195 | clocks = <&clock CLK_FIN_PLL>; | |
196 | #clock-cells = <1>; | |
c680036a LKA |
197 | }; |
198 | ||
dfbbdbf4 VG |
199 | sysreg_system_controller: syscon@10050000 { |
200 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
201 | reg = <0x10050000 0x5000>; | |
202 | }; | |
203 | ||
1d287620 LKA |
204 | watchdog@101D0000 { |
205 | compatible = "samsung,exynos5250-wdt"; | |
206 | reg = <0x101D0000 0x100>; | |
207 | interrupts = <0 42 0>; | |
fe273c3e | 208 | clocks = <&clock CLK_WDT>; |
2de6847c | 209 | clock-names = "watchdog"; |
1d287620 | 210 | samsung,syscon-phandle = <&pmu_system_controller>; |
b074abb7 KK |
211 | }; |
212 | ||
21aa5217 SK |
213 | g2d@10850000 { |
214 | compatible = "samsung,exynos5250-g2d"; | |
215 | reg = <0x10850000 0x1000>; | |
216 | interrupts = <0 91 0>; | |
fe273c3e | 217 | clocks = <&clock CLK_G2D>; |
21aa5217 SK |
218 | clock-names = "fimg2d"; |
219 | }; | |
220 | ||
2eae613b AK |
221 | codec@11000000 { |
222 | compatible = "samsung,mfc-v6"; | |
223 | reg = <0x11000000 0x10000>; | |
224 | interrupts = <0 96 0>; | |
6f9e95e6 | 225 | samsung,power-domain = <&pd_mfc>; |
fe273c3e | 226 | clocks = <&clock CLK_MFC>; |
8b6bea33 | 227 | clock-names = "mfc"; |
2eae613b AK |
228 | }; |
229 | ||
24b44d24 | 230 | rtc@101E0000 { |
fe273c3e | 231 | clocks = <&clock CLK_RTC>; |
2de6847c | 232 | clock-names = "rtc"; |
65cedf0e | 233 | status = "disabled"; |
b074abb7 KK |
234 | }; |
235 | ||
ef405e04 ADK |
236 | tmu@10060000 { |
237 | compatible = "samsung,exynos5250-tmu"; | |
238 | reg = <0x10060000 0x100>; | |
239 | interrupts = <0 65 0>; | |
fe273c3e | 240 | clocks = <&clock CLK_TMU>; |
2de6847c | 241 | clock-names = "tmu_apbif"; |
ef405e04 ADK |
242 | }; |
243 | ||
b074abb7 | 244 | serial@12C00000 { |
fe273c3e | 245 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
2de6847c | 246 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
247 | }; |
248 | ||
249 | serial@12C10000 { | |
fe273c3e | 250 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
2de6847c | 251 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
252 | }; |
253 | ||
254 | serial@12C20000 { | |
fe273c3e | 255 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
2de6847c | 256 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
257 | }; |
258 | ||
259 | serial@12C30000 { | |
fe273c3e | 260 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
2de6847c | 261 | clock-names = "uart", "clk_uart_baud0"; |
b074abb7 KK |
262 | }; |
263 | ||
c47d244a | 264 | sata@122F0000 { |
ba0d7ed3 YK |
265 | compatible = "snps,dwc-ahci"; |
266 | samsung,sata-freq = <66>; | |
c47d244a VA |
267 | reg = <0x122F0000 0x1ff>; |
268 | interrupts = <0 115 0>; | |
fe273c3e | 269 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
2de6847c | 270 | clock-names = "sata", "sclk_sata"; |
ba0d7ed3 YK |
271 | phys = <&sata_phy>; |
272 | phy-names = "sata-phy"; | |
273 | status = "disabled"; | |
c47d244a VA |
274 | }; |
275 | ||
ba0d7ed3 YK |
276 | sata_phy: sata-phy@12170000 { |
277 | compatible = "samsung,exynos5250-sata-phy"; | |
c47d244a | 278 | reg = <0x12170000 0x1ff>; |
e06e1067 | 279 | clocks = <&clock CLK_SATA_PHYCTRL>; |
ba0d7ed3 YK |
280 | clock-names = "sata_phyctrl"; |
281 | #phy-cells = <0>; | |
282 | samsung,syscon-phandle = <&pmu_system_controller>; | |
283 | status = "disabled"; | |
c47d244a VA |
284 | }; |
285 | ||
b9fa3e7b | 286 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
287 | compatible = "samsung,s3c2440-i2c"; |
288 | reg = <0x12C60000 0x100>; | |
289 | interrupts = <0 56 0>; | |
009f7c9f TA |
290 | #address-cells = <1>; |
291 | #size-cells = <0>; | |
fe273c3e | 292 | clocks = <&clock CLK_I2C0>; |
2de6847c | 293 | clock-names = "i2c"; |
f8bfe2b0 TA |
294 | pinctrl-names = "default"; |
295 | pinctrl-0 = <&i2c0_bus>; | |
6ad8ebff | 296 | status = "disabled"; |
b074abb7 KK |
297 | }; |
298 | ||
b9fa3e7b | 299 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
300 | compatible = "samsung,s3c2440-i2c"; |
301 | reg = <0x12C70000 0x100>; | |
302 | interrupts = <0 57 0>; | |
009f7c9f TA |
303 | #address-cells = <1>; |
304 | #size-cells = <0>; | |
fe273c3e | 305 | clocks = <&clock CLK_I2C1>; |
2de6847c | 306 | clock-names = "i2c"; |
f8bfe2b0 TA |
307 | pinctrl-names = "default"; |
308 | pinctrl-0 = <&i2c1_bus>; | |
6ad8ebff | 309 | status = "disabled"; |
b074abb7 KK |
310 | }; |
311 | ||
b9fa3e7b | 312 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
313 | compatible = "samsung,s3c2440-i2c"; |
314 | reg = <0x12C80000 0x100>; | |
315 | interrupts = <0 58 0>; | |
009f7c9f TA |
316 | #address-cells = <1>; |
317 | #size-cells = <0>; | |
fe273c3e | 318 | clocks = <&clock CLK_I2C2>; |
2de6847c | 319 | clock-names = "i2c"; |
f8bfe2b0 TA |
320 | pinctrl-names = "default"; |
321 | pinctrl-0 = <&i2c2_bus>; | |
6ad8ebff | 322 | status = "disabled"; |
b074abb7 KK |
323 | }; |
324 | ||
b9fa3e7b | 325 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
326 | compatible = "samsung,s3c2440-i2c"; |
327 | reg = <0x12C90000 0x100>; | |
328 | interrupts = <0 59 0>; | |
009f7c9f TA |
329 | #address-cells = <1>; |
330 | #size-cells = <0>; | |
fe273c3e | 331 | clocks = <&clock CLK_I2C3>; |
2de6847c | 332 | clock-names = "i2c"; |
f8bfe2b0 TA |
333 | pinctrl-names = "default"; |
334 | pinctrl-0 = <&i2c3_bus>; | |
6ad8ebff | 335 | status = "disabled"; |
b074abb7 KK |
336 | }; |
337 | ||
b9fa3e7b | 338 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
339 | compatible = "samsung,s3c2440-i2c"; |
340 | reg = <0x12CA0000 0x100>; | |
341 | interrupts = <0 60 0>; | |
009f7c9f TA |
342 | #address-cells = <1>; |
343 | #size-cells = <0>; | |
fe273c3e | 344 | clocks = <&clock CLK_I2C4>; |
2de6847c | 345 | clock-names = "i2c"; |
f8bfe2b0 TA |
346 | pinctrl-names = "default"; |
347 | pinctrl-0 = <&i2c4_bus>; | |
6ad8ebff | 348 | status = "disabled"; |
b074abb7 KK |
349 | }; |
350 | ||
b9fa3e7b | 351 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
352 | compatible = "samsung,s3c2440-i2c"; |
353 | reg = <0x12CB0000 0x100>; | |
354 | interrupts = <0 61 0>; | |
009f7c9f TA |
355 | #address-cells = <1>; |
356 | #size-cells = <0>; | |
fe273c3e | 357 | clocks = <&clock CLK_I2C5>; |
2de6847c | 358 | clock-names = "i2c"; |
f8bfe2b0 TA |
359 | pinctrl-names = "default"; |
360 | pinctrl-0 = <&i2c5_bus>; | |
6ad8ebff | 361 | status = "disabled"; |
b074abb7 KK |
362 | }; |
363 | ||
b9fa3e7b | 364 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
365 | compatible = "samsung,s3c2440-i2c"; |
366 | reg = <0x12CC0000 0x100>; | |
367 | interrupts = <0 62 0>; | |
009f7c9f TA |
368 | #address-cells = <1>; |
369 | #size-cells = <0>; | |
fe273c3e | 370 | clocks = <&clock CLK_I2C6>; |
2de6847c | 371 | clock-names = "i2c"; |
f8bfe2b0 TA |
372 | pinctrl-names = "default"; |
373 | pinctrl-0 = <&i2c6_bus>; | |
6ad8ebff | 374 | status = "disabled"; |
b074abb7 KK |
375 | }; |
376 | ||
b9fa3e7b | 377 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
378 | compatible = "samsung,s3c2440-i2c"; |
379 | reg = <0x12CD0000 0x100>; | |
380 | interrupts = <0 63 0>; | |
009f7c9f TA |
381 | #address-cells = <1>; |
382 | #size-cells = <0>; | |
fe273c3e | 383 | clocks = <&clock CLK_I2C7>; |
2de6847c | 384 | clock-names = "i2c"; |
f8bfe2b0 TA |
385 | pinctrl-names = "default"; |
386 | pinctrl-0 = <&i2c7_bus>; | |
6ad8ebff | 387 | status = "disabled"; |
3e3e9ce4 RS |
388 | }; |
389 | ||
b9fa3e7b | 390 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
391 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
392 | reg = <0x12CE0000 0x1000>; | |
393 | interrupts = <0 64 0>; | |
394 | #address-cells = <1>; | |
395 | #size-cells = <0>; | |
fe273c3e | 396 | clocks = <&clock CLK_I2C_HDMI>; |
2de6847c | 397 | clock-names = "i2c"; |
6ad8ebff | 398 | status = "disabled"; |
24025f6f OJ |
399 | }; |
400 | ||
ba0d7ed3 | 401 | i2c_9: i2c@121D0000 { |
c47d244a VA |
402 | compatible = "samsung,exynos5-sata-phy-i2c"; |
403 | reg = <0x121D0000 0x100>; | |
404 | #address-cells = <1>; | |
405 | #size-cells = <0>; | |
fe273c3e | 406 | clocks = <&clock CLK_SATA_PHYI2C>; |
2de6847c | 407 | clock-names = "i2c"; |
6ad8ebff | 408 | status = "disabled"; |
b074abb7 KK |
409 | }; |
410 | ||
79989ba3 TA |
411 | spi_0: spi@12d20000 { |
412 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 413 | status = "disabled"; |
79989ba3 TA |
414 | reg = <0x12d20000 0x100>; |
415 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
416 | dmas = <&pdma0 5 |
417 | &pdma0 4>; | |
418 | dma-names = "tx", "rx"; | |
79989ba3 TA |
419 | #address-cells = <1>; |
420 | #size-cells = <0>; | |
fe273c3e | 421 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
2de6847c | 422 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
423 | pinctrl-names = "default"; |
424 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
425 | }; |
426 | ||
427 | spi_1: spi@12d30000 { | |
428 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 429 | status = "disabled"; |
79989ba3 TA |
430 | reg = <0x12d30000 0x100>; |
431 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
432 | dmas = <&pdma1 5 |
433 | &pdma1 4>; | |
434 | dma-names = "tx", "rx"; | |
79989ba3 TA |
435 | #address-cells = <1>; |
436 | #size-cells = <0>; | |
fe273c3e | 437 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
2de6847c | 438 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
439 | pinctrl-names = "default"; |
440 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
441 | }; |
442 | ||
443 | spi_2: spi@12d40000 { | |
444 | compatible = "samsung,exynos4210-spi"; | |
fae93f7c | 445 | status = "disabled"; |
79989ba3 TA |
446 | reg = <0x12d40000 0x100>; |
447 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
448 | dmas = <&pdma0 7 |
449 | &pdma0 6>; | |
450 | dma-names = "tx", "rx"; | |
79989ba3 TA |
451 | #address-cells = <1>; |
452 | #size-cells = <0>; | |
fe273c3e | 453 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
2de6847c | 454 | clock-names = "spi", "spi_busclk0"; |
f8bfe2b0 TA |
455 | pinctrl-names = "default"; |
456 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
457 | }; |
458 | ||
c8149df0 | 459 | mmc_0: mmc@12200000 { |
906fd84e YK |
460 | compatible = "samsung,exynos5250-dw-mshc"; |
461 | interrupts = <0 75 0>; | |
462 | #address-cells = <1>; | |
463 | #size-cells = <0>; | |
84bd48a0 | 464 | reg = <0x12200000 0x1000>; |
fe273c3e | 465 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
2de6847c | 466 | clock-names = "biu", "ciu"; |
46285a90 | 467 | fifo-depth = <0x80>; |
e908d5c5 | 468 | status = "disabled"; |
84bd48a0 TA |
469 | }; |
470 | ||
c8149df0 | 471 | mmc_1: mmc@12210000 { |
906fd84e YK |
472 | compatible = "samsung,exynos5250-dw-mshc"; |
473 | interrupts = <0 76 0>; | |
474 | #address-cells = <1>; | |
475 | #size-cells = <0>; | |
84bd48a0 | 476 | reg = <0x12210000 0x1000>; |
fe273c3e | 477 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
2de6847c | 478 | clock-names = "biu", "ciu"; |
46285a90 | 479 | fifo-depth = <0x80>; |
e908d5c5 | 480 | status = "disabled"; |
84bd48a0 TA |
481 | }; |
482 | ||
c8149df0 | 483 | mmc_2: mmc@12220000 { |
906fd84e YK |
484 | compatible = "samsung,exynos5250-dw-mshc"; |
485 | interrupts = <0 77 0>; | |
486 | #address-cells = <1>; | |
487 | #size-cells = <0>; | |
84bd48a0 | 488 | reg = <0x12220000 0x1000>; |
fe273c3e | 489 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
2de6847c | 490 | clock-names = "biu", "ciu"; |
46285a90 | 491 | fifo-depth = <0x80>; |
e908d5c5 | 492 | status = "disabled"; |
84bd48a0 TA |
493 | }; |
494 | ||
c8149df0 | 495 | mmc_3: mmc@12230000 { |
84bd48a0 TA |
496 | compatible = "samsung,exynos5250-dw-mshc"; |
497 | reg = <0x12230000 0x1000>; | |
498 | interrupts = <0 78 0>; | |
499 | #address-cells = <1>; | |
500 | #size-cells = <0>; | |
fe273c3e | 501 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
2de6847c | 502 | clock-names = "biu", "ciu"; |
46285a90 | 503 | fifo-depth = <0x80>; |
e908d5c5 | 504 | status = "disabled"; |
84bd48a0 TA |
505 | }; |
506 | ||
28a48058 | 507 | i2s0: i2s@03830000 { |
64183656 | 508 | compatible = "samsung,s5pv210-i2s"; |
328aee4b | 509 | status = "disabled"; |
a0b5f81e | 510 | reg = <0x03830000 0x100>; |
4c4c7463 PV |
511 | dmas = <&pdma0 10 |
512 | &pdma0 9 | |
513 | &pdma0 8>; | |
514 | dma-names = "tx", "rx", "tx-sec"; | |
916ec47e PV |
515 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
516 | <&clock_audss EXYNOS_I2S_BUS>, | |
517 | <&clock_audss EXYNOS_SCLK_I2S>; | |
518 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
a0b5f81e | 519 | samsung,idma-addr = <0x03000000>; |
f8bfe2b0 TA |
520 | pinctrl-names = "default"; |
521 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
522 | }; |
523 | ||
28a48058 | 524 | i2s1: i2s@12D60000 { |
64183656 | 525 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 526 | status = "disabled"; |
a0b5f81e MB |
527 | reg = <0x12D60000 0x100>; |
528 | dmas = <&pdma1 12 | |
529 | &pdma1 11>; | |
530 | dma-names = "tx", "rx"; | |
fe273c3e | 531 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
916ec47e | 532 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
533 | pinctrl-names = "default"; |
534 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
535 | }; |
536 | ||
28a48058 | 537 | i2s2: i2s@12D70000 { |
64183656 | 538 | compatible = "samsung,s3c6410-i2s"; |
328aee4b | 539 | status = "disabled"; |
a0b5f81e MB |
540 | reg = <0x12D70000 0x100>; |
541 | dmas = <&pdma0 12 | |
542 | &pdma0 11>; | |
543 | dma-names = "tx", "rx"; | |
fe273c3e | 544 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
916ec47e | 545 | clock-names = "iis", "i2s_opclk0"; |
f8bfe2b0 TA |
546 | pinctrl-names = "default"; |
547 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
548 | }; |
549 | ||
0b3dc97e VG |
550 | usb@12000000 { |
551 | compatible = "samsung,exynos5250-dwusb3"; | |
fe273c3e | 552 | clocks = <&clock CLK_USB3>; |
0b3dc97e VG |
553 | clock-names = "usbdrd30"; |
554 | #address-cells = <1>; | |
555 | #size-cells = <1>; | |
556 | ranges; | |
557 | ||
558 | dwc3 { | |
559 | compatible = "synopsys,dwc3"; | |
560 | reg = <0x12000000 0x10000>; | |
561 | interrupts = <0 72 0>; | |
7a4cf0fd VG |
562 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
563 | phy-names = "usb2-phy", "usb3-phy"; | |
896db3b3 VG |
564 | }; |
565 | }; | |
566 | ||
517083f4 VG |
567 | usbdrd_phy: phy@12100000 { |
568 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
569 | reg = <0x12100000 0x100>; | |
570 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
571 | clock-names = "phy", "ref"; | |
572 | samsung,pmu-syscon = <&pmu_system_controller>; | |
573 | #phy-cells = <1>; | |
574 | }; | |
575 | ||
13cbd1e3 VG |
576 | usb@12110000 { |
577 | compatible = "samsung,exynos4210-ehci"; | |
578 | reg = <0x12110000 0x100>; | |
579 | interrupts = <0 71 0>; | |
b3cd7d87 | 580 | |
fe273c3e | 581 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 582 | clock-names = "usbhost"; |
dba2f058 KD |
583 | #address-cells = <1>; |
584 | #size-cells = <0>; | |
585 | port@0 { | |
586 | reg = <0>; | |
587 | phys = <&usb2_phy_gen 1>; | |
588 | }; | |
13cbd1e3 VG |
589 | }; |
590 | ||
7d40d867 VG |
591 | usb@12120000 { |
592 | compatible = "samsung,exynos4210-ohci"; | |
593 | reg = <0x12120000 0x100>; | |
594 | interrupts = <0 71 0>; | |
b3cd7d87 | 595 | |
fe273c3e | 596 | clocks = <&clock CLK_USB2>; |
b3cd7d87 | 597 | clock-names = "usbhost"; |
dba2f058 KD |
598 | #address-cells = <1>; |
599 | #size-cells = <0>; | |
600 | port@0 { | |
601 | reg = <0>; | |
602 | phys = <&usb2_phy_gen 1>; | |
603 | }; | |
7d40d867 VG |
604 | }; |
605 | ||
0b3dc97e | 606 | usb2_phy: usbphy@12130000 { |
7ec892ef VG |
607 | compatible = "samsung,exynos5250-usb2phy"; |
608 | reg = <0x12130000 0x100>; | |
fe273c3e | 609 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; |
7ec892ef VG |
610 | clock-names = "ext_xtal", "usbhost"; |
611 | #address-cells = <1>; | |
612 | #size-cells = <1>; | |
613 | ranges; | |
614 | ||
615 | usbphy-sys { | |
616 | reg = <0x10040704 0x8>, | |
617 | <0x10050230 0x4>; | |
618 | }; | |
619 | }; | |
620 | ||
dba2f058 KD |
621 | usb2_phy_gen: phy@12130000 { |
622 | compatible = "samsung,exynos5250-usb2-phy"; | |
623 | reg = <0x12130000 0x100>; | |
624 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
625 | clock-names = "phy", "ref"; | |
626 | #phy-cells = <1>; | |
627 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
628 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
629 | }; | |
630 | ||
022cf308 LKA |
631 | pwm: pwm@12dd0000 { |
632 | compatible = "samsung,exynos4210-pwm"; | |
633 | reg = <0x12dd0000 0x100>; | |
634 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
635 | #pwm-cells = <3>; | |
fe273c3e | 636 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
637 | clock-names = "timers"; |
638 | }; | |
639 | ||
b074abb7 KK |
640 | amba { |
641 | #address-cells = <1>; | |
642 | #size-cells = <1>; | |
643 | compatible = "arm,amba-bus"; | |
644 | interrupt-parent = <&gic>; | |
645 | ranges; | |
646 | ||
647 | pdma0: pdma@121A0000 { | |
648 | compatible = "arm,pl330", "arm,primecell"; | |
649 | reg = <0x121A0000 0x1000>; | |
650 | interrupts = <0 34 0>; | |
fe273c3e | 651 | clocks = <&clock CLK_PDMA0>; |
2de6847c | 652 | clock-names = "apb_pclk"; |
42cf2098 PV |
653 | #dma-cells = <1>; |
654 | #dma-channels = <8>; | |
655 | #dma-requests = <32>; | |
b074abb7 KK |
656 | }; |
657 | ||
658 | pdma1: pdma@121B0000 { | |
659 | compatible = "arm,pl330", "arm,primecell"; | |
660 | reg = <0x121B0000 0x1000>; | |
661 | interrupts = <0 35 0>; | |
fe273c3e | 662 | clocks = <&clock CLK_PDMA1>; |
2de6847c | 663 | clock-names = "apb_pclk"; |
42cf2098 PV |
664 | #dma-cells = <1>; |
665 | #dma-channels = <8>; | |
666 | #dma-requests = <32>; | |
b074abb7 KK |
667 | }; |
668 | ||
009f7c9f | 669 | mdma0: mdma@10800000 { |
b074abb7 KK |
670 | compatible = "arm,pl330", "arm,primecell"; |
671 | reg = <0x10800000 0x1000>; | |
672 | interrupts = <0 33 0>; | |
fe273c3e | 673 | clocks = <&clock CLK_MDMA0>; |
2de6847c | 674 | clock-names = "apb_pclk"; |
42cf2098 PV |
675 | #dma-cells = <1>; |
676 | #dma-channels = <8>; | |
677 | #dma-requests = <1>; | |
b074abb7 KK |
678 | }; |
679 | ||
009f7c9f | 680 | mdma1: mdma@11C10000 { |
b074abb7 KK |
681 | compatible = "arm,pl330", "arm,primecell"; |
682 | reg = <0x11C10000 0x1000>; | |
683 | interrupts = <0 124 0>; | |
fe273c3e | 684 | clocks = <&clock CLK_MDMA1>; |
2de6847c | 685 | clock-names = "apb_pclk"; |
42cf2098 PV |
686 | #dma-cells = <1>; |
687 | #dma-channels = <8>; | |
688 | #dma-requests = <1>; | |
b074abb7 KK |
689 | }; |
690 | }; | |
691 | ||
c31f566d | 692 | gsc_0: gsc@13e00000 { |
1128658a SAB |
693 | compatible = "samsung,exynos5-gsc"; |
694 | reg = <0x13e00000 0x1000>; | |
695 | interrupts = <0 85 0>; | |
6f9e95e6 | 696 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 697 | clocks = <&clock CLK_GSCL0>; |
2de6847c | 698 | clock-names = "gscl"; |
1128658a SAB |
699 | }; |
700 | ||
c31f566d | 701 | gsc_1: gsc@13e10000 { |
1128658a SAB |
702 | compatible = "samsung,exynos5-gsc"; |
703 | reg = <0x13e10000 0x1000>; | |
704 | interrupts = <0 86 0>; | |
6f9e95e6 | 705 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 706 | clocks = <&clock CLK_GSCL1>; |
2de6847c | 707 | clock-names = "gscl"; |
1128658a SAB |
708 | }; |
709 | ||
c31f566d | 710 | gsc_2: gsc@13e20000 { |
1128658a SAB |
711 | compatible = "samsung,exynos5-gsc"; |
712 | reg = <0x13e20000 0x1000>; | |
713 | interrupts = <0 87 0>; | |
6f9e95e6 | 714 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 715 | clocks = <&clock CLK_GSCL2>; |
2de6847c | 716 | clock-names = "gscl"; |
1128658a SAB |
717 | }; |
718 | ||
c31f566d | 719 | gsc_3: gsc@13e30000 { |
1128658a SAB |
720 | compatible = "samsung,exynos5-gsc"; |
721 | reg = <0x13e30000 0x1000>; | |
722 | interrupts = <0 88 0>; | |
6f9e95e6 | 723 | samsung,power-domain = <&pd_gsc>; |
fe273c3e | 724 | clocks = <&clock CLK_GSCL3>; |
2de6847c | 725 | clock-names = "gscl"; |
1128658a | 726 | }; |
566cf8ee RS |
727 | |
728 | hdmi { | |
0d1fc829 | 729 | compatible = "samsung,exynos4212-hdmi"; |
101250ce | 730 | reg = <0x14530000 0x70000>; |
566cf8ee | 731 | interrupts = <0 95 0>; |
fe273c3e AH |
732 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
733 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
734 | <&clock CLK_MOUT_HDMI>; | |
2de6847c | 735 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
27c16d19 | 736 | "sclk_hdmiphy", "mout_hdmi"; |
e54d90ec | 737 | samsung,syscon-phandle = <&pmu_system_controller>; |
566cf8ee | 738 | }; |
5af0d8a3 RS |
739 | |
740 | mixer { | |
0d1fc829 | 741 | compatible = "samsung,exynos5250-mixer"; |
5af0d8a3 RS |
742 | reg = <0x14450000 0x10000>; |
743 | interrupts = <0 94 0>; | |
fe273c3e | 744 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
18fe6ef0 | 745 | clock-names = "mixer", "sclk_hdmi"; |
5af0d8a3 | 746 | }; |
ad4aebe1 | 747 | |
77899d53 VS |
748 | dp_phy: video-phy@10040720 { |
749 | compatible = "samsung,exynos5250-dp-video-phy"; | |
750 | reg = <0x10040720 4>; | |
751 | #phy-cells = <0>; | |
752 | }; | |
753 | ||
754 | dp-controller@145B0000 { | |
fe273c3e | 755 | clocks = <&clock CLK_DP>; |
0f72a9ec | 756 | clock-names = "dp"; |
77899d53 VS |
757 | phys = <&dp_phy>; |
758 | phy-names = "dp"; | |
ad4aebe1 | 759 | }; |
a7389cb1 | 760 | |
9ee35a5b | 761 | fimd@14400000 { |
fe273c3e | 762 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
a7389cb1 LKA |
763 | clock-names = "sclk_fimd", "fimd"; |
764 | }; | |
f408f9db NKC |
765 | |
766 | adc: adc@12D10000 { | |
767 | compatible = "samsung,exynos-adc-v1"; | |
768 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; | |
769 | interrupts = <0 106 0>; | |
fe273c3e | 770 | clocks = <&clock CLK_ADC>; |
f408f9db NKC |
771 | clock-names = "adc"; |
772 | #io-channel-cells = <1>; | |
773 | io-channel-ranges; | |
774 | status = "disabled"; | |
775 | }; | |
183af252 NKC |
776 | |
777 | sss@10830000 { | |
778 | compatible = "samsung,exynos4210-secss"; | |
779 | reg = <0x10830000 0x10000>; | |
780 | interrupts = <0 112 0>; | |
e06e1067 | 781 | clocks = <&clock CLK_SSS>; |
183af252 NKC |
782 | clock-names = "secss"; |
783 | }; | |
b074abb7 | 784 | }; |