projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 34dcedfb CK |
1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
| 8 | * EXYNOS5420 based board files can include this file and provide | |
| 9 | * values for board specfic bindings. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License version 2 as | |
| 13 | * published by the Free Software Foundation. | |
| 14 | */ | |
| 15 | ||
| 16 | #include "exynos5.dtsi" | |
| 0bd03f6f | 17 | #include "exynos5420-pinctrl.dtsi" |
| 35e82775 AB |
18 | |
| 19 | #include <dt-bindings/clk/exynos-audss-clk.h> | |
| 20 | ||
| 34dcedfb CK |
21 | / { |
| 22 | compatible = "samsung,exynos5420"; | |
| 23 | ||
| d81c6cbe LKA |
24 | aliases { |
| 25 | pinctrl0 = &pinctrl_0; | |
| 26 | pinctrl1 = &pinctrl_1; | |
| 27 | pinctrl2 = &pinctrl_2; | |
| 28 | pinctrl3 = &pinctrl_3; | |
| 29 | pinctrl4 = &pinctrl_4; | |
| f49e347b AB |
30 | i2c0 = &i2c_0; |
| 31 | i2c1 = &i2c_1; | |
| 32 | i2c2 = &i2c_2; | |
| 33 | i2c3 = &i2c_3; | |
| d81c6cbe LKA |
34 | }; |
| 35 | ||
| 34dcedfb CK |
36 | cpus { |
| 37 | #address-cells = <1>; | |
| 38 | #size-cells = <0>; | |
| 39 | ||
| 40 | cpu0: cpu@0 { | |
| 41 | device_type = "cpu"; | |
| 42 | compatible = "arm,cortex-a15"; | |
| 43 | reg = <0x0>; | |
| 44 | clock-frequency = <1800000000>; | |
| 45 | }; | |
| 46 | ||
| 47 | cpu1: cpu@1 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a15"; | |
| 50 | reg = <0x1>; | |
| 51 | clock-frequency = <1800000000>; | |
| 52 | }; | |
| 53 | ||
| 54 | cpu2: cpu@2 { | |
| 55 | device_type = "cpu"; | |
| 56 | compatible = "arm,cortex-a15"; | |
| 57 | reg = <0x2>; | |
| 58 | clock-frequency = <1800000000>; | |
| 59 | }; | |
| 60 | ||
| 61 | cpu3: cpu@3 { | |
| 62 | device_type = "cpu"; | |
| 63 | compatible = "arm,cortex-a15"; | |
| 64 | reg = <0x3>; | |
| 65 | clock-frequency = <1800000000>; | |
| 66 | }; | |
| 67 | }; | |
| 68 | ||
| 92040bd6 | 69 | clock: clock-controller@10010000 { |
| 34dcedfb CK |
70 | compatible = "samsung,exynos5420-clock"; |
| 71 | reg = <0x10010000 0x30000>; | |
| 72 | #clock-cells = <1>; | |
| 73 | }; | |
| 74 | ||
| 35e82775 AB |
75 | clock_audss: audss-clock-controller@3810000 { |
| 76 | compatible = "samsung,exynos5420-audss-clock"; | |
| 77 | reg = <0x03810000 0x0C>; | |
| 78 | #clock-cells = <1>; | |
| 79 | clocks = <&clock 148>; | |
| 80 | clock-names = "sclk_audio"; | |
| 81 | }; | |
| 82 | ||
| f09d062f AK |
83 | codec@11000000 { |
| 84 | compatible = "samsung,mfc-v7"; | |
| 85 | reg = <0x11000000 0x10000>; | |
| 86 | interrupts = <0 96 0>; | |
| 87 | clocks = <&clock 401>; | |
| 88 | clock-names = "mfc"; | |
| 89 | }; | |
| 90 | ||
| 34dcedfb CK |
91 | mct@101C0000 { |
| 92 | compatible = "samsung,exynos4210-mct"; | |
| 93 | reg = <0x101C0000 0x800>; | |
| 94 | interrupt-controller; | |
| 95 | #interrups-cells = <1>; | |
| 96 | interrupt-parent = <&mct_map>; | |
| 97 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; | |
| 98 | clocks = <&clock 1>, <&clock 315>; | |
| 99 | clock-names = "fin_pll", "mct"; | |
| 100 | ||
| 101 | mct_map: mct-map { | |
| 102 | #interrupt-cells = <1>; | |
| 103 | #address-cells = <0>; | |
| 104 | #size-cells = <0>; | |
| 105 | interrupt-map = <0 &combiner 23 3>, | |
| 106 | <1 &combiner 23 4>, | |
| 107 | <2 &combiner 25 2>, | |
| 108 | <3 &combiner 25 3>, | |
| 109 | <4 &gic 0 120 0>, | |
| 110 | <5 &gic 0 121 0>, | |
| 111 | <6 &gic 0 122 0>, | |
| 112 | <7 &gic 0 123 0>; | |
| 113 | }; | |
| 114 | }; | |
| 115 | ||
| dcfca2cc YSB |
116 | gsc_pd: power-domain@10044000 { |
| 117 | compatible = "samsung,exynos4210-pd"; | |
| 118 | reg = <0x10044000 0x20>; | |
| 119 | }; | |
| 120 | ||
| 121 | isp_pd: power-domain@10044020 { | |
| 122 | compatible = "samsung,exynos4210-pd"; | |
| 123 | reg = <0x10044020 0x20>; | |
| 124 | }; | |
| 125 | ||
| 126 | mfc_pd: power-domain@10044060 { | |
| 127 | compatible = "samsung,exynos4210-pd"; | |
| 128 | reg = <0x10044060 0x20>; | |
| 129 | }; | |
| 130 | ||
| 131 | disp_pd: power-domain@100440C0 { | |
| 132 | compatible = "samsung,exynos4210-pd"; | |
| 133 | reg = <0x100440C0 0x20>; | |
| 134 | }; | |
| 135 | ||
| 136 | mau_pd: power-domain@100440E0 { | |
| 137 | compatible = "samsung,exynos4210-pd"; | |
| 138 | reg = <0x100440E0 0x20>; | |
| 139 | }; | |
| 140 | ||
| 141 | g2d_pd: power-domain@10044100 { | |
| 142 | compatible = "samsung,exynos4210-pd"; | |
| 143 | reg = <0x10044100 0x20>; | |
| 144 | }; | |
| 145 | ||
| 146 | msc_pd: power-domain@10044120 { | |
| 147 | compatible = "samsung,exynos4210-pd"; | |
| 148 | reg = <0x10044120 0x20>; | |
| 149 | }; | |
| 150 | ||
| d81c6cbe LKA |
151 | pinctrl_0: pinctrl@13400000 { |
| 152 | compatible = "samsung,exynos5420-pinctrl"; | |
| 153 | reg = <0x13400000 0x1000>; | |
| 154 | interrupts = <0 45 0>; | |
| 155 | ||
| 156 | wakeup-interrupt-controller { | |
| 157 | compatible = "samsung,exynos4210-wakeup-eint"; | |
| 158 | interrupt-parent = <&gic>; | |
| 159 | interrupts = <0 32 0>; | |
| 160 | }; | |
| 161 | }; | |
| 162 | ||
| 163 | pinctrl_1: pinctrl@13410000 { | |
| 164 | compatible = "samsung,exynos5420-pinctrl"; | |
| 165 | reg = <0x13410000 0x1000>; | |
| 166 | interrupts = <0 78 0>; | |
| 167 | }; | |
| 168 | ||
| 169 | pinctrl_2: pinctrl@14000000 { | |
| 170 | compatible = "samsung,exynos5420-pinctrl"; | |
| 171 | reg = <0x14000000 0x1000>; | |
| 172 | interrupts = <0 46 0>; | |
| 173 | }; | |
| 174 | ||
| 175 | pinctrl_3: pinctrl@14010000 { | |
| 176 | compatible = "samsung,exynos5420-pinctrl"; | |
| 177 | reg = <0x14010000 0x1000>; | |
| 178 | interrupts = <0 50 0>; | |
| 179 | }; | |
| 180 | ||
| 181 | pinctrl_4: pinctrl@03860000 { | |
| 182 | compatible = "samsung,exynos5420-pinctrl"; | |
| 183 | reg = <0x03860000 0x1000>; | |
| 184 | interrupts = <0 47 0>; | |
| 185 | }; | |
| 186 | ||
| a81951d9 VS |
187 | rtc@101E0000 { |
| 188 | clocks = <&clock 317>; | |
| 189 | clock-names = "rtc"; | |
| 190 | status = "okay"; | |
| 191 | }; | |
| 192 | ||
| 34dcedfb CK |
193 | serial@12C00000 { |
| 194 | clocks = <&clock 257>, <&clock 128>; | |
| 195 | clock-names = "uart", "clk_uart_baud0"; | |
| 196 | }; | |
| 197 | ||
| 198 | serial@12C10000 { | |
| 199 | clocks = <&clock 258>, <&clock 129>; | |
| 200 | clock-names = "uart", "clk_uart_baud0"; | |
| 201 | }; | |
| 202 | ||
| 203 | serial@12C20000 { | |
| 204 | clocks = <&clock 259>, <&clock 130>; | |
| 205 | clock-names = "uart", "clk_uart_baud0"; | |
| 206 | }; | |
| 207 | ||
| 208 | serial@12C30000 { | |
| 209 | clocks = <&clock 260>, <&clock 131>; | |
| 210 | clock-names = "uart", "clk_uart_baud0"; | |
| 211 | }; | |
| ee3381d4 | 212 | |
| 1339d33a VS |
213 | dp_phy: video-phy@10040728 { |
| 214 | compatible = "samsung,exynos5250-dp-video-phy"; | |
| 215 | reg = <0x10040728 4>; | |
| 216 | #phy-cells = <0>; | |
| 217 | }; | |
| 218 | ||
| 219 | dp-controller@145B0000 { | |
| 220 | clocks = <&clock 412>; | |
| 221 | clock-names = "dp"; | |
| 222 | phys = <&dp_phy>; | |
| 223 | phy-names = "dp"; | |
| 224 | }; | |
| 225 | ||
| ee3381d4 VS |
226 | fimd@14400000 { |
| 227 | samsung,power-domain = <&disp_pd>; | |
| 228 | clocks = <&clock 147>, <&clock 421>; | |
| 229 | clock-names = "sclk_fimd", "fimd"; | |
| 230 | }; | |
| f408f9db NKC |
231 | |
| 232 | adc: adc@12D10000 { | |
| 233 | compatible = "samsung,exynos-adc-v2"; | |
| 234 | reg = <0x12D10000 0x100>, <0x10040720 0x4>; | |
| 235 | interrupts = <0 106 0>; | |
| 236 | clocks = <&clock 270>; | |
| 237 | clock-names = "adc"; | |
| 238 | #io-channel-cells = <1>; | |
| 239 | io-channel-ranges; | |
| 240 | status = "disabled"; | |
| 241 | }; | |
| f49e347b AB |
242 | |
| 243 | i2c_0: i2c@12C60000 { | |
| 244 | compatible = "samsung,s3c2440-i2c"; | |
| 245 | reg = <0x12C60000 0x100>; | |
| 246 | interrupts = <0 56 0>; | |
| 247 | #address-cells = <1>; | |
| 248 | #size-cells = <0>; | |
| 249 | clocks = <&clock 261>; | |
| 250 | clock-names = "i2c"; | |
| 251 | pinctrl-names = "default"; | |
| 252 | pinctrl-0 = <&i2c0_bus>; | |
| 253 | status = "disabled"; | |
| 254 | }; | |
| 255 | ||
| 256 | i2c_1: i2c@12C70000 { | |
| 257 | compatible = "samsung,s3c2440-i2c"; | |
| 258 | reg = <0x12C70000 0x100>; | |
| 259 | interrupts = <0 57 0>; | |
| 260 | #address-cells = <1>; | |
| 261 | #size-cells = <0>; | |
| 262 | clocks = <&clock 262>; | |
| 263 | clock-names = "i2c"; | |
| 264 | pinctrl-names = "default"; | |
| 265 | pinctrl-0 = <&i2c1_bus>; | |
| 266 | status = "disabled"; | |
| 267 | }; | |
| 268 | ||
| 269 | i2c_2: i2c@12C80000 { | |
| 270 | compatible = "samsung,s3c2440-i2c"; | |
| 271 | reg = <0x12C80000 0x100>; | |
| 272 | interrupts = <0 58 0>; | |
| 273 | #address-cells = <1>; | |
| 274 | #size-cells = <0>; | |
| 275 | clocks = <&clock 263>; | |
| 276 | clock-names = "i2c"; | |
| 277 | pinctrl-names = "default"; | |
| 278 | pinctrl-0 = <&i2c2_bus>; | |
| 279 | status = "disabled"; | |
| 280 | }; | |
| 281 | ||
| 282 | i2c_3: i2c@12C90000 { | |
| 283 | compatible = "samsung,s3c2440-i2c"; | |
| 284 | reg = <0x12C90000 0x100>; | |
| 285 | interrupts = <0 59 0>; | |
| 286 | #address-cells = <1>; | |
| 287 | #size-cells = <0>; | |
| 288 | clocks = <&clock 264>; | |
| 289 | clock-names = "i2c"; | |
| 290 | pinctrl-names = "default"; | |
| 291 | pinctrl-0 = <&i2c3_bus>; | |
| 292 | status = "disabled"; | |
| 293 | }; | |
| b0e505ce RS |
294 | |
| 295 | hdmi@14530000 { | |
| 296 | compatible = "samsung,exynos4212-hdmi"; | |
| 297 | reg = <0x14530000 0x70000>; | |
| 298 | interrupts = <0 95 0>; | |
| 299 | clocks = <&clock 413>, <&clock 143>, <&clock 768>, | |
| 300 | <&clock 158>, <&clock 640>; | |
| 301 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
| 302 | "sclk_hdmiphy", "mout_hdmi"; | |
| 303 | status = "disabled"; | |
| 304 | }; | |
| 305 | ||
| 306 | mixer@14450000 { | |
| 307 | compatible = "samsung,exynos5420-mixer"; | |
| 308 | reg = <0x14450000 0x10000>; | |
| 309 | interrupts = <0 94 0>; | |
| 310 | clocks = <&clock 431>, <&clock 143>; | |
| 311 | clock-names = "mixer", "sclk_hdmi"; | |
| 312 | }; | |
| 34dcedfb | 313 | }; |