projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| df09df6f CP |
1 | /* |
| 2 | * SAMSUNG EXYNOS5422 SoC cpu device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The | |
| 8 | * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting | |
| 9 | * from Cortex-A15 core. | |
| 10 | * | |
| 11 | * EXYNOS5422 based board files can include this file to provide cpu ordering | |
| 12 | * which could boot a cortex-a7 from cpu0. | |
| 13 | * | |
| 14 | * This program is free software; you can redistribute it and/or modify | |
| 15 | * it under the terms of the GNU General Public License version 2 as | |
| 16 | * published by the Free Software Foundation. | |
| 17 | */ | |
| 18 | ||
| 19 | &cpu0 { | |
| 20 | device_type = "cpu"; | |
| 21 | compatible = "arm,cortex-a7"; | |
| 22 | reg = <0x100>; | |
| 23 | clock-frequency = <1000000000>; | |
| 24 | cci-control-port = <&cci_control0>; | |
| 25 | }; | |
| 26 | ||
| 27 | &cpu1 { | |
| 28 | device_type = "cpu"; | |
| 29 | compatible = "arm,cortex-a7"; | |
| 30 | reg = <0x101>; | |
| 31 | clock-frequency = <1000000000>; | |
| 32 | cci-control-port = <&cci_control0>; | |
| 33 | }; | |
| 34 | ||
| 35 | &cpu2 { | |
| 36 | device_type = "cpu"; | |
| 37 | compatible = "arm,cortex-a7"; | |
| 38 | reg = <0x102>; | |
| 39 | clock-frequency = <1000000000>; | |
| 40 | cci-control-port = <&cci_control0>; | |
| 41 | }; | |
| 42 | ||
| 43 | &cpu3 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "arm,cortex-a7"; | |
| 46 | reg = <0x103>; | |
| 47 | clock-frequency = <1000000000>; | |
| 48 | cci-control-port = <&cci_control0>; | |
| 49 | }; | |
| 50 | ||
| 51 | &cpu4 { | |
| 52 | device_type = "cpu"; | |
| 53 | compatible = "arm,cortex-a15"; | |
| 54 | reg = <0x0>; | |
| 55 | clock-frequency = <1800000000>; | |
| 56 | cci-control-port = <&cci_control1>; | |
| 57 | }; | |
| 58 | ||
| 59 | &cpu5 { | |
| 60 | device_type = "cpu"; | |
| 61 | compatible = "arm,cortex-a15"; | |
| 62 | reg = <0x1>; | |
| 63 | clock-frequency = <1800000000>; | |
| 64 | cci-control-port = <&cci_control1>; | |
| 65 | }; | |
| 66 | ||
| 67 | &cpu6 { | |
| 68 | device_type = "cpu"; | |
| 69 | compatible = "arm,cortex-a15"; | |
| 70 | reg = <0x2>; | |
| 71 | clock-frequency = <1800000000>; | |
| 72 | cci-control-port = <&cci_control1>; | |
| 73 | }; | |
| 74 | ||
| 75 | &cpu7 { | |
| 76 | device_type = "cpu"; | |
| 77 | compatible = "arm,cortex-a15"; | |
| 78 | reg = <0x3>; | |
| 79 | clock-frequency = <1800000000>; | |
| 80 | cci-control-port = <&cci_control1>; | |
| 81 | }; |