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acc3329e AS |
1 | /* |
2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | #include "imx1.dtsi" | |
14 | ||
15 | / { | |
16 | model = "Armadeus APF9328"; | |
17 | compatible = "armadeus,imx1-apf9328", "fsl,imx1"; | |
18 | ||
19 | chosen { | |
20 | stdout-path = &uart1; | |
21 | }; | |
22 | ||
23 | memory { | |
24 | reg = <0x08000000 0x00800000>; | |
25 | }; | |
26 | }; | |
27 | ||
28 | &i2c { | |
29 | pinctrl-names = "default"; | |
30 | pinctrl-0 = <&pinctrl_i2c>; | |
31 | status = "okay"; | |
32 | }; | |
33 | ||
34 | &uart1 { | |
35 | pinctrl-names = "default"; | |
36 | pinctrl-0 = <&pinctrl_uart1>; | |
37 | fsl,uart-has-rtscts; | |
38 | status = "okay"; | |
39 | }; | |
40 | ||
41 | &uart2 { | |
42 | pinctrl-names = "default"; | |
43 | pinctrl-0 = <&pinctrl_uart2>; | |
44 | fsl,uart-has-rtscts; | |
45 | status = "okay"; | |
46 | }; | |
47 | ||
48 | &weim { | |
49 | pinctrl-names = "default"; | |
50 | pinctrl-0 = <&pinctrl_weim>; | |
51 | status = "okay"; | |
52 | ||
53 | nor: nor@0,0 { | |
54 | compatible = "cfi-flash"; | |
55 | reg = <0 0x00000000 0x02000000>; | |
56 | bank-width = <2>; | |
57 | fsl,weim-cs-timing = <0x00330e04 0x00000d01>; | |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | }; | |
61 | ||
62 | eth: eth@4,c00000 { | |
63 | pinctrl-names = "default"; | |
64 | pinctrl-0 = <&pinctrl_eth>; | |
65 | compatible = "davicom,dm9000"; | |
66 | reg = < | |
67 | 4 0x00c00000 0x2 | |
68 | 4 0x00c00002 0x2 | |
69 | >; | |
70 | interrupt-parent = <&gpio2>; | |
71 | interrupts = <14 IRQ_TYPE_LEVEL_LOW>; | |
72 | fsl,weim-cs-timing = <0x0000c700 0x19190d01>; | |
73 | }; | |
74 | }; | |
75 | ||
76 | &iomuxc { | |
77 | imx1-apf9328 { | |
78 | pinctrl_eth: ethgrp { | |
79 | fsl,pins = < | |
80 | MX1_PAD_SIM_SVEN__GPIO2_14 0x0 | |
81 | >; | |
82 | }; | |
83 | ||
84 | pinctrl_i2c: i2cgrp { | |
85 | fsl,pins = < | |
86 | MX1_PAD_I2C_SCL__I2C_SCL 0x0 | |
87 | MX1_PAD_I2C_SDA__I2C_SDA 0x0 | |
88 | >; | |
89 | }; | |
90 | ||
91 | pinctrl_uart1: uart1grp { | |
92 | fsl,pins = < | |
93 | MX1_PAD_UART1_TXD__UART1_TXD 0x0 | |
94 | MX1_PAD_UART1_RXD__UART1_RXD 0x0 | |
95 | MX1_PAD_UART1_CTS__UART1_CTS 0x0 | |
96 | MX1_PAD_UART1_RTS__UART1_RTS 0x0 | |
97 | >; | |
98 | }; | |
99 | ||
100 | pinctrl_uart2: uart2grp { | |
101 | fsl,pins = < | |
102 | MX1_PAD_UART2_TXD__UART2_TXD 0x0 | |
103 | MX1_PAD_UART2_RXD__UART2_RXD 0x0 | |
104 | MX1_PAD_UART2_CTS__UART2_CTS 0x0 | |
105 | MX1_PAD_UART2_RTS__UART2_RTS 0x0 | |
106 | >; | |
107 | }; | |
108 | ||
109 | pinctrl_weim: weimgrp { | |
110 | fsl,pins = < | |
111 | MX1_PAD_A0__A0 0x0 | |
112 | MX1_PAD_A16__A16 0x0 | |
113 | MX1_PAD_A17__A17 0x0 | |
114 | MX1_PAD_A18__A18 0x0 | |
115 | MX1_PAD_A19__A19 0x0 | |
116 | MX1_PAD_A20__A20 0x0 | |
117 | MX1_PAD_A21__A21 0x0 | |
118 | MX1_PAD_A22__A22 0x0 | |
119 | MX1_PAD_A23__A23 0x0 | |
120 | MX1_PAD_A24__A24 0x0 | |
121 | MX1_PAD_BCLK__BCLK 0x0 | |
122 | MX1_PAD_CS4__CS4 0x0 | |
123 | MX1_PAD_DTACK__DTACK 0x0 | |
124 | MX1_PAD_ECB__ECB 0x0 | |
125 | MX1_PAD_LBA__LBA 0x0 | |
126 | >; | |
127 | }; | |
128 | }; | |
129 | }; |