Commit | Line | Data |
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c05c1bf5 AS |
1 | /* |
2 | * The code contained herein is licensed under the GNU General Public | |
3 | * License. You may obtain a copy of the GNU General Public License | |
4 | * Version 2 or later at the following locations: | |
5 | * | |
6 | * http://www.opensource.org/licenses/gpl-license.html | |
7 | * http://www.gnu.org/copyleft/gpl.html | |
8 | */ | |
9 | ||
e3da3d21 | 10 | #include "imx27-phytec-phycore-som.dtsi" |
c05c1bf5 AS |
11 | |
12 | / { | |
13 | model = "Phytec pcm970"; | |
14 | compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; | |
8994181a AS |
15 | |
16 | display0: LQ035Q7 { | |
17 | model = "Sharp-LQ035Q7"; | |
18 | native-mode = <&timing0>; | |
19 | bits-per-pixel = <16>; | |
20 | fsl,pcr = <0xf00080c0>; | |
21 | ||
22 | display-timings { | |
23 | timing0: 240x320 { | |
24 | clock-frequency = <5500000>; | |
25 | hactive = <240>; | |
26 | vactive = <320>; | |
27 | hback-porch = <5>; | |
28 | hsync-len = <7>; | |
29 | hfront-porch = <16>; | |
30 | vback-porch = <7>; | |
31 | vsync-len = <1>; | |
32 | vfront-porch = <9>; | |
6a21e4bb AS |
33 | pixelclk-active = <1>; |
34 | hsync-active = <1>; | |
35 | vsync-active = <1>; | |
36 | de-active = <0>; | |
8994181a AS |
37 | }; |
38 | }; | |
39 | }; | |
c05c1bf5 AS |
40 | }; |
41 | ||
42 | &cspi1 { | |
e8e8d621 | 43 | pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; |
c05c1bf5 | 44 | fsl,spi-num-chipselects = <2>; |
6ece55b3 AS |
45 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, |
46 | <&gpio4 27 GPIO_ACTIVE_LOW>; | |
c05c1bf5 AS |
47 | }; |
48 | ||
8994181a AS |
49 | &fb { |
50 | pinctrl-names = "default"; | |
51 | pinctrl-0 = <&pinctrl_imxfb1>; | |
52 | display = <&display0>; | |
53 | lcd-supply = <®_5v0>; | |
54 | fsl,dmacr = <0x00020010>; | |
55 | fsl,lscr1 = <0x00120300>; | |
56 | fsl,lpccr = <0x00a903ff>; | |
57 | status = "okay"; | |
58 | }; | |
59 | ||
5f9fe244 AS |
60 | &i2c1 { |
61 | clock-frequency = <400000>; | |
62 | pinctrl-names = "default"; | |
63 | pinctrl-0 = <&pinctrl_i2c1>; | |
64 | status = "okay"; | |
65 | ||
66 | camgpio: pca9536@41 { | |
67 | compatible = "nxp,pca9536"; | |
68 | reg = <0x41>; | |
69 | gpio-controller; | |
70 | #gpio-cells = <2>; | |
71 | }; | |
72 | }; | |
73 | ||
26508cb7 MP |
74 | &iomuxc { |
75 | imx27_phycore_rdk { | |
e8e8d621 AS |
76 | pinctrl_cspi1cs1: cspi1cs1grp { |
77 | fsl,pins = < | |
78 | MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 | |
79 | >; | |
80 | }; | |
81 | ||
8994181a AS |
82 | pinctrl_imxfb1: imxfbgrp { |
83 | fsl,pins = < | |
84 | MX27_PAD_LD0__LD0 0x0 | |
85 | MX27_PAD_LD1__LD1 0x0 | |
86 | MX27_PAD_LD2__LD2 0x0 | |
87 | MX27_PAD_LD3__LD3 0x0 | |
88 | MX27_PAD_LD4__LD4 0x0 | |
89 | MX27_PAD_LD5__LD5 0x0 | |
90 | MX27_PAD_LD6__LD6 0x0 | |
91 | MX27_PAD_LD7__LD7 0x0 | |
92 | MX27_PAD_LD8__LD8 0x0 | |
93 | MX27_PAD_LD9__LD9 0x0 | |
94 | MX27_PAD_LD10__LD10 0x0 | |
95 | MX27_PAD_LD11__LD11 0x0 | |
96 | MX27_PAD_LD12__LD12 0x0 | |
97 | MX27_PAD_LD13__LD13 0x0 | |
98 | MX27_PAD_LD14__LD14 0x0 | |
99 | MX27_PAD_LD15__LD15 0x0 | |
100 | MX27_PAD_LD16__LD16 0x0 | |
101 | MX27_PAD_LD17__LD17 0x0 | |
102 | MX27_PAD_CLS__CLS 0x0 | |
103 | MX27_PAD_CONTRAST__CONTRAST 0x0 | |
104 | MX27_PAD_LSCLK__LSCLK 0x0 | |
105 | MX27_PAD_OE_ACD__OE_ACD 0x0 | |
106 | MX27_PAD_PS__PS 0x0 | |
107 | MX27_PAD_REV__REV 0x0 | |
108 | MX27_PAD_SPL_SPR__SPL_SPR 0x0 | |
109 | MX27_PAD_HSYNC__HSYNC 0x0 | |
110 | MX27_PAD_VSYNC__VSYNC 0x0 | |
111 | >; | |
112 | }; | |
113 | ||
5f9fe244 AS |
114 | pinctrl_i2c1: i2c1grp { |
115 | /* Add pullup to DATA line */ | |
116 | fsl,pins = < | |
117 | MX27_PAD_I2C_DATA__I2C_DATA 0x1 | |
118 | MX27_PAD_I2C_CLK__I2C_CLK 0x0 | |
119 | >; | |
120 | }; | |
121 | ||
5e01e585 AS |
122 | pinctrl_owire1: owire1grp { |
123 | fsl,pins = < | |
124 | MX27_PAD_RTCK__OWIRE 0x0 | |
125 | >; | |
126 | }; | |
127 | ||
836ac783 AS |
128 | pinctrl_sdhc2: sdhc2grp { |
129 | fsl,pins = < | |
130 | MX27_PAD_SD2_CLK__SD2_CLK 0x0 | |
131 | MX27_PAD_SD2_CMD__SD2_CMD 0x0 | |
132 | MX27_PAD_SD2_D0__SD2_D0 0x0 | |
133 | MX27_PAD_SD2_D1__SD2_D1 0x0 | |
134 | MX27_PAD_SD2_D2__SD2_D2 0x0 | |
135 | MX27_PAD_SD2_D3__SD2_D3 0x0 | |
136 | MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ | |
137 | MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ | |
138 | >; | |
139 | }; | |
140 | ||
26508cb7 MP |
141 | pinctrl_uart1: uart1grp { |
142 | fsl,pins = < | |
143 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | |
144 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | |
145 | MX27_PAD_UART1_CTS__UART1_CTS 0x0 | |
146 | MX27_PAD_UART1_RTS__UART1_RTS 0x0 | |
147 | >; | |
148 | }; | |
149 | ||
150 | pinctrl_uart2: uart2grp { | |
151 | fsl,pins = < | |
152 | MX27_PAD_UART2_TXD__UART2_TXD 0x0 | |
153 | MX27_PAD_UART2_RXD__UART2_RXD 0x0 | |
154 | MX27_PAD_UART2_CTS__UART2_CTS 0x0 | |
155 | MX27_PAD_UART2_RTS__UART2_RTS 0x0 | |
156 | >; | |
157 | }; | |
3c6c9eeb | 158 | |
9089ce52 AS |
159 | pinctrl_usbh2: usbh2grp { |
160 | fsl,pins = < | |
161 | MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 | |
162 | MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 | |
163 | MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 | |
164 | MX27_PAD_USBH2_STP__USBH2_STP 0x0 | |
165 | MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 | |
166 | MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 | |
167 | MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 | |
168 | MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 | |
169 | MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 | |
170 | MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 | |
171 | MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 | |
172 | MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 | |
173 | >; | |
174 | }; | |
175 | ||
3c6c9eeb AS |
176 | pinctrl_weim: weimgrp { |
177 | fsl,pins = < | |
178 | MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ | |
179 | MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ | |
180 | >; | |
181 | }; | |
26508cb7 MP |
182 | }; |
183 | }; | |
184 | ||
5e01e585 AS |
185 | &owire { |
186 | pinctrl-names = "default"; | |
187 | pinctrl-0 = <&pinctrl_owire1>; | |
188 | status = "okay"; | |
189 | }; | |
190 | ||
5ee49a11 AS |
191 | &pmicleds { |
192 | ledr1: led@3 { | |
193 | reg = <3>; | |
194 | label = "system:red1:user"; | |
195 | }; | |
196 | ||
197 | ledg1: led@4 { | |
198 | reg = <4>; | |
199 | label = "system:green1:user"; | |
200 | }; | |
201 | ||
202 | ledb1: led@5 { | |
203 | reg = <5>; | |
204 | label = "system:blue1:user"; | |
205 | }; | |
206 | ||
207 | ledr2: led@6 { | |
208 | reg = <6>; | |
209 | label = "system:red2:user"; | |
210 | }; | |
211 | ||
212 | ledg2: led@7 { | |
213 | reg = <7>; | |
214 | label = "system:green2:user"; | |
215 | }; | |
216 | ||
217 | ledb2: led@8 { | |
218 | reg = <8>; | |
219 | label = "system:blue2:user"; | |
220 | }; | |
221 | ||
222 | ledr3: led@9 { | |
223 | reg = <9>; | |
224 | label = "system:red3:nand"; | |
225 | linux,default-trigger = "nand-disk"; | |
226 | }; | |
227 | ||
228 | ledg3: led@10 { | |
229 | reg = <10>; | |
230 | label = "system:green3:live"; | |
231 | linux,default-trigger = "heartbeat"; | |
232 | }; | |
233 | ||
234 | ledb3: led@11 { | |
235 | reg = <11>; | |
236 | label = "system:blue3:cpu"; | |
237 | linux,default-trigger = "cpu0"; | |
238 | }; | |
239 | }; | |
240 | ||
8440ae70 | 241 | &sdhci2 { |
836ac783 AS |
242 | pinctrl-names = "default"; |
243 | pinctrl-0 = <&pinctrl_sdhc2>; | |
8440ae70 | 244 | bus-width = <4>; |
6ece55b3 AS |
245 | cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; |
246 | wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; | |
8440ae70 AS |
247 | vmmc-supply = <&vmmc1_reg>; |
248 | status = "okay"; | |
249 | }; | |
250 | ||
c05c1bf5 AS |
251 | &uart1 { |
252 | fsl,uart-has-rtscts; | |
26508cb7 MP |
253 | pinctrl-names = "default"; |
254 | pinctrl-0 = <&pinctrl_uart1>; | |
858db316 | 255 | status = "okay"; |
c05c1bf5 AS |
256 | }; |
257 | ||
258 | &uart2 { | |
259 | fsl,uart-has-rtscts; | |
26508cb7 MP |
260 | pinctrl-names = "default"; |
261 | pinctrl-0 = <&pinctrl_uart2>; | |
c05c1bf5 AS |
262 | status = "okay"; |
263 | }; | |
52303d13 | 264 | |
9089ce52 AS |
265 | &usbh2 { |
266 | pinctrl-names = "default"; | |
267 | pinctrl-0 = <&pinctrl_usbh2>; | |
268 | dr_mode = "host"; | |
269 | phy_type = "ulpi"; | |
270 | vbus-supply = <®_5v0>; | |
271 | disable-over-current; | |
272 | status = "okay"; | |
273 | }; | |
274 | ||
275 | &usbphy2 { | |
276 | vcc-supply = <®_5v0>; | |
277 | }; | |
278 | ||
52303d13 | 279 | &weim { |
3c6c9eeb AS |
280 | pinctrl-names = "default"; |
281 | pinctrl-0 = <&pinctrl_weim>; | |
282 | ||
52303d13 AS |
283 | can@d4000000 { |
284 | compatible = "nxp,sja1000"; | |
285 | reg = <4 0x00000000 0x00000100>; | |
286 | interrupt-parent = <&gpio5>; | |
6ece55b3 | 287 | interrupts = <19 IRQ_TYPE_EDGE_FALLING>; |
52303d13 AS |
288 | nxp,external-clock-frequency = <16000000>; |
289 | nxp,tx-output-config = <0x16>; | |
290 | nxp,no-comparator-bypass; | |
291 | fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; | |
292 | }; | |
293 | }; |