projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c05c1bf5 AS |
1 | /* |
| 2 | * The code contained herein is licensed under the GNU General Public | |
| 3 | * License. You may obtain a copy of the GNU General Public License | |
| 4 | * Version 2 or later at the following locations: | |
| 5 | * | |
| 6 | * http://www.opensource.org/licenses/gpl-license.html | |
| 7 | * http://www.gnu.org/copyleft/gpl.html | |
| 8 | */ | |
| 9 | ||
| e3da3d21 | 10 | #include "imx27-phytec-phycore-som.dtsi" |
| c05c1bf5 AS |
11 | |
| 12 | / { | |
| 13 | model = "Phytec pcm970"; | |
| 14 | compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; | |
| 15 | }; | |
| 16 | ||
| 17 | &cspi1 { | |
| 18 | fsl,spi-num-chipselects = <2>; | |
| 6ece55b3 AS |
19 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, |
| 20 | <&gpio4 27 GPIO_ACTIVE_LOW>; | |
| c05c1bf5 AS |
21 | }; |
| 22 | ||
| 5f9fe244 AS |
23 | &i2c1 { |
| 24 | clock-frequency = <400000>; | |
| 25 | pinctrl-names = "default"; | |
| 26 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 27 | status = "okay"; | |
| 28 | ||
| 29 | camgpio: pca9536@41 { | |
| 30 | compatible = "nxp,pca9536"; | |
| 31 | reg = <0x41>; | |
| 32 | gpio-controller; | |
| 33 | #gpio-cells = <2>; | |
| 34 | }; | |
| 35 | }; | |
| 36 | ||
| 26508cb7 MP |
37 | &iomuxc { |
| 38 | imx27_phycore_rdk { | |
| 5f9fe244 AS |
39 | pinctrl_i2c1: i2c1grp { |
| 40 | /* Add pullup to DATA line */ | |
| 41 | fsl,pins = < | |
| 42 | MX27_PAD_I2C_DATA__I2C_DATA 0x1 | |
| 43 | MX27_PAD_I2C_CLK__I2C_CLK 0x0 | |
| 44 | >; | |
| 45 | }; | |
| 46 | ||
| 26508cb7 MP |
47 | pinctrl_uart1: uart1grp { |
| 48 | fsl,pins = < | |
| 49 | MX27_PAD_UART1_TXD__UART1_TXD 0x0 | |
| 50 | MX27_PAD_UART1_RXD__UART1_RXD 0x0 | |
| 51 | MX27_PAD_UART1_CTS__UART1_CTS 0x0 | |
| 52 | MX27_PAD_UART1_RTS__UART1_RTS 0x0 | |
| 53 | >; | |
| 54 | }; | |
| 55 | ||
| 56 | pinctrl_uart2: uart2grp { | |
| 57 | fsl,pins = < | |
| 58 | MX27_PAD_UART2_TXD__UART2_TXD 0x0 | |
| 59 | MX27_PAD_UART2_RXD__UART2_RXD 0x0 | |
| 60 | MX27_PAD_UART2_CTS__UART2_CTS 0x0 | |
| 61 | MX27_PAD_UART2_RTS__UART2_RTS 0x0 | |
| 62 | >; | |
| 63 | }; | |
| 64 | }; | |
| 65 | }; | |
| 66 | ||
| 8440ae70 AS |
67 | &sdhci2 { |
| 68 | bus-width = <4>; | |
| 6ece55b3 AS |
69 | cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; |
| 70 | wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; | |
| 8440ae70 AS |
71 | vmmc-supply = <&vmmc1_reg>; |
| 72 | status = "okay"; | |
| 73 | }; | |
| 74 | ||
| c05c1bf5 AS |
75 | &uart1 { |
| 76 | fsl,uart-has-rtscts; | |
| 26508cb7 MP |
77 | pinctrl-names = "default"; |
| 78 | pinctrl-0 = <&pinctrl_uart1>; | |
| 858db316 | 79 | status = "okay"; |
| c05c1bf5 AS |
80 | }; |
| 81 | ||
| 82 | &uart2 { | |
| 83 | fsl,uart-has-rtscts; | |
| 26508cb7 MP |
84 | pinctrl-names = "default"; |
| 85 | pinctrl-0 = <&pinctrl_uart2>; | |
| c05c1bf5 AS |
86 | status = "okay"; |
| 87 | }; | |
| 52303d13 AS |
88 | |
| 89 | &weim { | |
| 90 | can@d4000000 { | |
| 91 | compatible = "nxp,sja1000"; | |
| 92 | reg = <4 0x00000000 0x00000100>; | |
| 93 | interrupt-parent = <&gpio5>; | |
| 6ece55b3 | 94 | interrupts = <19 IRQ_TYPE_EDGE_FALLING>; |
| 52303d13 AS |
95 | nxp,external-clock-frequency = <16000000>; |
| 96 | nxp,tx-output-config = <0x16>; | |
| 97 | nxp,no-comparator-bypass; | |
| 98 | fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; | |
| 99 | }; | |
| 100 | }; |