[deliverable/linux.git] / arch / arm / boot / dts / imx27.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx27-pinfunc.h"

#include <dt-bindings/clock/imx27-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &cspi1;
		spi1 = &cspi2;
		spi2 = &cspi3;
	};

	aitc: aitc-interrupt-controller@e0000000 {
		compatible = "fsl,imx27-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10040000 0x1000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc26m {
			compatible = "fsl,imx-osc26m", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			operating-points = <
				/* kHz uV */
				266000 1300000
				399000 1450000
			>;
			clock-latency = <62500>;
			clocks = <&clks IMX27_CLK_CPU_DIV>;
			voltage-tolerance = <5>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@10000000 { /* AIPI1 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10000000 0x20000>;
			ranges;

			dma: dma@10001000 {
				compatible = "fsl,imx27-dma";
				reg = <0x10001000 0x1000>;
				interrupts = <32>;
				clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
					 <&clks IMX27_CLK_DMA_AHB_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
				#dma-channels = <16>;
			};

			wdog: wdog@10002000 {
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
				reg = <0x10002000 0x1000>;
				interrupts = <27>;
				clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
			};

			gpt1: timer@10003000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10003000 0x1000>;
				interrupts = <26>;
				clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@10004000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10004000 0x1000>;
				interrupts = <25>;
				clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt3: timer@10005000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10005000 0x1000>;
				interrupts = <24>;
				clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			pwm: pwm@10006000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx27-pwm";
				reg = <0x10006000 0x1000>;
				interrupts = <23>;
				clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			kpp: kpp@10008000 {
				compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
				reg = <0x10008000 0x1000>;
				interrupts = <21>;
				clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
				status = "disabled";
			};

			owire: owire@10009000 {
				compatible = "fsl,imx27-owire", "fsl,imx21-owire";
				reg = <0x10009000 0x1000>;
				clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
				status = "disabled";
			};

			uart1: serial@1000a000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000a000 0x1000>;
				interrupts = <20>;
				clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@1000b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000b000 0x1000>;
				interrupts = <19>;
				clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@1000c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000c000 0x1000>;
				interrupts = <18>;
				clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@1000d000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000d000 0x1000>;
				interrupts = <17>;
				clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi1: cspi@1000e000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000e000 0x1000>;
				interrupts = <16>;
				clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi2: cspi@1000f000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000f000 0x1000>;
				interrupts = <15>;
				clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			ssi1: ssi@10010000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10010000 0x1000>;
				interrupts = <14>;
				clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
				dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			ssi2: ssi@10011000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10011000 0x1000>;
				interrupts = <13>;
				clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
				dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			i2c1: i2c@10012000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x10012000 0x1000>;
				interrupts = <12>;
				clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
				status = "disabled";
			};

			sdhci1: sdhci@10013000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10013000 0x1000>;
				interrupts = <11>;
				clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 7>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			sdhci2: sdhci@10014000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10014000 0x1000>;
				interrupts = <10>;
				clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 6>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			iomuxc: iomuxc@10015000 {
				compatible = "fsl,imx27-iomuxc";
				reg = <0x10015000 0x600>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio1: gpio@10015000 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015000 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@10015100 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015100 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@10015200 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015200 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@10015300 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015300 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio5: gpio@10015400 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015400 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio6: gpio@10015500 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015500 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			audmux: audmux@10016000 {
				compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
				reg = <0x10016000 0x1000>;
				clocks = <&clks IMX27_CLK_DUMMY>;
				clock-names = "audmux";
				status = "disabled";
			};

			cspi3: cspi@10017000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x10017000 0x1000>;
				interrupts = <6>;
				clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@10019000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10019000 0x1000>;
				interrupts = <4>;
				clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt5: timer@1001a000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001a000 0x1000>;
				interrupts = <3>;
				clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			uart5: serial@1001b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001b000 0x1000>;
				interrupts = <49>;
				clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@1001c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001c000 0x1000>;
				interrupts = <48>;
				clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@1001d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x1001d000 0x1000>;
				interrupts = <1>;
				clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
				status = "disabled";
			};

			sdhci3: sdhci@1001e000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x1001e000 0x1000>;
				interrupts = <9>;
				clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 36>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			gpt6: timer@1001f000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001f000 0x1000>;
				interrupts = <2>;
				clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};
		};

		aipi@10020000 { /* AIPI2 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10020000 0x20000>;
			ranges;

			fb: fb@10021000 {
				compatible = "fsl,imx27-fb", "fsl,imx21-fb";
				interrupts = <61>;
				reg = <0x10021000 0x1000>;
				clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
					 <&clks IMX27_CLK_LCDC_AHB_GATE>,
					 <&clks IMX27_CLK_PER3_GATE>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			coda: coda@10023000 {
				compatible = "fsl,imx27-vpu";
				reg = <0x10023000 0x0200>;
				interrupts = <53>;
				clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
					 <&clks IMX27_CLK_VPU_AHB_GATE>;
				clock-names = "per", "ahb";
				iram = <&iram>;
			};

			usbotg: usb@10024000 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024000 0x200>;
				interrupts = <56>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 0>;
				status = "disabled";
			};

			usbh1: usb@10024200 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024200 0x200>;
				interrupts = <54>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 1>;
				status = "disabled";
			};

			usbh2: usb@10024400 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024400 0x200>;
				interrupts = <55>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 2>;
				status = "disabled";
			};

			usbmisc: usbmisc@10024600 {
				#index-cells = <1>;
				compatible = "fsl,imx27-usbmisc";
				reg = <0x10024600 0x200>;
				clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
			};

			sahara2: sahara@10025000 {
				compatible = "fsl,imx27-sahara";
				reg = <0x10025000 0x1000>;
				interrupts = <59>;
				clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
					 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
				clock-names = "ipg", "ahb";
			};

			clks: ccm@10027000{
				compatible = "fsl,imx27-ccm";
				reg = <0x10027000 0x1000>;
				#clock-cells = <1>;
			};

			iim: iim@10028000 {
				compatible = "fsl,imx27-iim";
				reg = <0x10028000 0x1000>;
				interrupts = <62>;
				clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
			};

			fec: ethernet@1002b000 {
				compatible = "fsl,imx27-fec";
				reg = <0x1002b000 0x4000>;
				interrupts = <50>;
				clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
					 <&clks IMX27_CLK_FEC_AHB_GATE>;
				clock-names = "ipg", "ahb";
				status = "disabled";
			};
		};

		nfc: nand@d8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,imx27-nand";
			reg = <0xd8000000 0x1000>;
			interrupts = <29>;
			clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
			status = "disabled";
		};

		weim: weim@d8002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx27-weim";
			reg = <0xd8002000 0x1000>;
			clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
			ranges = <
				0 0 0xc0000000 0x08000000
				1 0 0xc8000000 0x08000000
				2 0 0xd0000000 0x02000000
				3 0 0xd2000000 0x02000000
				4 0 0xd4000000 0x02000000
				5 0 0xd6000000 0x02000000
			>;
			status = "disabled";
		};

		iram: iram@ffff4c00 {
			compatible = "mmio-sram";
			reg = <0xffff4c00 0xb400>;
		};
	};
};
Commit	Line	Data
9f0749e3 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
36dffd8f	12	#include "skeleton.dtsi"
61664d0b	13	#include "imx27-pinfunc.h"
ea336fa8 AS	14
	15	#include <dt-bindings/clock/imx27-clock.h>
	16	#include <dt-bindings/gpio/gpio.h>
f6bd3f30	17	#include <dt-bindings/input/input.h>
6ece55b3	18	#include <dt-bindings/interrupt-controller/irq.h>
9f0749e3 SH	19
	20	/ {
	21	aliases {
22970070	22	ethernet0 = &fec;
5230f8fe SG	23	gpio0 = &gpio1;
	24	gpio1 = &gpio2;
	25	gpio2 = &gpio3;
	26	gpio3 = &gpio4;
	27	gpio4 = &gpio5;
	28	gpio5 = &gpio6;
6a3c0b39 SH	29	i2c0 = &i2c1;
	30	i2c1 = &i2c2;
	31	serial0 = &uart1;
	32	serial1 = &uart2;
	33	serial2 = &uart3;
	34	serial3 = &uart4;
	35	serial4 = &uart5;
	36	serial5 = &uart6;
a5a641a1 AS	37	spi0 = &cspi1;
	38	spi1 = &cspi2;
	39	spi2 = &cspi3;
9f0749e3 SH	40	};
9f0749e3 SH	41
6189bc34 FE	42	aitc: aitc-interrupt-controller@e0000000 {
6189bc34 FE	43	compatible = "fsl,imx27-aitc", "fsl,avic";
9f0749e3 SH	44	interrupt-controller;
	45	#interrupt-cells = <1>;
	46	reg = <0x10040000 0x1000>;
	47	};
	48
	49	clocks {
	50	#address-cells = <1>;
	51	#size-cells = <0>;
	52
	53	osc26m {
	54	compatible = "fsl,imx-osc26m", "fixed-clock";
4b2b4043	55	#clock-cells = <0>;
9f0749e3 SH	56	clock-frequency = <26000000>;
	57	};
	58	};
	59
dc1d0f91 MP	60	cpus {
	61	#size-cells = <0>;
	62	#address-cells = <1>;
	63
48568be6	64	cpu: cpu@0 {
dc1d0f91 MP	65	device_type = "cpu";
	66	compatible = "arm,arm926ej-s";
	67	operating-points = <
98a3e804 AS	68	/* kHz uV */
	69	266000 1300000
	70	399000 1450000
dc1d0f91	71	>;
8defcb53	72	clock-latency = <62500>;
ea336fa8	73	clocks = <&clks IMX27_CLK_CPU_DIV>;
98a3e804	74	voltage-tolerance = <5>;
dc1d0f91 MP	75	};
	76	};
	77
9f0749e3 SH	78	soc {
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	compatible = "simple-bus";
6189bc34	82	interrupt-parent = <&aitc>;
9f0749e3 SH	83	ranges;
	84
	85	aipi@10000000 { /* AIPI1 */
	86	compatible = "fsl,aipi-bus", "simple-bus";
	87	#address-cells = <1>;
	88	#size-cells = <1>;
3e24b05b	89	reg = <0x10000000 0x20000>;
9f0749e3 SH	90	ranges;
9f0749e3 SH	91
b858c34f AS	92	dma: dma@10001000 {
	93	compatible = "fsl,imx27-dma";
	94	reg = <0x10001000 0x1000>;
	95	interrupts = <32>;
ea336fa8 AS	96	clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
ea336fa8 AS	97	<&clks IMX27_CLK_DMA_AHB_GATE>;
b858c34f AS	98	clock-names = "ipg", "ahb";
	99	#dma-cells = <1>;
	100	#dma-channels = <16>;
	101	};
	102
7b7d6727	103	wdog: wdog@10002000 {
9f0749e3	104	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
ca26d041	105	reg = <0x10002000 0x1000>;
9f0749e3	106	interrupts = <27>;
ea336fa8	107	clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
9f0749e3 SH	108	};
9f0749e3 SH	109
ca26d041 SH	110	gpt1: timer@10003000 {
	111	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	112	reg = <0x10003000 0x1000>;
	113	interrupts = <26>;
ea336fa8 AS	114	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
ea336fa8 AS	115	<&clks IMX27_CLK_PER1_GATE>;
b700c119	116	clock-names = "ipg", "per";
ca26d041 SH	117	};
	118
	119	gpt2: timer@10004000 {
	120	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	121	reg = <0x10004000 0x1000>;
	122	interrupts = <25>;
ea336fa8 AS	123	clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
ea336fa8 AS	124	<&clks IMX27_CLK_PER1_GATE>;
b700c119	125	clock-names = "ipg", "per";
ca26d041 SH	126	};
	127
	128	gpt3: timer@10005000 {
	129	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	130	reg = <0x10005000 0x1000>;
	131	interrupts = <24>;
ea336fa8 AS	132	clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
ea336fa8 AS	133	<&clks IMX27_CLK_PER1_GATE>;
b700c119	134	clock-names = "ipg", "per";
ca26d041 SH	135	};
ca26d041 SH	136
a392d044	137	pwm: pwm@10006000 {
443b6585	138	#pwm-cells = <2>;
08f4881a GGM	139	compatible = "fsl,imx27-pwm";
	140	reg = <0x10006000 0x1000>;
	141	interrupts = <23>;
ea336fa8 AS	142	clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
ea336fa8 AS	143	<&clks IMX27_CLK_PER1_GATE>;
08f4881a GGM	144	clock-names = "ipg", "per";
	145	};
	146
6c04ad22 AS	147	kpp: kpp@10008000 {
	148	compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
	149	reg = <0x10008000 0x1000>;
	150	interrupts = <21>;
ea336fa8	151	clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
6c04ad22 AS	152	status = "disabled";
	153	};
	154
6a486b7e MP	155	owire: owire@10009000 {
	156	compatible = "fsl,imx27-owire", "fsl,imx21-owire";
	157	reg = <0x10009000 0x1000>;
ea336fa8	158	clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
6a486b7e MP	159	status = "disabled";
	160	};
	161
0c456cfa	162	uart1: serial@1000a000 {
9f0749e3 SH	163	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	164	reg = <0x1000a000 0x1000>;
	165	interrupts = <20>;
ea336fa8 AS	166	clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
ea336fa8 AS	167	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	168	clock-names = "ipg", "per";
9f0749e3 SH	169	status = "disabled";
	170	};
	171
0c456cfa	172	uart2: serial@1000b000 {
9f0749e3 SH	173	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	174	reg = <0x1000b000 0x1000>;
	175	interrupts = <19>;
ea336fa8 AS	176	clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
ea336fa8 AS	177	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	178	clock-names = "ipg", "per";
9f0749e3 SH	179	status = "disabled";
	180	};
	181
0c456cfa	182	uart3: serial@1000c000 {
9f0749e3 SH	183	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	184	reg = <0x1000c000 0x1000>;
	185	interrupts = <18>;
ea336fa8 AS	186	clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
ea336fa8 AS	187	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	188	clock-names = "ipg", "per";
9f0749e3 SH	189	status = "disabled";
	190	};
	191
0c456cfa	192	uart4: serial@1000d000 {
9f0749e3 SH	193	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	194	reg = <0x1000d000 0x1000>;
	195	interrupts = <17>;
ea336fa8 AS	196	clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
ea336fa8 AS	197	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	198	clock-names = "ipg", "per";
9f0749e3 SH	199	status = "disabled";
	200	};
	201
	202	cspi1: cspi@1000e000 {
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	compatible = "fsl,imx27-cspi";
	206	reg = <0x1000e000 0x1000>;
	207	interrupts = <16>;
ea336fa8 AS	208	clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
ea336fa8 AS	209	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	210	clock-names = "ipg", "per";
9f0749e3 SH	211	status = "disabled";
	212	};
	213
	214	cspi2: cspi@1000f000 {
	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	compatible = "fsl,imx27-cspi";
	218	reg = <0x1000f000 0x1000>;
	219	interrupts = <15>;
ea336fa8 AS	220	clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
ea336fa8 AS	221	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	222	clock-names = "ipg", "per";
9f0749e3 SH	223	status = "disabled";
	224	};
	225
ba2d1ea7 AS	226	ssi1: ssi@10010000 {
	227	#sound-dai-cells = <0>;
	228	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	229	reg = <0x10010000 0x1000>;
	230	interrupts = <14>;
ea336fa8	231	clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
ba2d1ea7 AS	232	dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
	233	dma-names = "rx0", "tx0", "rx1", "tx1";
	234	fsl,fifo-depth = <8>;
	235	status = "disabled";
	236	};
	237
	238	ssi2: ssi@10011000 {
	239	#sound-dai-cells = <0>;
	240	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	241	reg = <0x10011000 0x1000>;
	242	interrupts = <13>;
ea336fa8	243	clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
ba2d1ea7 AS	244	dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
	245	dma-names = "rx0", "tx0", "rx1", "tx1";
	246	fsl,fifo-depth = <8>;
	247	status = "disabled";
	248	};
	249
9f0749e3 SH	250	i2c1: i2c@10012000 {
	251	#address-cells = <1>;
	252	#size-cells = <0>;
5bdfba29	253	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	254	reg = <0x10012000 0x1000>;
9f0749e3 SH	255	interrupts = <12>;
ea336fa8	256	clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
9f0749e3 SH	257	status = "disabled";
	258	};
	259
0e7b01aa AS	260	sdhci1: sdhci@10013000 {
	261	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	262	reg = <0x10013000 0x1000>;
	263	interrupts = <11>;
ea336fa8 AS	264	clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
ea336fa8 AS	265	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	266	clock-names = "ipg", "per";
	267	dmas = <&dma 7>;
	268	dma-names = "rx-tx";
	269	status = "disabled";
	270	};
	271
	272	sdhci2: sdhci@10014000 {
	273	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	274	reg = <0x10014000 0x1000>;
	275	interrupts = <10>;
ea336fa8 AS	276	clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
ea336fa8 AS	277	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	278	clock-names = "ipg", "per";
	279	dmas = <&dma 6>;
	280	dma-names = "rx-tx";
	281	status = "disabled";
	282	};
	283
733f6cae MP	284	iomuxc: iomuxc@10015000 {
	285	compatible = "fsl,imx27-iomuxc";
	286	reg = <0x10015000 0x600>;
	287	#address-cells = <1>;
	288	#size-cells = <1>;
	289	ranges;
	290
	291	gpio1: gpio@10015000 {
	292	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	293	reg = <0x10015000 0x100>;
ea336fa8	294	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	295	interrupts = <8>;
	296	gpio-controller;
	297	#gpio-cells = <2>;
	298	interrupt-controller;
	299	#interrupt-cells = <2>;
	300	};
	301
	302	gpio2: gpio@10015100 {
	303	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	304	reg = <0x10015100 0x100>;
ea336fa8	305	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	306	interrupts = <8>;
	307	gpio-controller;
	308	#gpio-cells = <2>;
	309	interrupt-controller;
	310	#interrupt-cells = <2>;
	311	};
	312
	313	gpio3: gpio@10015200 {
	314	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	315	reg = <0x10015200 0x100>;
ea336fa8	316	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	317	interrupts = <8>;
	318	gpio-controller;
	319	#gpio-cells = <2>;
	320	interrupt-controller;
	321	#interrupt-cells = <2>;
	322	};
	323
	324	gpio4: gpio@10015300 {
	325	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	326	reg = <0x10015300 0x100>;
ea336fa8	327	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	328	interrupts = <8>;
	329	gpio-controller;
	330	#gpio-cells = <2>;
	331	interrupt-controller;
	332	#interrupt-cells = <2>;
	333	};
	334
	335	gpio5: gpio@10015400 {
	336	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	337	reg = <0x10015400 0x100>;
ea336fa8	338	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	339	interrupts = <8>;
	340	gpio-controller;
	341	#gpio-cells = <2>;
	342	interrupt-controller;
	343	#interrupt-cells = <2>;
	344	};
	345
	346	gpio6: gpio@10015500 {
	347	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	348	reg = <0x10015500 0x100>;
ea336fa8	349	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	350	interrupts = <8>;
	351	gpio-controller;
	352	#gpio-cells = <2>;
	353	interrupt-controller;
	354	#interrupt-cells = <2>;
	355	};
9f0749e3 SH	356	};
9f0749e3 SH	357
6e228e80 AS	358	audmux: audmux@10016000 {
	359	compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
	360	reg = <0x10016000 0x1000>;
ea336fa8	361	clocks = <&clks IMX27_CLK_DUMMY>;
6e228e80	362	clock-names = "audmux";
1c04ab0f	363	status = "disabled";
6e228e80 AS	364	};
6e228e80 AS	365
9f0749e3 SH	366	cspi3: cspi@10017000 {
	367	#address-cells = <1>;
	368	#size-cells = <0>;
	369	compatible = "fsl,imx27-cspi";
	370	reg = <0x10017000 0x1000>;
	371	interrupts = <6>;
ea336fa8 AS	372	clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
ea336fa8 AS	373	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	374	clock-names = "ipg", "per";
9f0749e3 SH	375	status = "disabled";
	376	};
	377
ca26d041 SH	378	gpt4: timer@10019000 {
	379	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	380	reg = <0x10019000 0x1000>;
	381	interrupts = <4>;
ea336fa8 AS	382	clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
ea336fa8 AS	383	<&clks IMX27_CLK_PER1_GATE>;
b700c119	384	clock-names = "ipg", "per";
ca26d041 SH	385	};
	386
	387	gpt5: timer@1001a000 {
	388	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	389	reg = <0x1001a000 0x1000>;
	390	interrupts = <3>;
ea336fa8 AS	391	clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
ea336fa8 AS	392	<&clks IMX27_CLK_PER1_GATE>;
b700c119	393	clock-names = "ipg", "per";
ca26d041 SH	394	};
ca26d041 SH	395
0c456cfa	396	uart5: serial@1001b000 {
9f0749e3 SH	397	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	398	reg = <0x1001b000 0x1000>;
	399	interrupts = <49>;
ea336fa8 AS	400	clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
ea336fa8 AS	401	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	402	clock-names = "ipg", "per";
9f0749e3 SH	403	status = "disabled";
	404	};
	405
0c456cfa	406	uart6: serial@1001c000 {
9f0749e3 SH	407	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	408	reg = <0x1001c000 0x1000>;
	409	interrupts = <48>;
ea336fa8 AS	410	clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
ea336fa8 AS	411	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	412	clock-names = "ipg", "per";
9f0749e3 SH	413	status = "disabled";
	414	};
	415
	416	i2c2: i2c@1001d000 {
	417	#address-cells = <1>;
	418	#size-cells = <0>;
5bdfba29	419	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	420	reg = <0x1001d000 0x1000>;
9f0749e3 SH	421	interrupts = <1>;
ea336fa8	422	clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
9f0749e3 SH	423	status = "disabled";
	424	};
	425
0e7b01aa AS	426	sdhci3: sdhci@1001e000 {
	427	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	428	reg = <0x1001e000 0x1000>;
	429	interrupts = <9>;
ea336fa8 AS	430	clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
ea336fa8 AS	431	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	432	clock-names = "ipg", "per";
	433	dmas = <&dma 36>;
	434	dma-names = "rx-tx";
	435	status = "disabled";
	436	};
	437
ca26d041 SH	438	gpt6: timer@1001f000 {
	439	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	440	reg = <0x1001f000 0x1000>;
	441	interrupts = <2>;
ea336fa8 AS	442	clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
ea336fa8 AS	443	<&clks IMX27_CLK_PER1_GATE>;
b700c119	444	clock-names = "ipg", "per";
ca26d041	445	};
3e24b05b FE	446	};
	447
	448	aipi@10020000 { /* AIPI2 */
	449	compatible = "fsl,aipi-bus", "simple-bus";
	450	#address-cells = <1>;
	451	#size-cells = <1>;
	452	reg = <0x10020000 0x20000>;
	453	ranges;
	454
5e57b241 MP	455	fb: fb@10021000 {
	456	compatible = "fsl,imx27-fb", "fsl,imx21-fb";
	457	interrupts = <61>;
	458	reg = <0x10021000 0x1000>;
ea336fa8 AS	459	clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
	460	<&clks IMX27_CLK_LCDC_AHB_GATE>,
	461	<&clks IMX27_CLK_PER3_GATE>;
5e57b241 MP	462	clock-names = "ipg", "ahb", "per";
	463	status = "disabled";
	464	};
	465
93b331ce AS	466	coda: coda@10023000 {
	467	compatible = "fsl,imx27-vpu";
	468	reg = <0x10023000 0x0200>;
	469	interrupts = <53>;
ea336fa8 AS	470	clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
ea336fa8 AS	471	<&clks IMX27_CLK_VPU_AHB_GATE>;
93b331ce AS	472	clock-names = "per", "ahb";
	473	iram = <&iram>;
	474	};
	475
a2e502c2 AS	476	usbotg: usb@10024000 {
	477	compatible = "fsl,imx27-usb";
	478	reg = <0x10024000 0x200>;
	479	interrupts = <56>;
ea336fa8	480	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2	481	fsl,usbmisc = <&usbmisc 0>;
a2e502c2 AS	482	status = "disabled";
	483	};
	484
	485	usbh1: usb@10024200 {
	486	compatible = "fsl,imx27-usb";
	487	reg = <0x10024200 0x200>;
	488	interrupts = <54>;
ea336fa8	489	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2 AS	490	fsl,usbmisc = <&usbmisc 1>;
	491	status = "disabled";
	492	};
	493
	494	usbh2: usb@10024400 {
	495	compatible = "fsl,imx27-usb";
	496	reg = <0x10024400 0x200>;
	497	interrupts = <55>;
ea336fa8	498	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2	499	fsl,usbmisc = <&usbmisc 2>;
a2e502c2 AS	500	status = "disabled";
	501	};
	502
	503	usbmisc: usbmisc@10024600 {
	504	#index-cells = <1>;
	505	compatible = "fsl,imx27-usbmisc";
	506	reg = <0x10024600 0x200>;
ea336fa8	507	clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
a2e502c2 AS	508	};
a2e502c2 AS	509
e4b6a056 AS	510	sahara2: sahara@10025000 {
	511	compatible = "fsl,imx27-sahara";
	512	reg = <0x10025000 0x1000>;
	513	interrupts = <59>;
ea336fa8 AS	514	clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
ea336fa8 AS	515	<&clks IMX27_CLK_SAHARA_AHB_GATE>;
e4b6a056 AS	516	clock-names = "ipg", "ahb";
	517	};
	518
93b331ce AS	519	clks: ccm@10027000{
	520	compatible = "fsl,imx27-ccm";
	521	reg = <0x10027000 0x1000>;
	522	#clock-cells = <1>;
	523	};
	524
d36afcd4 AS	525	iim: iim@10028000 {
	526	compatible = "fsl,imx27-iim";
	527	reg = <0x10028000 0x1000>;
	528	interrupts = <62>;
ea336fa8	529	clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
d36afcd4 AS	530	};
d36afcd4 AS	531
0c456cfa	532	fec: ethernet@1002b000 {
9f0749e3 SH	533	compatible = "fsl,imx27-fec";
	534	reg = <0x1002b000 0x4000>;
	535	interrupts = <50>;
ea336fa8 AS	536	clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
ea336fa8 AS	537	<&clks IMX27_CLK_FEC_AHB_GATE>;
c0b357c0	538	clock-names = "ipg", "ahb";
9f0749e3 SH	539	status = "disabled";
	540	};
	541	};
7b7d6727 SH	542
7b7d6727 SH	543	nfc: nand@d8000000 {
37787360 UKK	544	#address-cells = <1>;
37787360 UKK	545	#size-cells = <1>;
37787360 UKK	546	compatible = "fsl,imx27-nand";
	547	reg = <0xd8000000 0x1000>;
	548	interrupts = <29>;
ea336fa8	549	clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
37787360 UKK	550	status = "disabled";
37787360 UKK	551	};
ff1450f6	552
0912f594 AS	553	weim: weim@d8002000 {
	554	#address-cells = <2>;
	555	#size-cells = <1>;
	556	compatible = "fsl,imx27-weim";
	557	reg = <0xd8002000 0x1000>;
ea336fa8	558	clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
0912f594 AS	559	ranges = <
	560	0 0 0xc0000000 0x08000000
	561	1 0 0xc8000000 0x08000000
	562	2 0 0xd0000000 0x02000000
	563	3 0 0xd2000000 0x02000000
	564	4 0 0xd4000000 0x02000000
	565	5 0 0xd6000000 0x02000000
	566	>;
	567	status = "disabled";
	568	};
	569
ff1450f6 AS	570	iram: iram@ffff4c00 {
	571	compatible = "mmio-sram";
	572	reg = <0xffff4c00 0xb400>;
	573	};
9f0749e3 SH	574	};
9f0749e3 SH	575	};