[deliverable/linux.git] / arch / arm / boot / dts / imx27.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx27-pinfunc.h"

#include <dt-bindings/clock/imx27-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &cspi1;
		spi1 = &cspi2;
		spi2 = &cspi3;
	};

	aitc: aitc-interrupt-controller@e0000000 {
		compatible = "fsl,imx27-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10040000 0x1000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc26m {
			compatible = "fsl,imx-osc26m", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			operating-points = <
				/* kHz uV */
				266000 1300000
				399000 1450000
			>;
			clock-latency = <62500>;
			clocks = <&clks IMX27_CLK_CPU_DIV>;
			voltage-tolerance = <5>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@10000000 { /* AIPI1 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10000000 0x20000>;
			ranges;

			dma: dma@10001000 {
				compatible = "fsl,imx27-dma";
				reg = <0x10001000 0x1000>;
				interrupts = <32>;
				clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
					 <&clks IMX27_CLK_DMA_AHB_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
				#dma-channels = <16>;
			};

			wdog: wdog@10002000 {
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
				reg = <0x10002000 0x1000>;
				interrupts = <27>;
				clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
			};

			gpt1: timer@10003000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x10003000 0x1000>;
				interrupts = <26>;
				clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@10004000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x10004000 0x1000>;
				interrupts = <25>;
				clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt3: timer@10005000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x10005000 0x1000>;
				interrupts = <24>;
				clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			pwm: pwm@10006000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx27-pwm";
				reg = <0x10006000 0x1000>;
				interrupts = <23>;
				clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			rtc: rtc@10007000 {
				compatible = "fsl,imx21-rtc";
				reg = <0x10007000 0x1000>;
				interrupts = <22>;
				clocks = <&clks IMX27_CLK_CKIL>,
					 <&clks IMX27_CLK_RTC_IPG_GATE>;
				clock-names = "ref", "ipg";
			};

			kpp: kpp@10008000 {
				compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
				reg = <0x10008000 0x1000>;
				interrupts = <21>;
				clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
				status = "disabled";
			};

			owire: owire@10009000 {
				compatible = "fsl,imx27-owire", "fsl,imx21-owire";
				reg = <0x10009000 0x1000>;
				clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
				status = "disabled";
			};

			uart1: serial@1000a000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000a000 0x1000>;
				interrupts = <20>;
				clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@1000b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000b000 0x1000>;
				interrupts = <19>;
				clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@1000c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000c000 0x1000>;
				interrupts = <18>;
				clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@1000d000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000d000 0x1000>;
				interrupts = <17>;
				clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi1: cspi@1000e000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000e000 0x1000>;
				interrupts = <16>;
				clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi2: cspi@1000f000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000f000 0x1000>;
				interrupts = <15>;
				clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			ssi1: ssi@10010000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10010000 0x1000>;
				interrupts = <14>;
				clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
				dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			ssi2: ssi@10011000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10011000 0x1000>;
				interrupts = <13>;
				clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
				dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			i2c1: i2c@10012000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x10012000 0x1000>;
				interrupts = <12>;
				clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
				status = "disabled";
			};

			sdhci1: sdhci@10013000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10013000 0x1000>;
				interrupts = <11>;
				clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 7>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			sdhci2: sdhci@10014000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10014000 0x1000>;
				interrupts = <10>;
				clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 6>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			iomuxc: iomuxc@10015000 {
				compatible = "fsl,imx27-iomuxc";
				reg = <0x10015000 0x600>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio1: gpio@10015000 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015000 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@10015100 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015100 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@10015200 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015200 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@10015300 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015300 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio5: gpio@10015400 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015400 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio6: gpio@10015500 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015500 0x100>;
					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			audmux: audmux@10016000 {
				compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
				reg = <0x10016000 0x1000>;
				clocks = <&clks IMX27_CLK_DUMMY>;
				clock-names = "audmux";
				status = "disabled";
			};

			cspi3: cspi@10017000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x10017000 0x1000>;
				interrupts = <6>;
				clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@10019000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x10019000 0x1000>;
				interrupts = <4>;
				clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			gpt5: timer@1001a000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x1001a000 0x1000>;
				interrupts = <3>;
				clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};

			uart5: serial@1001b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001b000 0x1000>;
				interrupts = <49>;
				clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@1001c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001c000 0x1000>;
				interrupts = <48>;
				clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@1001d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x1001d000 0x1000>;
				interrupts = <1>;
				clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
				status = "disabled";
			};

			sdhci3: sdhci@1001e000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x1001e000 0x1000>;
				interrupts = <9>;
				clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
					 <&clks IMX27_CLK_PER2_GATE>;
				clock-names = "ipg", "per";
				dmas = <&dma 36>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			gpt6: timer@1001f000 {
				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
				reg = <0x1001f000 0x1000>;
				interrupts = <2>;
				clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
					 <&clks IMX27_CLK_PER1_GATE>;
				clock-names = "ipg", "per";
			};
		};

		aipi@10020000 { /* AIPI2 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10020000 0x20000>;
			ranges;

			fb: fb@10021000 {
				compatible = "fsl,imx27-fb", "fsl,imx21-fb";
				interrupts = <61>;
				reg = <0x10021000 0x1000>;
				clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
					 <&clks IMX27_CLK_LCDC_AHB_GATE>,
					 <&clks IMX27_CLK_PER3_GATE>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			coda: coda@10023000 {
				compatible = "fsl,imx27-vpu", "cnm,codadx6";
				reg = <0x10023000 0x0200>;
				interrupts = <53>;
				clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
					 <&clks IMX27_CLK_VPU_AHB_GATE>;
				clock-names = "per", "ahb";
				iram = <&iram>;
			};

			usbotg: usb@10024000 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024000 0x200>;
				interrupts = <56>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 0>;
				status = "disabled";
			};

			usbh1: usb@10024200 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024200 0x200>;
				interrupts = <54>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 1>;
				dr_mode = "host";
				status = "disabled";
			};

			usbh2: usb@10024400 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024400 0x200>;
				interrupts = <55>;
				clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
				fsl,usbmisc = <&usbmisc 2>;
				dr_mode = "host";
				status = "disabled";
			};

			usbmisc: usbmisc@10024600 {
				#index-cells = <1>;
				compatible = "fsl,imx27-usbmisc";
				reg = <0x10024600 0x200>;
				clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
			};

			sahara2: sahara@10025000 {
				compatible = "fsl,imx27-sahara";
				reg = <0x10025000 0x1000>;
				interrupts = <59>;
				clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
					 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
				clock-names = "ipg", "ahb";
			};

			clks: ccm@10027000{
				compatible = "fsl,imx27-ccm";
				reg = <0x10027000 0x1000>;
				#clock-cells = <1>;
			};

			iim: iim@10028000 {
				compatible = "fsl,imx27-iim";
				reg = <0x10028000 0x1000>;
				interrupts = <62>;
				clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
			};

			fec: ethernet@1002b000 {
				compatible = "fsl,imx27-fec";
				reg = <0x1002b000 0x1000>;
				interrupts = <50>;
				clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
					 <&clks IMX27_CLK_FEC_AHB_GATE>;
				clock-names = "ipg", "ahb";
				status = "disabled";
			};
		};

		nfc: nand@d8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,imx27-nand";
			reg = <0xd8000000 0x1000>;
			interrupts = <29>;
			clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
			status = "disabled";
		};

		weim: weim@d8002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx27-weim";
			reg = <0xd8002000 0x1000>;
			clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
			ranges = <
				0 0 0xc0000000 0x08000000
				1 0 0xc8000000 0x08000000
				2 0 0xd0000000 0x02000000
				3 0 0xd2000000 0x02000000
				4 0 0xd4000000 0x02000000
				5 0 0xd6000000 0x02000000
			>;
			status = "disabled";
		};

		iram: iram@ffff4c00 {
			compatible = "mmio-sram";
			reg = <0xffff4c00 0xb400>;
		};
	};
};
Commit	Line	Data
9f0749e3 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
36dffd8f	12	#include "skeleton.dtsi"
61664d0b	13	#include "imx27-pinfunc.h"
ea336fa8 AS	14
	15	#include <dt-bindings/clock/imx27-clock.h>
	16	#include <dt-bindings/gpio/gpio.h>
f6bd3f30	17	#include <dt-bindings/input/input.h>
6ece55b3	18	#include <dt-bindings/interrupt-controller/irq.h>
9f0749e3 SH	19
	20	/ {
	21	aliases {
22970070	22	ethernet0 = &fec;
5230f8fe SG	23	gpio0 = &gpio1;
	24	gpio1 = &gpio2;
	25	gpio2 = &gpio3;
	26	gpio3 = &gpio4;
	27	gpio4 = &gpio5;
	28	gpio5 = &gpio6;
6a3c0b39 SH	29	i2c0 = &i2c1;
	30	i2c1 = &i2c2;
	31	serial0 = &uart1;
	32	serial1 = &uart2;
	33	serial2 = &uart3;
	34	serial3 = &uart4;
	35	serial4 = &uart5;
	36	serial5 = &uart6;
a5a641a1 AS	37	spi0 = &cspi1;
	38	spi1 = &cspi2;
	39	spi2 = &cspi3;
9f0749e3 SH	40	};
9f0749e3 SH	41
6189bc34 FE	42	aitc: aitc-interrupt-controller@e0000000 {
6189bc34 FE	43	compatible = "fsl,imx27-aitc", "fsl,avic";
9f0749e3 SH	44	interrupt-controller;
	45	#interrupt-cells = <1>;
	46	reg = <0x10040000 0x1000>;
	47	};
	48
	49	clocks {
	50	#address-cells = <1>;
	51	#size-cells = <0>;
	52
	53	osc26m {
	54	compatible = "fsl,imx-osc26m", "fixed-clock";
4b2b4043	55	#clock-cells = <0>;
9f0749e3 SH	56	clock-frequency = <26000000>;
	57	};
	58	};
	59
dc1d0f91 MP	60	cpus {
	61	#size-cells = <0>;
	62	#address-cells = <1>;
	63
48568be6	64	cpu: cpu@0 {
dc1d0f91 MP	65	device_type = "cpu";
	66	compatible = "arm,arm926ej-s";
	67	operating-points = <
98a3e804 AS	68	/* kHz uV */
	69	266000 1300000
	70	399000 1450000
dc1d0f91	71	>;
8defcb53	72	clock-latency = <62500>;
ea336fa8	73	clocks = <&clks IMX27_CLK_CPU_DIV>;
98a3e804	74	voltage-tolerance = <5>;
dc1d0f91 MP	75	};
	76	};
	77
9f0749e3 SH	78	soc {
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	compatible = "simple-bus";
6189bc34	82	interrupt-parent = <&aitc>;
9f0749e3 SH	83	ranges;
	84
	85	aipi@10000000 { /* AIPI1 */
	86	compatible = "fsl,aipi-bus", "simple-bus";
	87	#address-cells = <1>;
	88	#size-cells = <1>;
3e24b05b	89	reg = <0x10000000 0x20000>;
9f0749e3 SH	90	ranges;
9f0749e3 SH	91
b858c34f AS	92	dma: dma@10001000 {
	93	compatible = "fsl,imx27-dma";
	94	reg = <0x10001000 0x1000>;
	95	interrupts = <32>;
ea336fa8 AS	96	clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
ea336fa8 AS	97	<&clks IMX27_CLK_DMA_AHB_GATE>;
b858c34f AS	98	clock-names = "ipg", "ahb";
	99	#dma-cells = <1>;
	100	#dma-channels = <16>;
	101	};
	102
7b7d6727	103	wdog: wdog@10002000 {
9f0749e3	104	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
ca26d041	105	reg = <0x10002000 0x1000>;
9f0749e3	106	interrupts = <27>;
ea336fa8	107	clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
9f0749e3 SH	108	};
9f0749e3 SH	109
ca26d041	110	gpt1: timer@10003000 {
afde1312	111	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	112	reg = <0x10003000 0x1000>;
ca26d041 SH	113	interrupts = <26>;
ea336fa8 AS	114	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
ea336fa8 AS	115	<&clks IMX27_CLK_PER1_GATE>;
b700c119	116	clock-names = "ipg", "per";
ca26d041 SH	117	};
	118
	119	gpt2: timer@10004000 {
afde1312	120	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	121	reg = <0x10004000 0x1000>;
ca26d041 SH	122	interrupts = <25>;
ea336fa8 AS	123	clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
ea336fa8 AS	124	<&clks IMX27_CLK_PER1_GATE>;
b700c119	125	clock-names = "ipg", "per";
ca26d041 SH	126	};
	127
	128	gpt3: timer@10005000 {
afde1312	129	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	130	reg = <0x10005000 0x1000>;
ca26d041 SH	131	interrupts = <24>;
ea336fa8 AS	132	clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
ea336fa8 AS	133	<&clks IMX27_CLK_PER1_GATE>;
b700c119	134	clock-names = "ipg", "per";
ca26d041 SH	135	};
ca26d041 SH	136
a392d044	137	pwm: pwm@10006000 {
443b6585	138	#pwm-cells = <2>;
08f4881a GGM	139	compatible = "fsl,imx27-pwm";
	140	reg = <0x10006000 0x1000>;
	141	interrupts = <23>;
ea336fa8 AS	142	clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
ea336fa8 AS	143	<&clks IMX27_CLK_PER1_GATE>;
08f4881a GGM	144	clock-names = "ipg", "per";
	145	};
	146
91eca8d5 PR	147	rtc: rtc@10007000 {
	148	compatible = "fsl,imx21-rtc";
	149	reg = <0x10007000 0x1000>;
	150	interrupts = <22>;
	151	clocks = <&clks IMX27_CLK_CKIL>,
	152	<&clks IMX27_CLK_RTC_IPG_GATE>;
	153	clock-names = "ref", "ipg";
	154	};
	155
6c04ad22 AS	156	kpp: kpp@10008000 {
	157	compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
	158	reg = <0x10008000 0x1000>;
	159	interrupts = <21>;
ea336fa8	160	clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
6c04ad22 AS	161	status = "disabled";
	162	};
	163
6a486b7e MP	164	owire: owire@10009000 {
	165	compatible = "fsl,imx27-owire", "fsl,imx21-owire";
	166	reg = <0x10009000 0x1000>;
ea336fa8	167	clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
6a486b7e MP	168	status = "disabled";
	169	};
	170
0c456cfa	171	uart1: serial@1000a000 {
9f0749e3 SH	172	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	173	reg = <0x1000a000 0x1000>;
	174	interrupts = <20>;
ea336fa8 AS	175	clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
ea336fa8 AS	176	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	177	clock-names = "ipg", "per";
9f0749e3 SH	178	status = "disabled";
	179	};
	180
0c456cfa	181	uart2: serial@1000b000 {
9f0749e3 SH	182	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	183	reg = <0x1000b000 0x1000>;
	184	interrupts = <19>;
ea336fa8 AS	185	clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
ea336fa8 AS	186	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	187	clock-names = "ipg", "per";
9f0749e3 SH	188	status = "disabled";
	189	};
	190
0c456cfa	191	uart3: serial@1000c000 {
9f0749e3 SH	192	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	193	reg = <0x1000c000 0x1000>;
	194	interrupts = <18>;
ea336fa8 AS	195	clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
ea336fa8 AS	196	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	197	clock-names = "ipg", "per";
9f0749e3 SH	198	status = "disabled";
	199	};
	200
0c456cfa	201	uart4: serial@1000d000 {
9f0749e3 SH	202	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	203	reg = <0x1000d000 0x1000>;
	204	interrupts = <17>;
ea336fa8 AS	205	clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
ea336fa8 AS	206	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	207	clock-names = "ipg", "per";
9f0749e3 SH	208	status = "disabled";
	209	};
	210
	211	cspi1: cspi@1000e000 {
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	compatible = "fsl,imx27-cspi";
	215	reg = <0x1000e000 0x1000>;
	216	interrupts = <16>;
ea336fa8 AS	217	clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
ea336fa8 AS	218	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	219	clock-names = "ipg", "per";
9f0749e3 SH	220	status = "disabled";
	221	};
	222
	223	cspi2: cspi@1000f000 {
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	compatible = "fsl,imx27-cspi";
	227	reg = <0x1000f000 0x1000>;
	228	interrupts = <15>;
ea336fa8 AS	229	clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
ea336fa8 AS	230	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	231	clock-names = "ipg", "per";
9f0749e3 SH	232	status = "disabled";
	233	};
	234
ba2d1ea7 AS	235	ssi1: ssi@10010000 {
	236	#sound-dai-cells = <0>;
	237	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	238	reg = <0x10010000 0x1000>;
	239	interrupts = <14>;
ea336fa8	240	clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
ba2d1ea7 AS	241	dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
	242	dma-names = "rx0", "tx0", "rx1", "tx1";
	243	fsl,fifo-depth = <8>;
	244	status = "disabled";
	245	};
	246
	247	ssi2: ssi@10011000 {
	248	#sound-dai-cells = <0>;
	249	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	250	reg = <0x10011000 0x1000>;
	251	interrupts = <13>;
ea336fa8	252	clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
ba2d1ea7 AS	253	dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
	254	dma-names = "rx0", "tx0", "rx1", "tx1";
	255	fsl,fifo-depth = <8>;
	256	status = "disabled";
	257	};
	258
9f0749e3 SH	259	i2c1: i2c@10012000 {
	260	#address-cells = <1>;
	261	#size-cells = <0>;
5bdfba29	262	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	263	reg = <0x10012000 0x1000>;
9f0749e3 SH	264	interrupts = <12>;
ea336fa8	265	clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
9f0749e3 SH	266	status = "disabled";
	267	};
	268
0e7b01aa AS	269	sdhci1: sdhci@10013000 {
	270	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	271	reg = <0x10013000 0x1000>;
	272	interrupts = <11>;
ea336fa8 AS	273	clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
ea336fa8 AS	274	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	275	clock-names = "ipg", "per";
	276	dmas = <&dma 7>;
	277	dma-names = "rx-tx";
	278	status = "disabled";
	279	};
	280
	281	sdhci2: sdhci@10014000 {
	282	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	283	reg = <0x10014000 0x1000>;
	284	interrupts = <10>;
ea336fa8 AS	285	clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
ea336fa8 AS	286	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	287	clock-names = "ipg", "per";
	288	dmas = <&dma 6>;
	289	dma-names = "rx-tx";
	290	status = "disabled";
	291	};
	292
733f6cae MP	293	iomuxc: iomuxc@10015000 {
	294	compatible = "fsl,imx27-iomuxc";
	295	reg = <0x10015000 0x600>;
	296	#address-cells = <1>;
	297	#size-cells = <1>;
	298	ranges;
	299
	300	gpio1: gpio@10015000 {
	301	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	302	reg = <0x10015000 0x100>;
ea336fa8	303	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	304	interrupts = <8>;
	305	gpio-controller;
	306	#gpio-cells = <2>;
	307	interrupt-controller;
	308	#interrupt-cells = <2>;
	309	};
	310
	311	gpio2: gpio@10015100 {
	312	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	313	reg = <0x10015100 0x100>;
ea336fa8	314	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	315	interrupts = <8>;
	316	gpio-controller;
	317	#gpio-cells = <2>;
	318	interrupt-controller;
	319	#interrupt-cells = <2>;
	320	};
	321
	322	gpio3: gpio@10015200 {
	323	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	324	reg = <0x10015200 0x100>;
ea336fa8	325	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	326	interrupts = <8>;
	327	gpio-controller;
	328	#gpio-cells = <2>;
	329	interrupt-controller;
	330	#interrupt-cells = <2>;
	331	};
	332
	333	gpio4: gpio@10015300 {
	334	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	335	reg = <0x10015300 0x100>;
ea336fa8	336	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	337	interrupts = <8>;
	338	gpio-controller;
	339	#gpio-cells = <2>;
	340	interrupt-controller;
	341	#interrupt-cells = <2>;
	342	};
	343
	344	gpio5: gpio@10015400 {
	345	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	346	reg = <0x10015400 0x100>;
ea336fa8	347	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	348	interrupts = <8>;
	349	gpio-controller;
	350	#gpio-cells = <2>;
	351	interrupt-controller;
	352	#interrupt-cells = <2>;
	353	};
	354
	355	gpio6: gpio@10015500 {
	356	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	357	reg = <0x10015500 0x100>;
ea336fa8	358	clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
733f6cae MP	359	interrupts = <8>;
	360	gpio-controller;
	361	#gpio-cells = <2>;
	362	interrupt-controller;
	363	#interrupt-cells = <2>;
	364	};
9f0749e3 SH	365	};
9f0749e3 SH	366
6e228e80 AS	367	audmux: audmux@10016000 {
	368	compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
	369	reg = <0x10016000 0x1000>;
ea336fa8	370	clocks = <&clks IMX27_CLK_DUMMY>;
6e228e80	371	clock-names = "audmux";
1c04ab0f	372	status = "disabled";
6e228e80 AS	373	};
6e228e80 AS	374
9f0749e3 SH	375	cspi3: cspi@10017000 {
	376	#address-cells = <1>;
	377	#size-cells = <0>;
	378	compatible = "fsl,imx27-cspi";
	379	reg = <0x10017000 0x1000>;
	380	interrupts = <6>;
ea336fa8 AS	381	clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
ea336fa8 AS	382	<&clks IMX27_CLK_PER2_GATE>;
c20736f1	383	clock-names = "ipg", "per";
9f0749e3 SH	384	status = "disabled";
	385	};
	386
ca26d041	387	gpt4: timer@10019000 {
afde1312	388	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	389	reg = <0x10019000 0x1000>;
ca26d041 SH	390	interrupts = <4>;
ea336fa8 AS	391	clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
ea336fa8 AS	392	<&clks IMX27_CLK_PER1_GATE>;
b700c119	393	clock-names = "ipg", "per";
ca26d041 SH	394	};
	395
	396	gpt5: timer@1001a000 {
afde1312	397	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	398	reg = <0x1001a000 0x1000>;
ca26d041 SH	399	interrupts = <3>;
ea336fa8 AS	400	clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
ea336fa8 AS	401	<&clks IMX27_CLK_PER1_GATE>;
b700c119	402	clock-names = "ipg", "per";
ca26d041 SH	403	};
ca26d041 SH	404
0c456cfa	405	uart5: serial@1001b000 {
9f0749e3 SH	406	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	407	reg = <0x1001b000 0x1000>;
	408	interrupts = <49>;
ea336fa8 AS	409	clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
ea336fa8 AS	410	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	411	clock-names = "ipg", "per";
9f0749e3 SH	412	status = "disabled";
	413	};
	414
0c456cfa	415	uart6: serial@1001c000 {
9f0749e3 SH	416	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	417	reg = <0x1001c000 0x1000>;
	418	interrupts = <48>;
ea336fa8 AS	419	clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
ea336fa8 AS	420	<&clks IMX27_CLK_PER1_GATE>;
c20736f1	421	clock-names = "ipg", "per";
9f0749e3 SH	422	status = "disabled";
	423	};
	424
	425	i2c2: i2c@1001d000 {
	426	#address-cells = <1>;
	427	#size-cells = <0>;
5bdfba29	428	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	429	reg = <0x1001d000 0x1000>;
9f0749e3 SH	430	interrupts = <1>;
ea336fa8	431	clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
9f0749e3 SH	432	status = "disabled";
	433	};
	434
0e7b01aa AS	435	sdhci3: sdhci@1001e000 {
	436	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	437	reg = <0x1001e000 0x1000>;
	438	interrupts = <9>;
ea336fa8 AS	439	clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
ea336fa8 AS	440	<&clks IMX27_CLK_PER2_GATE>;
0e7b01aa AS	441	clock-names = "ipg", "per";
	442	dmas = <&dma 36>;
	443	dma-names = "rx-tx";
	444	status = "disabled";
	445	};
	446
ca26d041	447	gpt6: timer@1001f000 {
afde1312	448	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
ca26d041 SH	449	reg = <0x1001f000 0x1000>;
ca26d041 SH	450	interrupts = <2>;
ea336fa8 AS	451	clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
ea336fa8 AS	452	<&clks IMX27_CLK_PER1_GATE>;
b700c119	453	clock-names = "ipg", "per";
ca26d041	454	};
3e24b05b FE	455	};
	456
	457	aipi@10020000 { /* AIPI2 */
	458	compatible = "fsl,aipi-bus", "simple-bus";
	459	#address-cells = <1>;
	460	#size-cells = <1>;
	461	reg = <0x10020000 0x20000>;
	462	ranges;
	463
5e57b241 MP	464	fb: fb@10021000 {
	465	compatible = "fsl,imx27-fb", "fsl,imx21-fb";
	466	interrupts = <61>;
	467	reg = <0x10021000 0x1000>;
ea336fa8 AS	468	clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
	469	<&clks IMX27_CLK_LCDC_AHB_GATE>,
	470	<&clks IMX27_CLK_PER3_GATE>;
5e57b241 MP	471	clock-names = "ipg", "ahb", "per";
	472	status = "disabled";
	473	};
	474
93b331ce	475	coda: coda@10023000 {
71946619	476	compatible = "fsl,imx27-vpu", "cnm,codadx6";
93b331ce AS	477	reg = <0x10023000 0x0200>;
93b331ce AS	478	interrupts = <53>;
ea336fa8 AS	479	clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
ea336fa8 AS	480	<&clks IMX27_CLK_VPU_AHB_GATE>;
93b331ce AS	481	clock-names = "per", "ahb";
	482	iram = <&iram>;
	483	};
	484
a2e502c2 AS	485	usbotg: usb@10024000 {
	486	compatible = "fsl,imx27-usb";
	487	reg = <0x10024000 0x200>;
	488	interrupts = <56>;
ea336fa8	489	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2	490	fsl,usbmisc = <&usbmisc 0>;
a2e502c2 AS	491	status = "disabled";
	492	};
	493
	494	usbh1: usb@10024200 {
	495	compatible = "fsl,imx27-usb";
	496	reg = <0x10024200 0x200>;
	497	interrupts = <54>;
ea336fa8	498	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2	499	fsl,usbmisc = <&usbmisc 1>;
3ec481ed	500	dr_mode = "host";
a2e502c2 AS	501	status = "disabled";
	502	};
	503
	504	usbh2: usb@10024400 {
	505	compatible = "fsl,imx27-usb";
	506	reg = <0x10024400 0x200>;
	507	interrupts = <55>;
ea336fa8	508	clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
a2e502c2	509	fsl,usbmisc = <&usbmisc 2>;
3ec481ed	510	dr_mode = "host";
a2e502c2 AS	511	status = "disabled";
	512	};
	513
	514	usbmisc: usbmisc@10024600 {
	515	#index-cells = <1>;
	516	compatible = "fsl,imx27-usbmisc";
	517	reg = <0x10024600 0x200>;
ea336fa8	518	clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
a2e502c2 AS	519	};
a2e502c2 AS	520
e4b6a056 AS	521	sahara2: sahara@10025000 {
	522	compatible = "fsl,imx27-sahara";
	523	reg = <0x10025000 0x1000>;
	524	interrupts = <59>;
ea336fa8 AS	525	clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
ea336fa8 AS	526	<&clks IMX27_CLK_SAHARA_AHB_GATE>;
e4b6a056 AS	527	clock-names = "ipg", "ahb";
	528	};
	529
93b331ce AS	530	clks: ccm@10027000{
	531	compatible = "fsl,imx27-ccm";
	532	reg = <0x10027000 0x1000>;
	533	#clock-cells = <1>;
	534	};
	535
d36afcd4 AS	536	iim: iim@10028000 {
	537	compatible = "fsl,imx27-iim";
	538	reg = <0x10028000 0x1000>;
	539	interrupts = <62>;
ea336fa8	540	clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
d36afcd4 AS	541	};
d36afcd4 AS	542
0c456cfa	543	fec: ethernet@1002b000 {
9f0749e3	544	compatible = "fsl,imx27-fec";
a29ef819	545	reg = <0x1002b000 0x1000>;
9f0749e3	546	interrupts = <50>;
ea336fa8 AS	547	clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
ea336fa8 AS	548	<&clks IMX27_CLK_FEC_AHB_GATE>;
c0b357c0	549	clock-names = "ipg", "ahb";
9f0749e3 SH	550	status = "disabled";
	551	};
	552	};
7b7d6727 SH	553
7b7d6727 SH	554	nfc: nand@d8000000 {
37787360 UKK	555	#address-cells = <1>;
37787360 UKK	556	#size-cells = <1>;
37787360 UKK	557	compatible = "fsl,imx27-nand";
	558	reg = <0xd8000000 0x1000>;
	559	interrupts = <29>;
ea336fa8	560	clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
37787360 UKK	561	status = "disabled";
37787360 UKK	562	};
ff1450f6	563
0912f594 AS	564	weim: weim@d8002000 {
	565	#address-cells = <2>;
	566	#size-cells = <1>;
	567	compatible = "fsl,imx27-weim";
	568	reg = <0xd8002000 0x1000>;
ea336fa8	569	clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
0912f594 AS	570	ranges = <
	571	0 0 0xc0000000 0x08000000
	572	1 0 0xc8000000 0x08000000
	573	2 0 0xd0000000 0x02000000
	574	3 0 0xd2000000 0x02000000
	575	4 0 0xd4000000 0x02000000
	576	5 0 0xd6000000 0x02000000
	577	>;
	578	status = "disabled";
	579	};
	580
ff1450f6 AS	581	iram: iram@ffff4c00 {
	582	compatible = "mmio-sram";
	583	reg = <0xffff4c00 0xb400>;
	584	};
9f0749e3 SH	585	};
9f0749e3 SH	586	};