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9f0749e3 SH |
1 | /* |
2 | * Copyright 2012 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
36dffd8f | 12 | #include "skeleton.dtsi" |
9f0749e3 SH |
13 | |
14 | / { | |
15 | aliases { | |
16 | serial0 = &uart1; | |
17 | serial1 = &uart2; | |
18 | serial2 = &uart3; | |
19 | serial3 = &uart4; | |
20 | serial4 = &uart5; | |
21 | serial5 = &uart6; | |
5230f8fe SG |
22 | gpio0 = &gpio1; |
23 | gpio1 = &gpio2; | |
24 | gpio2 = &gpio3; | |
25 | gpio3 = &gpio4; | |
26 | gpio4 = &gpio5; | |
27 | gpio5 = &gpio6; | |
9f0749e3 SH |
28 | }; |
29 | ||
30 | avic: avic-interrupt-controller@e0000000 { | |
31 | compatible = "fsl,imx27-avic", "fsl,avic"; | |
32 | interrupt-controller; | |
33 | #interrupt-cells = <1>; | |
34 | reg = <0x10040000 0x1000>; | |
35 | }; | |
36 | ||
37 | clocks { | |
38 | #address-cells = <1>; | |
39 | #size-cells = <0>; | |
40 | ||
41 | osc26m { | |
42 | compatible = "fsl,imx-osc26m", "fixed-clock"; | |
43 | clock-frequency = <26000000>; | |
44 | }; | |
45 | }; | |
46 | ||
47 | soc { | |
48 | #address-cells = <1>; | |
49 | #size-cells = <1>; | |
50 | compatible = "simple-bus"; | |
51 | interrupt-parent = <&avic>; | |
52 | ranges; | |
53 | ||
54 | aipi@10000000 { /* AIPI1 */ | |
55 | compatible = "fsl,aipi-bus", "simple-bus"; | |
56 | #address-cells = <1>; | |
57 | #size-cells = <1>; | |
3e24b05b | 58 | reg = <0x10000000 0x20000>; |
9f0749e3 SH |
59 | ranges; |
60 | ||
7b7d6727 | 61 | wdog: wdog@10002000 { |
9f0749e3 | 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
ca26d041 | 63 | reg = <0x10002000 0x1000>; |
9f0749e3 | 64 | interrupts = <27>; |
c20736f1 | 65 | clocks = <&clks 0>; |
9f0749e3 SH |
66 | }; |
67 | ||
ca26d041 SH |
68 | gpt1: timer@10003000 { |
69 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
70 | reg = <0x10003000 0x1000>; | |
71 | interrupts = <26>; | |
b700c119 SH |
72 | clocks = <&clks 46>, <&clks 61>; |
73 | clock-names = "ipg", "per"; | |
ca26d041 SH |
74 | }; |
75 | ||
76 | gpt2: timer@10004000 { | |
77 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
78 | reg = <0x10004000 0x1000>; | |
79 | interrupts = <25>; | |
b700c119 SH |
80 | clocks = <&clks 45>, <&clks 61>; |
81 | clock-names = "ipg", "per"; | |
ca26d041 SH |
82 | }; |
83 | ||
84 | gpt3: timer@10005000 { | |
85 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
86 | reg = <0x10005000 0x1000>; | |
87 | interrupts = <24>; | |
b700c119 SH |
88 | clocks = <&clks 44>, <&clks 61>; |
89 | clock-names = "ipg", "per"; | |
ca26d041 SH |
90 | }; |
91 | ||
08f4881a GGM |
92 | pwm0: pwm@10006000 { |
93 | compatible = "fsl,imx27-pwm"; | |
94 | reg = <0x10006000 0x1000>; | |
95 | interrupts = <23>; | |
96 | clocks = <&clks 34>, <&clks 61>; | |
97 | clock-names = "ipg", "per"; | |
98 | }; | |
99 | ||
0c456cfa | 100 | uart1: serial@1000a000 { |
9f0749e3 SH |
101 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
102 | reg = <0x1000a000 0x1000>; | |
103 | interrupts = <20>; | |
c20736f1 FE |
104 | clocks = <&clks 81>, <&clks 61>; |
105 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
106 | status = "disabled"; |
107 | }; | |
108 | ||
0c456cfa | 109 | uart2: serial@1000b000 { |
9f0749e3 SH |
110 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
111 | reg = <0x1000b000 0x1000>; | |
112 | interrupts = <19>; | |
c20736f1 FE |
113 | clocks = <&clks 80>, <&clks 61>; |
114 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
115 | status = "disabled"; |
116 | }; | |
117 | ||
0c456cfa | 118 | uart3: serial@1000c000 { |
9f0749e3 SH |
119 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
120 | reg = <0x1000c000 0x1000>; | |
121 | interrupts = <18>; | |
c20736f1 FE |
122 | clocks = <&clks 79>, <&clks 61>; |
123 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
124 | status = "disabled"; |
125 | }; | |
126 | ||
0c456cfa | 127 | uart4: serial@1000d000 { |
9f0749e3 SH |
128 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
129 | reg = <0x1000d000 0x1000>; | |
130 | interrupts = <17>; | |
c20736f1 FE |
131 | clocks = <&clks 78>, <&clks 61>; |
132 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
133 | status = "disabled"; |
134 | }; | |
135 | ||
136 | cspi1: cspi@1000e000 { | |
137 | #address-cells = <1>; | |
138 | #size-cells = <0>; | |
139 | compatible = "fsl,imx27-cspi"; | |
140 | reg = <0x1000e000 0x1000>; | |
141 | interrupts = <16>; | |
37523dc5 | 142 | clocks = <&clks 53>, <&clks 53>; |
c20736f1 | 143 | clock-names = "ipg", "per"; |
9f0749e3 SH |
144 | status = "disabled"; |
145 | }; | |
146 | ||
147 | cspi2: cspi@1000f000 { | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | compatible = "fsl,imx27-cspi"; | |
151 | reg = <0x1000f000 0x1000>; | |
152 | interrupts = <15>; | |
37523dc5 | 153 | clocks = <&clks 52>, <&clks 52>; |
c20736f1 | 154 | clock-names = "ipg", "per"; |
9f0749e3 SH |
155 | status = "disabled"; |
156 | }; | |
157 | ||
158 | i2c1: i2c@10012000 { | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
5bdfba29 | 161 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
162 | reg = <0x10012000 0x1000>; |
163 | interrupts = <12>; | |
c20736f1 | 164 | clocks = <&clks 40>; |
9f0749e3 SH |
165 | status = "disabled"; |
166 | }; | |
167 | ||
168 | gpio1: gpio@10015000 { | |
169 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
170 | reg = <0x10015000 0x100>; | |
171 | interrupts = <8>; | |
172 | gpio-controller; | |
173 | #gpio-cells = <2>; | |
174 | interrupt-controller; | |
88cde8b7 | 175 | #interrupt-cells = <2>; |
9f0749e3 SH |
176 | }; |
177 | ||
178 | gpio2: gpio@10015100 { | |
179 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
180 | reg = <0x10015100 0x100>; | |
181 | interrupts = <8>; | |
182 | gpio-controller; | |
183 | #gpio-cells = <2>; | |
184 | interrupt-controller; | |
88cde8b7 | 185 | #interrupt-cells = <2>; |
9f0749e3 SH |
186 | }; |
187 | ||
188 | gpio3: gpio@10015200 { | |
189 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
190 | reg = <0x10015200 0x100>; | |
191 | interrupts = <8>; | |
192 | gpio-controller; | |
193 | #gpio-cells = <2>; | |
194 | interrupt-controller; | |
88cde8b7 | 195 | #interrupt-cells = <2>; |
9f0749e3 SH |
196 | }; |
197 | ||
198 | gpio4: gpio@10015300 { | |
199 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
200 | reg = <0x10015300 0x100>; | |
201 | interrupts = <8>; | |
202 | gpio-controller; | |
203 | #gpio-cells = <2>; | |
204 | interrupt-controller; | |
88cde8b7 | 205 | #interrupt-cells = <2>; |
9f0749e3 SH |
206 | }; |
207 | ||
208 | gpio5: gpio@10015400 { | |
209 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
210 | reg = <0x10015400 0x100>; | |
211 | interrupts = <8>; | |
212 | gpio-controller; | |
213 | #gpio-cells = <2>; | |
214 | interrupt-controller; | |
88cde8b7 | 215 | #interrupt-cells = <2>; |
9f0749e3 SH |
216 | }; |
217 | ||
218 | gpio6: gpio@10015500 { | |
219 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
220 | reg = <0x10015500 0x100>; | |
221 | interrupts = <8>; | |
222 | gpio-controller; | |
223 | #gpio-cells = <2>; | |
224 | interrupt-controller; | |
88cde8b7 | 225 | #interrupt-cells = <2>; |
9f0749e3 SH |
226 | }; |
227 | ||
228 | cspi3: cspi@10017000 { | |
229 | #address-cells = <1>; | |
230 | #size-cells = <0>; | |
231 | compatible = "fsl,imx27-cspi"; | |
232 | reg = <0x10017000 0x1000>; | |
233 | interrupts = <6>; | |
37523dc5 | 234 | clocks = <&clks 51>, <&clks 51>; |
c20736f1 | 235 | clock-names = "ipg", "per"; |
9f0749e3 SH |
236 | status = "disabled"; |
237 | }; | |
238 | ||
ca26d041 SH |
239 | gpt4: timer@10019000 { |
240 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
241 | reg = <0x10019000 0x1000>; | |
242 | interrupts = <4>; | |
b700c119 SH |
243 | clocks = <&clks 43>, <&clks 61>; |
244 | clock-names = "ipg", "per"; | |
ca26d041 SH |
245 | }; |
246 | ||
247 | gpt5: timer@1001a000 { | |
248 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
249 | reg = <0x1001a000 0x1000>; | |
250 | interrupts = <3>; | |
b700c119 SH |
251 | clocks = <&clks 42>, <&clks 61>; |
252 | clock-names = "ipg", "per"; | |
ca26d041 SH |
253 | }; |
254 | ||
0c456cfa | 255 | uart5: serial@1001b000 { |
9f0749e3 SH |
256 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
257 | reg = <0x1001b000 0x1000>; | |
258 | interrupts = <49>; | |
c20736f1 FE |
259 | clocks = <&clks 77>, <&clks 61>; |
260 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
261 | status = "disabled"; |
262 | }; | |
263 | ||
0c456cfa | 264 | uart6: serial@1001c000 { |
9f0749e3 SH |
265 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
266 | reg = <0x1001c000 0x1000>; | |
267 | interrupts = <48>; | |
c20736f1 FE |
268 | clocks = <&clks 78>, <&clks 61>; |
269 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
270 | status = "disabled"; |
271 | }; | |
272 | ||
273 | i2c2: i2c@1001d000 { | |
274 | #address-cells = <1>; | |
275 | #size-cells = <0>; | |
5bdfba29 | 276 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
277 | reg = <0x1001d000 0x1000>; |
278 | interrupts = <1>; | |
c20736f1 | 279 | clocks = <&clks 39>; |
9f0749e3 SH |
280 | status = "disabled"; |
281 | }; | |
282 | ||
ca26d041 SH |
283 | gpt6: timer@1001f000 { |
284 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
285 | reg = <0x1001f000 0x1000>; | |
286 | interrupts = <2>; | |
b700c119 SH |
287 | clocks = <&clks 41>, <&clks 61>; |
288 | clock-names = "ipg", "per"; | |
ca26d041 | 289 | }; |
3e24b05b FE |
290 | }; |
291 | ||
292 | aipi@10020000 { /* AIPI2 */ | |
293 | compatible = "fsl,aipi-bus", "simple-bus"; | |
294 | #address-cells = <1>; | |
295 | #size-cells = <1>; | |
296 | reg = <0x10020000 0x20000>; | |
297 | ranges; | |
298 | ||
0c456cfa | 299 | fec: ethernet@1002b000 { |
9f0749e3 SH |
300 | compatible = "fsl,imx27-fec"; |
301 | reg = <0x1002b000 0x4000>; | |
302 | interrupts = <50>; | |
c20736f1 FE |
303 | clocks = <&clks 48>, <&clks 67>, <&clks 0>; |
304 | clock-names = "ipg", "ahb", "ptp"; | |
9f0749e3 SH |
305 | status = "disabled"; |
306 | }; | |
c20736f1 FE |
307 | |
308 | clks: ccm@10027000{ | |
309 | compatible = "fsl,imx27-ccm"; | |
310 | reg = <0x10027000 0x1000>; | |
311 | #clock-cells = <1>; | |
312 | }; | |
9f0749e3 | 313 | }; |
7b7d6727 | 314 | |
c20736f1 | 315 | |
7b7d6727 | 316 | nfc: nand@d8000000 { |
37787360 UKK |
317 | #address-cells = <1>; |
318 | #size-cells = <1>; | |
319 | ||
320 | compatible = "fsl,imx27-nand"; | |
321 | reg = <0xd8000000 0x1000>; | |
322 | interrupts = <29>; | |
c20736f1 | 323 | clocks = <&clks 54>; |
37787360 UKK |
324 | status = "disabled"; |
325 | }; | |
9f0749e3 SH |
326 | }; |
327 | }; |