Commit | Line | Data |
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9f0749e3 SH |
1 | /* |
2 | * Copyright 2012 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
36dffd8f | 12 | #include "skeleton.dtsi" |
9f0749e3 SH |
13 | |
14 | / { | |
15 | aliases { | |
5230f8fe SG |
16 | gpio0 = &gpio1; |
17 | gpio1 = &gpio2; | |
18 | gpio2 = &gpio3; | |
19 | gpio3 = &gpio4; | |
20 | gpio4 = &gpio5; | |
21 | gpio5 = &gpio6; | |
6a3c0b39 SH |
22 | i2c0 = &i2c1; |
23 | i2c1 = &i2c2; | |
24 | serial0 = &uart1; | |
25 | serial1 = &uart2; | |
26 | serial2 = &uart3; | |
27 | serial3 = &uart4; | |
28 | serial4 = &uart5; | |
29 | serial5 = &uart6; | |
a5a641a1 AS |
30 | spi0 = &cspi1; |
31 | spi1 = &cspi2; | |
32 | spi2 = &cspi3; | |
9f0749e3 SH |
33 | }; |
34 | ||
6189bc34 FE |
35 | aitc: aitc-interrupt-controller@e0000000 { |
36 | compatible = "fsl,imx27-aitc", "fsl,avic"; | |
9f0749e3 SH |
37 | interrupt-controller; |
38 | #interrupt-cells = <1>; | |
39 | reg = <0x10040000 0x1000>; | |
40 | }; | |
41 | ||
42 | clocks { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | osc26m { | |
47 | compatible = "fsl,imx-osc26m", "fixed-clock"; | |
48 | clock-frequency = <26000000>; | |
49 | }; | |
50 | }; | |
51 | ||
dc1d0f91 MP |
52 | cpus { |
53 | #size-cells = <0>; | |
54 | #address-cells = <1>; | |
55 | ||
48568be6 | 56 | cpu: cpu@0 { |
dc1d0f91 MP |
57 | device_type = "cpu"; |
58 | compatible = "arm,arm926ej-s"; | |
59 | operating-points = < | |
98a3e804 AS |
60 | /* kHz uV */ |
61 | 266000 1300000 | |
62 | 399000 1450000 | |
dc1d0f91 | 63 | >; |
8defcb53 | 64 | clock-latency = <62500>; |
dc1d0f91 | 65 | clocks = <&clks 18>; |
98a3e804 | 66 | voltage-tolerance = <5>; |
dc1d0f91 MP |
67 | }; |
68 | }; | |
69 | ||
9f0749e3 SH |
70 | soc { |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | compatible = "simple-bus"; | |
6189bc34 | 74 | interrupt-parent = <&aitc>; |
9f0749e3 SH |
75 | ranges; |
76 | ||
77 | aipi@10000000 { /* AIPI1 */ | |
78 | compatible = "fsl,aipi-bus", "simple-bus"; | |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
3e24b05b | 81 | reg = <0x10000000 0x20000>; |
9f0749e3 SH |
82 | ranges; |
83 | ||
b858c34f AS |
84 | dma: dma@10001000 { |
85 | compatible = "fsl,imx27-dma"; | |
86 | reg = <0x10001000 0x1000>; | |
87 | interrupts = <32>; | |
88 | clocks = <&clks 50>, <&clks 70>; | |
89 | clock-names = "ipg", "ahb"; | |
90 | #dma-cells = <1>; | |
91 | #dma-channels = <16>; | |
92 | }; | |
93 | ||
7b7d6727 | 94 | wdog: wdog@10002000 { |
9f0749e3 | 95 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
ca26d041 | 96 | reg = <0x10002000 0x1000>; |
9f0749e3 | 97 | interrupts = <27>; |
3c0e2a22 | 98 | clocks = <&clks 74>; |
9f0749e3 SH |
99 | }; |
100 | ||
ca26d041 SH |
101 | gpt1: timer@10003000 { |
102 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
103 | reg = <0x10003000 0x1000>; | |
104 | interrupts = <26>; | |
b700c119 SH |
105 | clocks = <&clks 46>, <&clks 61>; |
106 | clock-names = "ipg", "per"; | |
ca26d041 SH |
107 | }; |
108 | ||
109 | gpt2: timer@10004000 { | |
110 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
111 | reg = <0x10004000 0x1000>; | |
112 | interrupts = <25>; | |
b700c119 SH |
113 | clocks = <&clks 45>, <&clks 61>; |
114 | clock-names = "ipg", "per"; | |
ca26d041 SH |
115 | }; |
116 | ||
117 | gpt3: timer@10005000 { | |
118 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
119 | reg = <0x10005000 0x1000>; | |
120 | interrupts = <24>; | |
b700c119 SH |
121 | clocks = <&clks 44>, <&clks 61>; |
122 | clock-names = "ipg", "per"; | |
ca26d041 SH |
123 | }; |
124 | ||
a392d044 | 125 | pwm: pwm@10006000 { |
443b6585 | 126 | #pwm-cells = <2>; |
08f4881a GGM |
127 | compatible = "fsl,imx27-pwm"; |
128 | reg = <0x10006000 0x1000>; | |
129 | interrupts = <23>; | |
130 | clocks = <&clks 34>, <&clks 61>; | |
131 | clock-names = "ipg", "per"; | |
132 | }; | |
133 | ||
6c04ad22 AS |
134 | kpp: kpp@10008000 { |
135 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; | |
136 | reg = <0x10008000 0x1000>; | |
137 | interrupts = <21>; | |
138 | clocks = <&clks 37>; | |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
6a486b7e MP |
142 | owire: owire@10009000 { |
143 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; | |
144 | reg = <0x10009000 0x1000>; | |
145 | clocks = <&clks 35>; | |
146 | status = "disabled"; | |
147 | }; | |
148 | ||
0c456cfa | 149 | uart1: serial@1000a000 { |
9f0749e3 SH |
150 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
151 | reg = <0x1000a000 0x1000>; | |
152 | interrupts = <20>; | |
c20736f1 FE |
153 | clocks = <&clks 81>, <&clks 61>; |
154 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
155 | status = "disabled"; |
156 | }; | |
157 | ||
0c456cfa | 158 | uart2: serial@1000b000 { |
9f0749e3 SH |
159 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
160 | reg = <0x1000b000 0x1000>; | |
161 | interrupts = <19>; | |
c20736f1 FE |
162 | clocks = <&clks 80>, <&clks 61>; |
163 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
164 | status = "disabled"; |
165 | }; | |
166 | ||
0c456cfa | 167 | uart3: serial@1000c000 { |
9f0749e3 SH |
168 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
169 | reg = <0x1000c000 0x1000>; | |
170 | interrupts = <18>; | |
c20736f1 FE |
171 | clocks = <&clks 79>, <&clks 61>; |
172 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
173 | status = "disabled"; |
174 | }; | |
175 | ||
0c456cfa | 176 | uart4: serial@1000d000 { |
9f0749e3 SH |
177 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
178 | reg = <0x1000d000 0x1000>; | |
179 | interrupts = <17>; | |
c20736f1 FE |
180 | clocks = <&clks 78>, <&clks 61>; |
181 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
182 | status = "disabled"; |
183 | }; | |
184 | ||
185 | cspi1: cspi@1000e000 { | |
186 | #address-cells = <1>; | |
187 | #size-cells = <0>; | |
188 | compatible = "fsl,imx27-cspi"; | |
189 | reg = <0x1000e000 0x1000>; | |
190 | interrupts = <16>; | |
7c37b617 | 191 | clocks = <&clks 53>, <&clks 60>; |
c20736f1 | 192 | clock-names = "ipg", "per"; |
9f0749e3 SH |
193 | status = "disabled"; |
194 | }; | |
195 | ||
196 | cspi2: cspi@1000f000 { | |
197 | #address-cells = <1>; | |
198 | #size-cells = <0>; | |
199 | compatible = "fsl,imx27-cspi"; | |
200 | reg = <0x1000f000 0x1000>; | |
201 | interrupts = <15>; | |
7c37b617 | 202 | clocks = <&clks 52>, <&clks 60>; |
c20736f1 | 203 | clock-names = "ipg", "per"; |
9f0749e3 SH |
204 | status = "disabled"; |
205 | }; | |
206 | ||
207 | i2c1: i2c@10012000 { | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
5bdfba29 | 210 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
211 | reg = <0x10012000 0x1000>; |
212 | interrupts = <12>; | |
c20736f1 | 213 | clocks = <&clks 40>; |
9f0749e3 SH |
214 | status = "disabled"; |
215 | }; | |
216 | ||
0e7b01aa AS |
217 | sdhci1: sdhci@10013000 { |
218 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
219 | reg = <0x10013000 0x1000>; | |
220 | interrupts = <11>; | |
221 | clocks = <&clks 30>, <&clks 60>; | |
222 | clock-names = "ipg", "per"; | |
223 | dmas = <&dma 7>; | |
224 | dma-names = "rx-tx"; | |
225 | status = "disabled"; | |
226 | }; | |
227 | ||
228 | sdhci2: sdhci@10014000 { | |
229 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
230 | reg = <0x10014000 0x1000>; | |
231 | interrupts = <10>; | |
232 | clocks = <&clks 29>, <&clks 60>; | |
233 | clock-names = "ipg", "per"; | |
234 | dmas = <&dma 6>; | |
235 | dma-names = "rx-tx"; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
9f0749e3 SH |
239 | gpio1: gpio@10015000 { |
240 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
241 | reg = <0x10015000 0x100>; | |
242 | interrupts = <8>; | |
243 | gpio-controller; | |
244 | #gpio-cells = <2>; | |
245 | interrupt-controller; | |
88cde8b7 | 246 | #interrupt-cells = <2>; |
9f0749e3 SH |
247 | }; |
248 | ||
249 | gpio2: gpio@10015100 { | |
250 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
251 | reg = <0x10015100 0x100>; | |
252 | interrupts = <8>; | |
253 | gpio-controller; | |
254 | #gpio-cells = <2>; | |
255 | interrupt-controller; | |
88cde8b7 | 256 | #interrupt-cells = <2>; |
9f0749e3 SH |
257 | }; |
258 | ||
259 | gpio3: gpio@10015200 { | |
260 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
261 | reg = <0x10015200 0x100>; | |
262 | interrupts = <8>; | |
263 | gpio-controller; | |
264 | #gpio-cells = <2>; | |
265 | interrupt-controller; | |
88cde8b7 | 266 | #interrupt-cells = <2>; |
9f0749e3 SH |
267 | }; |
268 | ||
269 | gpio4: gpio@10015300 { | |
270 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
271 | reg = <0x10015300 0x100>; | |
272 | interrupts = <8>; | |
273 | gpio-controller; | |
274 | #gpio-cells = <2>; | |
275 | interrupt-controller; | |
88cde8b7 | 276 | #interrupt-cells = <2>; |
9f0749e3 SH |
277 | }; |
278 | ||
279 | gpio5: gpio@10015400 { | |
280 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
281 | reg = <0x10015400 0x100>; | |
282 | interrupts = <8>; | |
283 | gpio-controller; | |
284 | #gpio-cells = <2>; | |
285 | interrupt-controller; | |
88cde8b7 | 286 | #interrupt-cells = <2>; |
9f0749e3 SH |
287 | }; |
288 | ||
289 | gpio6: gpio@10015500 { | |
290 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
291 | reg = <0x10015500 0x100>; | |
292 | interrupts = <8>; | |
293 | gpio-controller; | |
294 | #gpio-cells = <2>; | |
295 | interrupt-controller; | |
88cde8b7 | 296 | #interrupt-cells = <2>; |
9f0749e3 SH |
297 | }; |
298 | ||
6e228e80 AS |
299 | audmux: audmux@10016000 { |
300 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; | |
301 | reg = <0x10016000 0x1000>; | |
302 | clocks = <&clks 0>; | |
303 | clock-names = "audmux"; | |
1c04ab0f | 304 | status = "disabled"; |
6e228e80 AS |
305 | }; |
306 | ||
9f0749e3 SH |
307 | cspi3: cspi@10017000 { |
308 | #address-cells = <1>; | |
309 | #size-cells = <0>; | |
310 | compatible = "fsl,imx27-cspi"; | |
311 | reg = <0x10017000 0x1000>; | |
312 | interrupts = <6>; | |
7c37b617 | 313 | clocks = <&clks 51>, <&clks 60>; |
c20736f1 | 314 | clock-names = "ipg", "per"; |
9f0749e3 SH |
315 | status = "disabled"; |
316 | }; | |
317 | ||
ca26d041 SH |
318 | gpt4: timer@10019000 { |
319 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
320 | reg = <0x10019000 0x1000>; | |
321 | interrupts = <4>; | |
b700c119 SH |
322 | clocks = <&clks 43>, <&clks 61>; |
323 | clock-names = "ipg", "per"; | |
ca26d041 SH |
324 | }; |
325 | ||
326 | gpt5: timer@1001a000 { | |
327 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
328 | reg = <0x1001a000 0x1000>; | |
329 | interrupts = <3>; | |
b700c119 SH |
330 | clocks = <&clks 42>, <&clks 61>; |
331 | clock-names = "ipg", "per"; | |
ca26d041 SH |
332 | }; |
333 | ||
0c456cfa | 334 | uart5: serial@1001b000 { |
9f0749e3 SH |
335 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
336 | reg = <0x1001b000 0x1000>; | |
337 | interrupts = <49>; | |
c20736f1 FE |
338 | clocks = <&clks 77>, <&clks 61>; |
339 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
340 | status = "disabled"; |
341 | }; | |
342 | ||
0c456cfa | 343 | uart6: serial@1001c000 { |
9f0749e3 SH |
344 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
345 | reg = <0x1001c000 0x1000>; | |
346 | interrupts = <48>; | |
c20736f1 FE |
347 | clocks = <&clks 78>, <&clks 61>; |
348 | clock-names = "ipg", "per"; | |
9f0749e3 SH |
349 | status = "disabled"; |
350 | }; | |
351 | ||
352 | i2c2: i2c@1001d000 { | |
353 | #address-cells = <1>; | |
354 | #size-cells = <0>; | |
5bdfba29 | 355 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
356 | reg = <0x1001d000 0x1000>; |
357 | interrupts = <1>; | |
c20736f1 | 358 | clocks = <&clks 39>; |
9f0749e3 SH |
359 | status = "disabled"; |
360 | }; | |
361 | ||
0e7b01aa AS |
362 | sdhci3: sdhci@1001e000 { |
363 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
364 | reg = <0x1001e000 0x1000>; | |
365 | interrupts = <9>; | |
366 | clocks = <&clks 28>, <&clks 60>; | |
367 | clock-names = "ipg", "per"; | |
368 | dmas = <&dma 36>; | |
369 | dma-names = "rx-tx"; | |
370 | status = "disabled"; | |
371 | }; | |
372 | ||
ca26d041 SH |
373 | gpt6: timer@1001f000 { |
374 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
375 | reg = <0x1001f000 0x1000>; | |
376 | interrupts = <2>; | |
b700c119 SH |
377 | clocks = <&clks 41>, <&clks 61>; |
378 | clock-names = "ipg", "per"; | |
ca26d041 | 379 | }; |
3e24b05b FE |
380 | }; |
381 | ||
382 | aipi@10020000 { /* AIPI2 */ | |
383 | compatible = "fsl,aipi-bus", "simple-bus"; | |
384 | #address-cells = <1>; | |
385 | #size-cells = <1>; | |
386 | reg = <0x10020000 0x20000>; | |
387 | ranges; | |
388 | ||
5e57b241 MP |
389 | fb: fb@10021000 { |
390 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; | |
391 | interrupts = <61>; | |
392 | reg = <0x10021000 0x1000>; | |
393 | clocks = <&clks 36>, <&clks 65>, <&clks 59>; | |
394 | clock-names = "ipg", "ahb", "per"; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
93b331ce AS |
398 | coda: coda@10023000 { |
399 | compatible = "fsl,imx27-vpu"; | |
400 | reg = <0x10023000 0x0200>; | |
401 | interrupts = <53>; | |
402 | clocks = <&clks 57>, <&clks 66>; | |
403 | clock-names = "per", "ahb"; | |
404 | iram = <&iram>; | |
405 | }; | |
406 | ||
e4b6a056 AS |
407 | sahara2: sahara@10025000 { |
408 | compatible = "fsl,imx27-sahara"; | |
409 | reg = <0x10025000 0x1000>; | |
410 | interrupts = <59>; | |
411 | clocks = <&clks 32>, <&clks 64>; | |
412 | clock-names = "ipg", "ahb"; | |
413 | }; | |
414 | ||
93b331ce AS |
415 | clks: ccm@10027000{ |
416 | compatible = "fsl,imx27-ccm"; | |
417 | reg = <0x10027000 0x1000>; | |
418 | #clock-cells = <1>; | |
419 | }; | |
420 | ||
d36afcd4 AS |
421 | iim: iim@10028000 { |
422 | compatible = "fsl,imx27-iim"; | |
423 | reg = <0x10028000 0x1000>; | |
424 | interrupts = <62>; | |
425 | clocks = <&clks 38>; | |
426 | }; | |
427 | ||
0c456cfa | 428 | fec: ethernet@1002b000 { |
9f0749e3 SH |
429 | compatible = "fsl,imx27-fec"; |
430 | reg = <0x1002b000 0x4000>; | |
431 | interrupts = <50>; | |
c0b357c0 AS |
432 | clocks = <&clks 48>, <&clks 67>; |
433 | clock-names = "ipg", "ahb"; | |
9f0749e3 SH |
434 | status = "disabled"; |
435 | }; | |
436 | }; | |
7b7d6727 SH |
437 | |
438 | nfc: nand@d8000000 { | |
37787360 UKK |
439 | #address-cells = <1>; |
440 | #size-cells = <1>; | |
37787360 UKK |
441 | compatible = "fsl,imx27-nand"; |
442 | reg = <0xd8000000 0x1000>; | |
443 | interrupts = <29>; | |
c20736f1 | 444 | clocks = <&clks 54>; |
37787360 UKK |
445 | status = "disabled"; |
446 | }; | |
ff1450f6 | 447 | |
0912f594 AS |
448 | weim: weim@d8002000 { |
449 | #address-cells = <2>; | |
450 | #size-cells = <1>; | |
451 | compatible = "fsl,imx27-weim"; | |
452 | reg = <0xd8002000 0x1000>; | |
453 | clocks = <&clks 0>; | |
454 | ranges = < | |
455 | 0 0 0xc0000000 0x08000000 | |
456 | 1 0 0xc8000000 0x08000000 | |
457 | 2 0 0xd0000000 0x02000000 | |
458 | 3 0 0xd2000000 0x02000000 | |
459 | 4 0 0xd4000000 0x02000000 | |
460 | 5 0 0xd6000000 0x02000000 | |
461 | >; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
ff1450f6 AS |
465 | iram: iram@ffff4c00 { |
466 | compatible = "mmio-sram"; | |
467 | reg = <0xffff4c00 0xb400>; | |
468 | }; | |
9f0749e3 SH |
469 | }; |
470 | }; |