[deliverable/linux.git] / arch / arm / boot / dts / imx27.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &cspi1;
		spi1 = &cspi2;
		spi2 = &cspi3;
	};

	aitc: aitc-interrupt-controller@e0000000 {
		compatible = "fsl,imx27-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10040000 0x1000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc26m {
			compatible = "fsl,imx-osc26m", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			operating-points = <
				/* kHz uV */
				266000 1300000
				399000 1450000
			>;
			clock-latency = <62500>;
			clocks = <&clks 18>;
			voltage-tolerance = <5>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@10000000 { /* AIPI1 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10000000 0x20000>;
			ranges;

			dma: dma@10001000 {
				compatible = "fsl,imx27-dma";
				reg = <0x10001000 0x1000>;
				interrupts = <32>;
				clocks = <&clks 50>, <&clks 70>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
				#dma-channels = <16>;
			};

			wdog: wdog@10002000 {
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
				reg = <0x10002000 0x1000>;
				interrupts = <27>;
				clocks = <&clks 74>;
			};

			gpt1: timer@10003000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10003000 0x1000>;
				interrupts = <26>;
				clocks = <&clks 46>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@10004000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10004000 0x1000>;
				interrupts = <25>;
				clocks = <&clks 45>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt3: timer@10005000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10005000 0x1000>;
				interrupts = <24>;
				clocks = <&clks 44>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			pwm: pwm@10006000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx27-pwm";
				reg = <0x10006000 0x1000>;
				interrupts = <23>;
				clocks = <&clks 34>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			kpp: kpp@10008000 {
				compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
				reg = <0x10008000 0x1000>;
				interrupts = <21>;
				clocks = <&clks 37>;
				status = "disabled";
			};

			owire: owire@10009000 {
				compatible = "fsl,imx27-owire", "fsl,imx21-owire";
				reg = <0x10009000 0x1000>;
				clocks = <&clks 35>;
				status = "disabled";
			};

			uart1: serial@1000a000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000a000 0x1000>;
				interrupts = <20>;
				clocks = <&clks 81>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@1000b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000b000 0x1000>;
				interrupts = <19>;
				clocks = <&clks 80>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@1000c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000c000 0x1000>;
				interrupts = <18>;
				clocks = <&clks 79>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@1000d000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000d000 0x1000>;
				interrupts = <17>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi1: cspi@1000e000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000e000 0x1000>;
				interrupts = <16>;
				clocks = <&clks 53>, <&clks 60>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi2: cspi@1000f000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000f000 0x1000>;
				interrupts = <15>;
				clocks = <&clks 52>, <&clks 60>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			ssi1: ssi@10010000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10010000 0x1000>;
				interrupts = <14>;
				clocks = <&clks 26>;
				dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			ssi2: ssi@10011000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
				reg = <0x10011000 0x1000>;
				interrupts = <13>;
				clocks = <&clks 25>;
				dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
				dma-names = "rx0", "tx0", "rx1", "tx1";
				fsl,fifo-depth = <8>;
				status = "disabled";
			};

			i2c1: i2c@10012000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x10012000 0x1000>;
				interrupts = <12>;
				clocks = <&clks 40>;
				status = "disabled";
			};

			sdhci1: sdhci@10013000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10013000 0x1000>;
				interrupts = <11>;
				clocks = <&clks 30>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 7>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			sdhci2: sdhci@10014000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10014000 0x1000>;
				interrupts = <10>;
				clocks = <&clks 29>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 6>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			iomuxc: iomuxc@10015000 {
				compatible = "fsl,imx27-iomuxc";
				reg = <0x10015000 0x600>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio1: gpio@10015000 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015000 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@10015100 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015100 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@10015200 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015200 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@10015300 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015300 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio5: gpio@10015400 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015400 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio6: gpio@10015500 {
					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
					reg = <0x10015500 0x100>;
					interrupts = <8>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			audmux: audmux@10016000 {
				compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
				reg = <0x10016000 0x1000>;
				clocks = <&clks 0>;
				clock-names = "audmux";
				status = "disabled";
			};

			cspi3: cspi@10017000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x10017000 0x1000>;
				interrupts = <6>;
				clocks = <&clks 51>, <&clks 60>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@10019000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10019000 0x1000>;
				interrupts = <4>;
				clocks = <&clks 43>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt5: timer@1001a000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001a000 0x1000>;
				interrupts = <3>;
				clocks = <&clks 42>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			uart5: serial@1001b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001b000 0x1000>;
				interrupts = <49>;
				clocks = <&clks 77>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@1001c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001c000 0x1000>;
				interrupts = <48>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@1001d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x1001d000 0x1000>;
				interrupts = <1>;
				clocks = <&clks 39>;
				status = "disabled";
			};

			sdhci3: sdhci@1001e000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x1001e000 0x1000>;
				interrupts = <9>;
				clocks = <&clks 28>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 36>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			gpt6: timer@1001f000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001f000 0x1000>;
				interrupts = <2>;
				clocks = <&clks 41>, <&clks 61>;
				clock-names = "ipg", "per";
			};
		};

		aipi@10020000 { /* AIPI2 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10020000 0x20000>;
			ranges;

			fb: fb@10021000 {
				compatible = "fsl,imx27-fb", "fsl,imx21-fb";
				interrupts = <61>;
				reg = <0x10021000 0x1000>;
				clocks = <&clks 36>, <&clks 65>, <&clks 59>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			coda: coda@10023000 {
				compatible = "fsl,imx27-vpu";
				reg = <0x10023000 0x0200>;
				interrupts = <53>;
				clocks = <&clks 57>, <&clks 66>;
				clock-names = "per", "ahb";
				iram = <&iram>;
			};

			usbotg: usb@10024000 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024000 0x200>;
				interrupts = <56>;
				clocks = <&clks 75>;
				fsl,usbmisc = <&usbmisc 0>;
				status = "disabled";
			};

			usbh1: usb@10024200 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024200 0x200>;
				interrupts = <54>;
				clocks = <&clks 75>;
				fsl,usbmisc = <&usbmisc 1>;
				status = "disabled";
			};

			usbh2: usb@10024400 {
				compatible = "fsl,imx27-usb";
				reg = <0x10024400 0x200>;
				interrupts = <55>;
				clocks = <&clks 75>;
				fsl,usbmisc = <&usbmisc 2>;
				status = "disabled";
			};

			usbmisc: usbmisc@10024600 {
				#index-cells = <1>;
				compatible = "fsl,imx27-usbmisc";
				reg = <0x10024600 0x200>;
				clocks = <&clks 62>;
			};

			sahara2: sahara@10025000 {
				compatible = "fsl,imx27-sahara";
				reg = <0x10025000 0x1000>;
				interrupts = <59>;
				clocks = <&clks 32>, <&clks 64>;
				clock-names = "ipg", "ahb";
			};

			clks: ccm@10027000{
				compatible = "fsl,imx27-ccm";
				reg = <0x10027000 0x1000>;
				#clock-cells = <1>;
			};

			iim: iim@10028000 {
				compatible = "fsl,imx27-iim";
				reg = <0x10028000 0x1000>;
				interrupts = <62>;
				clocks = <&clks 38>;
			};

			fec: ethernet@1002b000 {
				compatible = "fsl,imx27-fec";
				reg = <0x1002b000 0x4000>;
				interrupts = <50>;
				clocks = <&clks 48>, <&clks 67>;
				clock-names = "ipg", "ahb";
				status = "disabled";
			};
		};

		nfc: nand@d8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,imx27-nand";
			reg = <0xd8000000 0x1000>;
			interrupts = <29>;
			clocks = <&clks 54>;
			status = "disabled";
		};

		weim: weim@d8002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx27-weim";
			reg = <0xd8002000 0x1000>;
			clocks = <&clks 0>;
			ranges = <
				0 0 0xc0000000 0x08000000
				1 0 0xc8000000 0x08000000
				2 0 0xd0000000 0x02000000
				3 0 0xd2000000 0x02000000
				4 0 0xd4000000 0x02000000
				5 0 0xd6000000 0x02000000
			>;
			status = "disabled";
		};

		iram: iram@ffff4c00 {
			compatible = "mmio-sram";
			reg = <0xffff4c00 0xb400>;
		};
	};
};
Commit	Line	Data
9f0749e3 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
36dffd8f	12	#include "skeleton.dtsi"
61664d0b	13	#include "imx27-pinfunc.h"
6ece55b3 AS	14	#include <dt-bindings/interrupt-controller/irq.h>
6ece55b3 AS	15	#include <dt-bindings/gpio/gpio.h>
9f0749e3 SH	16
	17	/ {
	18	aliases {
22970070	19	ethernet0 = &fec;
5230f8fe SG	20	gpio0 = &gpio1;
	21	gpio1 = &gpio2;
	22	gpio2 = &gpio3;
	23	gpio3 = &gpio4;
	24	gpio4 = &gpio5;
	25	gpio5 = &gpio6;
6a3c0b39 SH	26	i2c0 = &i2c1;
	27	i2c1 = &i2c2;
	28	serial0 = &uart1;
	29	serial1 = &uart2;
	30	serial2 = &uart3;
	31	serial3 = &uart4;
	32	serial4 = &uart5;
	33	serial5 = &uart6;
a5a641a1 AS	34	spi0 = &cspi1;
	35	spi1 = &cspi2;
	36	spi2 = &cspi3;
9f0749e3 SH	37	};
9f0749e3 SH	38
6189bc34 FE	39	aitc: aitc-interrupt-controller@e0000000 {
6189bc34 FE	40	compatible = "fsl,imx27-aitc", "fsl,avic";
9f0749e3 SH	41	interrupt-controller;
	42	#interrupt-cells = <1>;
	43	reg = <0x10040000 0x1000>;
	44	};
	45
	46	clocks {
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
	50	osc26m {
	51	compatible = "fsl,imx-osc26m", "fixed-clock";
4b2b4043	52	#clock-cells = <0>;
9f0749e3 SH	53	clock-frequency = <26000000>;
	54	};
	55	};
	56
dc1d0f91 MP	57	cpus {
	58	#size-cells = <0>;
	59	#address-cells = <1>;
	60
48568be6	61	cpu: cpu@0 {
dc1d0f91 MP	62	device_type = "cpu";
	63	compatible = "arm,arm926ej-s";
	64	operating-points = <
98a3e804 AS	65	/* kHz uV */
	66	266000 1300000
	67	399000 1450000
dc1d0f91	68	>;
8defcb53	69	clock-latency = <62500>;
dc1d0f91	70	clocks = <&clks 18>;
98a3e804	71	voltage-tolerance = <5>;
dc1d0f91 MP	72	};
	73	};
	74
9f0749e3 SH	75	soc {
	76	#address-cells = <1>;
	77	#size-cells = <1>;
	78	compatible = "simple-bus";
6189bc34	79	interrupt-parent = <&aitc>;
9f0749e3 SH	80	ranges;
	81
	82	aipi@10000000 { /* AIPI1 */
	83	compatible = "fsl,aipi-bus", "simple-bus";
	84	#address-cells = <1>;
	85	#size-cells = <1>;
3e24b05b	86	reg = <0x10000000 0x20000>;
9f0749e3 SH	87	ranges;
9f0749e3 SH	88
b858c34f AS	89	dma: dma@10001000 {
	90	compatible = "fsl,imx27-dma";
	91	reg = <0x10001000 0x1000>;
	92	interrupts = <32>;
	93	clocks = <&clks 50>, <&clks 70>;
	94	clock-names = "ipg", "ahb";
	95	#dma-cells = <1>;
	96	#dma-channels = <16>;
	97	};
	98
7b7d6727	99	wdog: wdog@10002000 {
9f0749e3	100	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
ca26d041	101	reg = <0x10002000 0x1000>;
9f0749e3	102	interrupts = <27>;
3c0e2a22	103	clocks = <&clks 74>;
9f0749e3 SH	104	};
9f0749e3 SH	105
ca26d041 SH	106	gpt1: timer@10003000 {
	107	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	108	reg = <0x10003000 0x1000>;
	109	interrupts = <26>;
b700c119 SH	110	clocks = <&clks 46>, <&clks 61>;
b700c119 SH	111	clock-names = "ipg", "per";
ca26d041 SH	112	};
	113
	114	gpt2: timer@10004000 {
	115	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	116	reg = <0x10004000 0x1000>;
	117	interrupts = <25>;
b700c119 SH	118	clocks = <&clks 45>, <&clks 61>;
b700c119 SH	119	clock-names = "ipg", "per";
ca26d041 SH	120	};
	121
	122	gpt3: timer@10005000 {
	123	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	124	reg = <0x10005000 0x1000>;
	125	interrupts = <24>;
b700c119 SH	126	clocks = <&clks 44>, <&clks 61>;
b700c119 SH	127	clock-names = "ipg", "per";
ca26d041 SH	128	};
ca26d041 SH	129
a392d044	130	pwm: pwm@10006000 {
443b6585	131	#pwm-cells = <2>;
08f4881a GGM	132	compatible = "fsl,imx27-pwm";
	133	reg = <0x10006000 0x1000>;
	134	interrupts = <23>;
	135	clocks = <&clks 34>, <&clks 61>;
	136	clock-names = "ipg", "per";
	137	};
	138
6c04ad22 AS	139	kpp: kpp@10008000 {
	140	compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
	141	reg = <0x10008000 0x1000>;
	142	interrupts = <21>;
	143	clocks = <&clks 37>;
	144	status = "disabled";
	145	};
	146
6a486b7e MP	147	owire: owire@10009000 {
	148	compatible = "fsl,imx27-owire", "fsl,imx21-owire";
	149	reg = <0x10009000 0x1000>;
	150	clocks = <&clks 35>;
	151	status = "disabled";
	152	};
	153
0c456cfa	154	uart1: serial@1000a000 {
9f0749e3 SH	155	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	156	reg = <0x1000a000 0x1000>;
	157	interrupts = <20>;
c20736f1 FE	158	clocks = <&clks 81>, <&clks 61>;
c20736f1 FE	159	clock-names = "ipg", "per";
9f0749e3 SH	160	status = "disabled";
	161	};
	162
0c456cfa	163	uart2: serial@1000b000 {
9f0749e3 SH	164	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	165	reg = <0x1000b000 0x1000>;
	166	interrupts = <19>;
c20736f1 FE	167	clocks = <&clks 80>, <&clks 61>;
c20736f1 FE	168	clock-names = "ipg", "per";
9f0749e3 SH	169	status = "disabled";
	170	};
	171
0c456cfa	172	uart3: serial@1000c000 {
9f0749e3 SH	173	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	174	reg = <0x1000c000 0x1000>;
	175	interrupts = <18>;
c20736f1 FE	176	clocks = <&clks 79>, <&clks 61>;
c20736f1 FE	177	clock-names = "ipg", "per";
9f0749e3 SH	178	status = "disabled";
	179	};
	180
0c456cfa	181	uart4: serial@1000d000 {
9f0749e3 SH	182	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	183	reg = <0x1000d000 0x1000>;
	184	interrupts = <17>;
c20736f1 FE	185	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	186	clock-names = "ipg", "per";
9f0749e3 SH	187	status = "disabled";
	188	};
	189
	190	cspi1: cspi@1000e000 {
	191	#address-cells = <1>;
	192	#size-cells = <0>;
	193	compatible = "fsl,imx27-cspi";
	194	reg = <0x1000e000 0x1000>;
	195	interrupts = <16>;
7c37b617	196	clocks = <&clks 53>, <&clks 60>;
c20736f1	197	clock-names = "ipg", "per";
9f0749e3 SH	198	status = "disabled";
	199	};
	200
	201	cspi2: cspi@1000f000 {
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	compatible = "fsl,imx27-cspi";
	205	reg = <0x1000f000 0x1000>;
	206	interrupts = <15>;
7c37b617	207	clocks = <&clks 52>, <&clks 60>;
c20736f1	208	clock-names = "ipg", "per";
9f0749e3 SH	209	status = "disabled";
	210	};
	211
ba2d1ea7 AS	212	ssi1: ssi@10010000 {
	213	#sound-dai-cells = <0>;
	214	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	215	reg = <0x10010000 0x1000>;
	216	interrupts = <14>;
	217	clocks = <&clks 26>;
	218	dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
	219	dma-names = "rx0", "tx0", "rx1", "tx1";
	220	fsl,fifo-depth = <8>;
	221	status = "disabled";
	222	};
	223
	224	ssi2: ssi@10011000 {
	225	#sound-dai-cells = <0>;
	226	compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
	227	reg = <0x10011000 0x1000>;
	228	interrupts = <13>;
	229	clocks = <&clks 25>;
	230	dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
	231	dma-names = "rx0", "tx0", "rx1", "tx1";
	232	fsl,fifo-depth = <8>;
	233	status = "disabled";
	234	};
	235
9f0749e3 SH	236	i2c1: i2c@10012000 {
	237	#address-cells = <1>;
	238	#size-cells = <0>;
5bdfba29	239	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	240	reg = <0x10012000 0x1000>;
9f0749e3 SH	241	interrupts = <12>;
c20736f1	242	clocks = <&clks 40>;
9f0749e3 SH	243	status = "disabled";
	244	};
	245
0e7b01aa AS	246	sdhci1: sdhci@10013000 {
	247	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	248	reg = <0x10013000 0x1000>;
	249	interrupts = <11>;
	250	clocks = <&clks 30>, <&clks 60>;
	251	clock-names = "ipg", "per";
	252	dmas = <&dma 7>;
	253	dma-names = "rx-tx";
	254	status = "disabled";
	255	};
	256
	257	sdhci2: sdhci@10014000 {
	258	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	259	reg = <0x10014000 0x1000>;
	260	interrupts = <10>;
	261	clocks = <&clks 29>, <&clks 60>;
	262	clock-names = "ipg", "per";
	263	dmas = <&dma 6>;
	264	dma-names = "rx-tx";
	265	status = "disabled";
	266	};
	267
733f6cae MP	268	iomuxc: iomuxc@10015000 {
	269	compatible = "fsl,imx27-iomuxc";
	270	reg = <0x10015000 0x600>;
	271	#address-cells = <1>;
	272	#size-cells = <1>;
	273	ranges;
	274
	275	gpio1: gpio@10015000 {
	276	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	277	reg = <0x10015000 0x100>;
	278	interrupts = <8>;
	279	gpio-controller;
	280	#gpio-cells = <2>;
	281	interrupt-controller;
	282	#interrupt-cells = <2>;
	283	};
	284
	285	gpio2: gpio@10015100 {
	286	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	287	reg = <0x10015100 0x100>;
	288	interrupts = <8>;
	289	gpio-controller;
	290	#gpio-cells = <2>;
	291	interrupt-controller;
	292	#interrupt-cells = <2>;
	293	};
	294
	295	gpio3: gpio@10015200 {
	296	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	297	reg = <0x10015200 0x100>;
	298	interrupts = <8>;
	299	gpio-controller;
	300	#gpio-cells = <2>;
	301	interrupt-controller;
	302	#interrupt-cells = <2>;
	303	};
	304
	305	gpio4: gpio@10015300 {
	306	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	307	reg = <0x10015300 0x100>;
	308	interrupts = <8>;
	309	gpio-controller;
	310	#gpio-cells = <2>;
	311	interrupt-controller;
	312	#interrupt-cells = <2>;
	313	};
	314
	315	gpio5: gpio@10015400 {
	316	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	317	reg = <0x10015400 0x100>;
	318	interrupts = <8>;
	319	gpio-controller;
	320	#gpio-cells = <2>;
	321	interrupt-controller;
	322	#interrupt-cells = <2>;
	323	};
	324
	325	gpio6: gpio@10015500 {
	326	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	327	reg = <0x10015500 0x100>;
	328	interrupts = <8>;
	329	gpio-controller;
	330	#gpio-cells = <2>;
	331	interrupt-controller;
332	#interrupt-cells = <2>;
333	};
9f0749e3 SH	334	};
9f0749e3 SH	335
6e228e80 AS	336	audmux: audmux@10016000 {
	337	compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
	338	reg = <0x10016000 0x1000>;
	339	clocks = <&clks 0>;
	340	clock-names = "audmux";
1c04ab0f	341	status = "disabled";
6e228e80 AS	342	};
6e228e80 AS	343
9f0749e3 SH	344	cspi3: cspi@10017000 {
	345	#address-cells = <1>;
	346	#size-cells = <0>;
	347	compatible = "fsl,imx27-cspi";
	348	reg = <0x10017000 0x1000>;
	349	interrupts = <6>;
7c37b617	350	clocks = <&clks 51>, <&clks 60>;
c20736f1	351	clock-names = "ipg", "per";
9f0749e3 SH	352	status = "disabled";
	353	};
	354
ca26d041 SH	355	gpt4: timer@10019000 {
	356	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	357	reg = <0x10019000 0x1000>;
	358	interrupts = <4>;
b700c119 SH	359	clocks = <&clks 43>, <&clks 61>;
b700c119 SH	360	clock-names = "ipg", "per";
ca26d041 SH	361	};
	362
	363	gpt5: timer@1001a000 {
	364	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	365	reg = <0x1001a000 0x1000>;
	366	interrupts = <3>;
b700c119 SH	367	clocks = <&clks 42>, <&clks 61>;
b700c119 SH	368	clock-names = "ipg", "per";
ca26d041 SH	369	};
ca26d041 SH	370
0c456cfa	371	uart5: serial@1001b000 {
9f0749e3 SH	372	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	373	reg = <0x1001b000 0x1000>;
	374	interrupts = <49>;
c20736f1 FE	375	clocks = <&clks 77>, <&clks 61>;
c20736f1 FE	376	clock-names = "ipg", "per";
9f0749e3 SH	377	status = "disabled";
	378	};
	379
0c456cfa	380	uart6: serial@1001c000 {
9f0749e3 SH	381	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	382	reg = <0x1001c000 0x1000>;
	383	interrupts = <48>;
c20736f1 FE	384	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	385	clock-names = "ipg", "per";
9f0749e3 SH	386	status = "disabled";
	387	};
	388
	389	i2c2: i2c@1001d000 {
	390	#address-cells = <1>;
	391	#size-cells = <0>;
5bdfba29	392	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	393	reg = <0x1001d000 0x1000>;
9f0749e3 SH	394	interrupts = <1>;
c20736f1	395	clocks = <&clks 39>;
9f0749e3 SH	396	status = "disabled";
	397	};
	398
0e7b01aa AS	399	sdhci3: sdhci@1001e000 {
	400	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	401	reg = <0x1001e000 0x1000>;
	402	interrupts = <9>;
	403	clocks = <&clks 28>, <&clks 60>;
	404	clock-names = "ipg", "per";
	405	dmas = <&dma 36>;
	406	dma-names = "rx-tx";
	407	status = "disabled";
	408	};
	409
ca26d041 SH	410	gpt6: timer@1001f000 {
	411	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	412	reg = <0x1001f000 0x1000>;
	413	interrupts = <2>;
b700c119 SH	414	clocks = <&clks 41>, <&clks 61>;
b700c119 SH	415	clock-names = "ipg", "per";
ca26d041	416	};
3e24b05b FE	417	};
	418
	419	aipi@10020000 { /* AIPI2 */
	420	compatible = "fsl,aipi-bus", "simple-bus";
	421	#address-cells = <1>;
	422	#size-cells = <1>;
	423	reg = <0x10020000 0x20000>;
	424	ranges;
	425
5e57b241 MP	426	fb: fb@10021000 {
	427	compatible = "fsl,imx27-fb", "fsl,imx21-fb";
	428	interrupts = <61>;
	429	reg = <0x10021000 0x1000>;
	430	clocks = <&clks 36>, <&clks 65>, <&clks 59>;
	431	clock-names = "ipg", "ahb", "per";
	432	status = "disabled";
	433	};
	434
93b331ce AS	435	coda: coda@10023000 {
	436	compatible = "fsl,imx27-vpu";
	437	reg = <0x10023000 0x0200>;
	438	interrupts = <53>;
	439	clocks = <&clks 57>, <&clks 66>;
	440	clock-names = "per", "ahb";
	441	iram = <&iram>;
	442	};
	443
a2e502c2 AS	444	usbotg: usb@10024000 {
	445	compatible = "fsl,imx27-usb";
	446	reg = <0x10024000 0x200>;
	447	interrupts = <56>;
b67b1944	448	clocks = <&clks 75>;
a2e502c2	449	fsl,usbmisc = <&usbmisc 0>;
a2e502c2 AS	450	status = "disabled";
	451	};
	452
	453	usbh1: usb@10024200 {
	454	compatible = "fsl,imx27-usb";
	455	reg = <0x10024200 0x200>;
	456	interrupts = <54>;
b67b1944	457	clocks = <&clks 75>;
a2e502c2 AS	458	fsl,usbmisc = <&usbmisc 1>;
	459	status = "disabled";
	460	};
	461
	462	usbh2: usb@10024400 {
	463	compatible = "fsl,imx27-usb";
	464	reg = <0x10024400 0x200>;
	465	interrupts = <55>;
b67b1944	466	clocks = <&clks 75>;
a2e502c2	467	fsl,usbmisc = <&usbmisc 2>;
a2e502c2 AS	468	status = "disabled";
	469	};
	470
	471	usbmisc: usbmisc@10024600 {
	472	#index-cells = <1>;
	473	compatible = "fsl,imx27-usbmisc";
	474	reg = <0x10024600 0x200>;
	475	clocks = <&clks 62>;
	476	};
	477
e4b6a056 AS	478	sahara2: sahara@10025000 {
	479	compatible = "fsl,imx27-sahara";
	480	reg = <0x10025000 0x1000>;
	481	interrupts = <59>;
	482	clocks = <&clks 32>, <&clks 64>;
	483	clock-names = "ipg", "ahb";
	484	};
	485
93b331ce AS	486	clks: ccm@10027000{
	487	compatible = "fsl,imx27-ccm";
	488	reg = <0x10027000 0x1000>;
	489	#clock-cells = <1>;
	490	};
	491
d36afcd4 AS	492	iim: iim@10028000 {
	493	compatible = "fsl,imx27-iim";
	494	reg = <0x10028000 0x1000>;
	495	interrupts = <62>;
	496	clocks = <&clks 38>;
	497	};
	498
0c456cfa	499	fec: ethernet@1002b000 {
9f0749e3 SH	500	compatible = "fsl,imx27-fec";
	501	reg = <0x1002b000 0x4000>;
	502	interrupts = <50>;
c0b357c0 AS	503	clocks = <&clks 48>, <&clks 67>;
c0b357c0 AS	504	clock-names = "ipg", "ahb";
9f0749e3 SH	505	status = "disabled";
	506	};
	507	};
7b7d6727 SH	508
7b7d6727 SH	509	nfc: nand@d8000000 {
37787360 UKK	510	#address-cells = <1>;
37787360 UKK	511	#size-cells = <1>;
37787360 UKK	512	compatible = "fsl,imx27-nand";
	513	reg = <0xd8000000 0x1000>;
	514	interrupts = <29>;
c20736f1	515	clocks = <&clks 54>;
37787360 UKK	516	status = "disabled";
37787360 UKK	517	};
ff1450f6	518
0912f594 AS	519	weim: weim@d8002000 {
	520	#address-cells = <2>;
	521	#size-cells = <1>;
	522	compatible = "fsl,imx27-weim";
	523	reg = <0xd8002000 0x1000>;
	524	clocks = <&clks 0>;
	525	ranges = <
	526	0 0 0xc0000000 0x08000000
	527	1 0 0xc8000000 0x08000000
	528	2 0 0xd0000000 0x02000000
	529	3 0 0xd2000000 0x02000000
	530	4 0 0xd4000000 0x02000000
	531	5 0 0xd6000000 0x02000000
	532	>;
	533	status = "disabled";
	534	};
	535
ff1450f6 AS	536	iram: iram@ffff4c00 {
	537	compatible = "mmio-sram";
	538	reg = <0xffff4c00 0xb400>;
	539	};
9f0749e3 SH	540	};
9f0749e3 SH	541	};