[deliverable/linux.git] / arch / arm / boot / dts / imx27.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		spi0 = &cspi1;
		spi1 = &cspi2;
		spi2 = &cspi3;
	};

	avic: avic-interrupt-controller@e0000000 {
		compatible = "fsl,imx27-avic", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10040000 0x1000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc26m {
			compatible = "fsl,imx-osc26m", "fixed-clock";
			clock-frequency = <26000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&avic>;
		ranges;

		aipi@10000000 { /* AIPI1 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10000000 0x20000>;
			ranges;

			dma: dma@10001000 {
				compatible = "fsl,imx27-dma";
				reg = <0x10001000 0x1000>;
				interrupts = <32>;
				clocks = <&clks 50>, <&clks 70>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
				#dma-channels = <16>;
			};

			wdog: wdog@10002000 {
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
				reg = <0x10002000 0x1000>;
				interrupts = <27>;
				clocks = <&clks 0>;
			};

			gpt1: timer@10003000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10003000 0x1000>;
				interrupts = <26>;
				clocks = <&clks 46>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@10004000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10004000 0x1000>;
				interrupts = <25>;
				clocks = <&clks 45>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt3: timer@10005000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10005000 0x1000>;
				interrupts = <24>;
				clocks = <&clks 44>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			pwm0: pwm@10006000 {
				compatible = "fsl,imx27-pwm";
				reg = <0x10006000 0x1000>;
				interrupts = <23>;
				clocks = <&clks 34>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			uart1: serial@1000a000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000a000 0x1000>;
				interrupts = <20>;
				clocks = <&clks 81>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@1000b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000b000 0x1000>;
				interrupts = <19>;
				clocks = <&clks 80>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@1000c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000c000 0x1000>;
				interrupts = <18>;
				clocks = <&clks 79>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@1000d000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000d000 0x1000>;
				interrupts = <17>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi1: cspi@1000e000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000e000 0x1000>;
				interrupts = <16>;
				clocks = <&clks 53>, <&clks 53>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi2: cspi@1000f000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000f000 0x1000>;
				interrupts = <15>;
				clocks = <&clks 52>, <&clks 52>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c1: i2c@10012000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x10012000 0x1000>;
				interrupts = <12>;
				clocks = <&clks 40>;
				status = "disabled";
			};

			gpio1: gpio@10015000 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015000 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@10015100 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015100 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@10015200 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015200 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@10015300 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015300 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@10015400 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015400 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@10015500 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015500 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			cspi3: cspi@10017000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x10017000 0x1000>;
				interrupts = <6>;
				clocks = <&clks 51>, <&clks 51>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@10019000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10019000 0x1000>;
				interrupts = <4>;
				clocks = <&clks 43>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt5: timer@1001a000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001a000 0x1000>;
				interrupts = <3>;
				clocks = <&clks 42>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			uart5: serial@1001b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001b000 0x1000>;
				interrupts = <49>;
				clocks = <&clks 77>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@1001c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001c000 0x1000>;
				interrupts = <48>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@1001d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x1001d000 0x1000>;
				interrupts = <1>;
				clocks = <&clks 39>;
				status = "disabled";
			};

			gpt6: timer@1001f000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001f000 0x1000>;
				interrupts = <2>;
				clocks = <&clks 41>, <&clks 61>;
				clock-names = "ipg", "per";
			};
		};

		aipi@10020000 { /* AIPI2 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10020000 0x20000>;
			ranges;

			fec: ethernet@1002b000 {
				compatible = "fsl,imx27-fec";
				reg = <0x1002b000 0x4000>;
				interrupts = <50>;
				clocks = <&clks 48>, <&clks 67>, <&clks 0>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};

			clks: ccm@10027000{
				compatible = "fsl,imx27-ccm";
				reg = <0x10027000 0x1000>;
				#clock-cells = <1>;
			};
		};


		nfc: nand@d8000000 {
			#address-cells = <1>;
			#size-cells = <1>;

			compatible = "fsl,imx27-nand";
			reg = <0xd8000000 0x1000>;
			interrupts = <29>;
			clocks = <&clks 54>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
9f0749e3 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
36dffd8f	12	#include "skeleton.dtsi"
9f0749e3 SH	13
	14	/ {
	15	aliases {
	16	serial0 = &uart1;
	17	serial1 = &uart2;
	18	serial2 = &uart3;
	19	serial3 = &uart4;
	20	serial4 = &uart5;
	21	serial5 = &uart6;
5230f8fe SG	22	gpio0 = &gpio1;
	23	gpio1 = &gpio2;
	24	gpio2 = &gpio3;
	25	gpio3 = &gpio4;
	26	gpio4 = &gpio5;
	27	gpio5 = &gpio6;
a5a641a1 AS	28	spi0 = &cspi1;
	29	spi1 = &cspi2;
	30	spi2 = &cspi3;
9f0749e3 SH	31	};
	32
	33	avic: avic-interrupt-controller@e0000000 {
	34	compatible = "fsl,imx27-avic", "fsl,avic";
	35	interrupt-controller;
	36	#interrupt-cells = <1>;
	37	reg = <0x10040000 0x1000>;
	38	};
	39
	40	clocks {
	41	#address-cells = <1>;
	42	#size-cells = <0>;
	43
	44	osc26m {
	45	compatible = "fsl,imx-osc26m", "fixed-clock";
	46	clock-frequency = <26000000>;
	47	};
	48	};
	49
	50	soc {
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53	compatible = "simple-bus";
	54	interrupt-parent = <&avic>;
	55	ranges;
	56
	57	aipi@10000000 { /* AIPI1 */
	58	compatible = "fsl,aipi-bus", "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
3e24b05b	61	reg = <0x10000000 0x20000>;
9f0749e3 SH	62	ranges;
9f0749e3 SH	63
b858c34f AS	64	dma: dma@10001000 {
	65	compatible = "fsl,imx27-dma";
	66	reg = <0x10001000 0x1000>;
	67	interrupts = <32>;
	68	clocks = <&clks 50>, <&clks 70>;
	69	clock-names = "ipg", "ahb";
	70	#dma-cells = <1>;
	71	#dma-channels = <16>;
	72	};
	73
7b7d6727	74	wdog: wdog@10002000 {
9f0749e3	75	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
ca26d041	76	reg = <0x10002000 0x1000>;
9f0749e3	77	interrupts = <27>;
c20736f1	78	clocks = <&clks 0>;
9f0749e3 SH	79	};
9f0749e3 SH	80
ca26d041 SH	81	gpt1: timer@10003000 {
	82	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	83	reg = <0x10003000 0x1000>;
	84	interrupts = <26>;
b700c119 SH	85	clocks = <&clks 46>, <&clks 61>;
b700c119 SH	86	clock-names = "ipg", "per";
ca26d041 SH	87	};
	88
	89	gpt2: timer@10004000 {
	90	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	91	reg = <0x10004000 0x1000>;
	92	interrupts = <25>;
b700c119 SH	93	clocks = <&clks 45>, <&clks 61>;
b700c119 SH	94	clock-names = "ipg", "per";
ca26d041 SH	95	};
	96
	97	gpt3: timer@10005000 {
	98	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	99	reg = <0x10005000 0x1000>;
	100	interrupts = <24>;
b700c119 SH	101	clocks = <&clks 44>, <&clks 61>;
b700c119 SH	102	clock-names = "ipg", "per";
ca26d041 SH	103	};
ca26d041 SH	104
08f4881a GGM	105	pwm0: pwm@10006000 {
	106	compatible = "fsl,imx27-pwm";
	107	reg = <0x10006000 0x1000>;
	108	interrupts = <23>;
	109	clocks = <&clks 34>, <&clks 61>;
	110	clock-names = "ipg", "per";
	111	};
	112
0c456cfa	113	uart1: serial@1000a000 {
9f0749e3 SH	114	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	115	reg = <0x1000a000 0x1000>;
	116	interrupts = <20>;
c20736f1 FE	117	clocks = <&clks 81>, <&clks 61>;
c20736f1 FE	118	clock-names = "ipg", "per";
9f0749e3 SH	119	status = "disabled";
	120	};
	121
0c456cfa	122	uart2: serial@1000b000 {
9f0749e3 SH	123	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	124	reg = <0x1000b000 0x1000>;
	125	interrupts = <19>;
c20736f1 FE	126	clocks = <&clks 80>, <&clks 61>;
c20736f1 FE	127	clock-names = "ipg", "per";
9f0749e3 SH	128	status = "disabled";
	129	};
	130
0c456cfa	131	uart3: serial@1000c000 {
9f0749e3 SH	132	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	133	reg = <0x1000c000 0x1000>;
	134	interrupts = <18>;
c20736f1 FE	135	clocks = <&clks 79>, <&clks 61>;
c20736f1 FE	136	clock-names = "ipg", "per";
9f0749e3 SH	137	status = "disabled";
	138	};
	139
0c456cfa	140	uart4: serial@1000d000 {
9f0749e3 SH	141	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	142	reg = <0x1000d000 0x1000>;
	143	interrupts = <17>;
c20736f1 FE	144	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	145	clock-names = "ipg", "per";
9f0749e3 SH	146	status = "disabled";
	147	};
	148
	149	cspi1: cspi@1000e000 {
	150	#address-cells = <1>;
	151	#size-cells = <0>;
	152	compatible = "fsl,imx27-cspi";
	153	reg = <0x1000e000 0x1000>;
	154	interrupts = <16>;
37523dc5	155	clocks = <&clks 53>, <&clks 53>;
c20736f1	156	clock-names = "ipg", "per";
9f0749e3 SH	157	status = "disabled";
	158	};
	159
	160	cspi2: cspi@1000f000 {
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163	compatible = "fsl,imx27-cspi";
	164	reg = <0x1000f000 0x1000>;
	165	interrupts = <15>;
37523dc5	166	clocks = <&clks 52>, <&clks 52>;
c20736f1	167	clock-names = "ipg", "per";
9f0749e3 SH	168	status = "disabled";
	169	};
	170
	171	i2c1: i2c@10012000 {
	172	#address-cells = <1>;
	173	#size-cells = <0>;
5bdfba29	174	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	175	reg = <0x10012000 0x1000>;
9f0749e3 SH	176	interrupts = <12>;
c20736f1	177	clocks = <&clks 40>;
9f0749e3 SH	178	status = "disabled";
	179	};
	180
	181	gpio1: gpio@10015000 {
	182	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	183	reg = <0x10015000 0x100>;
	184	interrupts = <8>;
	185	gpio-controller;
	186	#gpio-cells = <2>;
	187	interrupt-controller;
88cde8b7	188	#interrupt-cells = <2>;
9f0749e3 SH	189	};
	190
	191	gpio2: gpio@10015100 {
	192	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	193	reg = <0x10015100 0x100>;
	194	interrupts = <8>;
	195	gpio-controller;
	196	#gpio-cells = <2>;
	197	interrupt-controller;
88cde8b7	198	#interrupt-cells = <2>;
9f0749e3 SH	199	};
	200
	201	gpio3: gpio@10015200 {
	202	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	203	reg = <0x10015200 0x100>;
	204	interrupts = <8>;
	205	gpio-controller;
	206	#gpio-cells = <2>;
	207	interrupt-controller;
88cde8b7	208	#interrupt-cells = <2>;
9f0749e3 SH	209	};
	210
	211	gpio4: gpio@10015300 {
	212	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	213	reg = <0x10015300 0x100>;
	214	interrupts = <8>;
	215	gpio-controller;
	216	#gpio-cells = <2>;
	217	interrupt-controller;
88cde8b7	218	#interrupt-cells = <2>;
9f0749e3 SH	219	};
	220
	221	gpio5: gpio@10015400 {
	222	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	223	reg = <0x10015400 0x100>;
	224	interrupts = <8>;
	225	gpio-controller;
	226	#gpio-cells = <2>;
	227	interrupt-controller;
88cde8b7	228	#interrupt-cells = <2>;
9f0749e3 SH	229	};
	230
	231	gpio6: gpio@10015500 {
	232	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	233	reg = <0x10015500 0x100>;
	234	interrupts = <8>;
	235	gpio-controller;
	236	#gpio-cells = <2>;
	237	interrupt-controller;
88cde8b7	238	#interrupt-cells = <2>;
9f0749e3 SH	239	};
	240
	241	cspi3: cspi@10017000 {
	242	#address-cells = <1>;
	243	#size-cells = <0>;
	244	compatible = "fsl,imx27-cspi";
	245	reg = <0x10017000 0x1000>;
	246	interrupts = <6>;
37523dc5	247	clocks = <&clks 51>, <&clks 51>;
c20736f1	248	clock-names = "ipg", "per";
9f0749e3 SH	249	status = "disabled";
	250	};
	251
ca26d041 SH	252	gpt4: timer@10019000 {
	253	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	254	reg = <0x10019000 0x1000>;
	255	interrupts = <4>;
b700c119 SH	256	clocks = <&clks 43>, <&clks 61>;
b700c119 SH	257	clock-names = "ipg", "per";
ca26d041 SH	258	};
	259
	260	gpt5: timer@1001a000 {
	261	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	262	reg = <0x1001a000 0x1000>;
	263	interrupts = <3>;
b700c119 SH	264	clocks = <&clks 42>, <&clks 61>;
b700c119 SH	265	clock-names = "ipg", "per";
ca26d041 SH	266	};
ca26d041 SH	267
0c456cfa	268	uart5: serial@1001b000 {
9f0749e3 SH	269	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	270	reg = <0x1001b000 0x1000>;
	271	interrupts = <49>;
c20736f1 FE	272	clocks = <&clks 77>, <&clks 61>;
c20736f1 FE	273	clock-names = "ipg", "per";
9f0749e3 SH	274	status = "disabled";
	275	};
	276
0c456cfa	277	uart6: serial@1001c000 {
9f0749e3 SH	278	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	279	reg = <0x1001c000 0x1000>;
	280	interrupts = <48>;
c20736f1 FE	281	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	282	clock-names = "ipg", "per";
9f0749e3 SH	283	status = "disabled";
	284	};
	285
	286	i2c2: i2c@1001d000 {
	287	#address-cells = <1>;
	288	#size-cells = <0>;
5bdfba29	289	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	290	reg = <0x1001d000 0x1000>;
9f0749e3 SH	291	interrupts = <1>;
c20736f1	292	clocks = <&clks 39>;
9f0749e3 SH	293	status = "disabled";
	294	};
	295
ca26d041 SH	296	gpt6: timer@1001f000 {
	297	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	298	reg = <0x1001f000 0x1000>;
	299	interrupts = <2>;
b700c119 SH	300	clocks = <&clks 41>, <&clks 61>;
b700c119 SH	301	clock-names = "ipg", "per";
ca26d041	302	};
3e24b05b FE	303	};
	304
	305	aipi@10020000 { /* AIPI2 */
	306	compatible = "fsl,aipi-bus", "simple-bus";
	307	#address-cells = <1>;
	308	#size-cells = <1>;
	309	reg = <0x10020000 0x20000>;
	310	ranges;
	311
0c456cfa	312	fec: ethernet@1002b000 {
9f0749e3 SH	313	compatible = "fsl,imx27-fec";
	314	reg = <0x1002b000 0x4000>;
	315	interrupts = <50>;
c20736f1 FE	316	clocks = <&clks 48>, <&clks 67>, <&clks 0>;
c20736f1 FE	317	clock-names = "ipg", "ahb", "ptp";
9f0749e3 SH	318	status = "disabled";
9f0749e3 SH	319	};
c20736f1 FE	320
	321	clks: ccm@10027000{
	322	compatible = "fsl,imx27-ccm";
	323	reg = <0x10027000 0x1000>;
	324	#clock-cells = <1>;
	325	};
9f0749e3	326	};
7b7d6727	327
c20736f1	328
7b7d6727	329	nfc: nand@d8000000 {
37787360 UKK	330	#address-cells = <1>;
	331	#size-cells = <1>;
	332
	333	compatible = "fsl,imx27-nand";
	334	reg = <0xd8000000 0x1000>;
	335	interrupts = <29>;
c20736f1	336	clocks = <&clks 54>;
37787360 UKK	337	status = "disabled";
37787360 UKK	338	};
9f0749e3 SH	339	};
9f0749e3 SH	340	};