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ARM: mx28: add auart3 2 pins pinmux to imx28.dtsi
[deliverable/linux.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
ce4c6f9b
SG		 17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
530f1d41
SG		 23 saif0 = &saif0;
24 saif1 = &saif1;
80d969e4
FE		 25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
8c41d573
MV		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 };
33
bc3a59c1
DA		 34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
46
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
53
54 icoll: interrupt-controller@80000000 {
83a84efc 55 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
60
61 hsadc@80002000 {
0f06cde7 62 reg = <0x80002000 0x2000>;
bc3a59c1 63 interrupts = <13 87>;
f30fb03d
SG		 64 dmas = <&dma_apbh 12>;
65 dma-names = "rx";
bc3a59c1
DA		 66 status = "disabled";
67 };
68
f30fb03d 69 dma_apbh: dma-apbh@80004000 {
84f3570a 70 compatible = "fsl,imx28-dma-apbh";
0f06cde7 71 reg = <0x80004000 0x2000>;
f30fb03d
SG		 72 interrupts = <82 83 84 85
73 88 88 88 88
74 88 88 88 88
75 87 86 0 0>;
76 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
77 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
78 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
79 "hsadc", "lcdif", "empty", "empty";
80 #dma-cells = <1>;
81 dma-channels = <16>;
b598b9f3 82 clocks = <&clks 25>;
bc3a59c1
DA		 83 };
84
85 perfmon@80006000 {
0f06cde7 86 reg = <0x80006000 0x800>;
bc3a59c1
DA		 87 interrupts = <27>;
88 status = "disabled";
89 };
90
7a8e5149
HS		 91 gpmi-nand@8000c000 {
92 compatible = "fsl,imx28-gpmi-nand";
93 #address-cells = <1>;
94 #size-cells = <1>;
0f06cde7 95 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149
HS		 96 reg-names = "gpmi-nand", "bch";
97 interrupts = <88>, <41>;
98 interrupt-names = "gpmi-dma", "bch";
b598b9f3 99 clocks = <&clks 50>;
b6442559 100 clock-names = "gpmi_io";
f30fb03d
SG		 101 dmas = <&dma_apbh 4>;
102 dma-names = "rx-tx";
7a8e5149 103 fsl,gpmi-dma-channel = <4>;
bc3a59c1
DA		 104 status = "disabled";
105 };
106
107 ssp0: ssp@80010000 {
41bf5706
MR		 108 #address-cells = <1>;
109 #size-cells = <0>;
0f06cde7 110 reg = <0x80010000 0x2000>;
bc3a59c1 111 interrupts = <96 82>;
b598b9f3 112 clocks = <&clks 46>;
f30fb03d
SG		 113 dmas = <&dma_apbh 0>;
114 dma-names = "rx-tx";
35d23047 115 fsl,ssp-dma-channel = <0>;
bc3a59c1
DA		 116 status = "disabled";
117 };
118
119 ssp1: ssp@80012000 {
41bf5706
MR		 120 #address-cells = <1>;
121 #size-cells = <0>;
0f06cde7 122 reg = <0x80012000 0x2000>;
bc3a59c1 123 interrupts = <97 83>;
b598b9f3 124 clocks = <&clks 47>;
f30fb03d
SG		 125 dmas = <&dma_apbh 1>;
126 dma-names = "rx-tx";
35d23047 127 fsl,ssp-dma-channel = <1>;
bc3a59c1
DA		 128 status = "disabled";
129 };
130
131 ssp2: ssp@80014000 {
41bf5706
MR		 132 #address-cells = <1>;
133 #size-cells = <0>;
0f06cde7 134 reg = <0x80014000 0x2000>;
bc3a59c1 135 interrupts = <98 84>;
b598b9f3 136 clocks = <&clks 48>;
f30fb03d
SG		 137 dmas = <&dma_apbh 2>;
138 dma-names = "rx-tx";
35d23047 139 fsl,ssp-dma-channel = <2>;
bc3a59c1
DA		 140 status = "disabled";
141 };
142
143 ssp3: ssp@80016000 {
41bf5706
MR		 144 #address-cells = <1>;
145 #size-cells = <0>;
0f06cde7 146 reg = <0x80016000 0x2000>;
bc3a59c1 147 interrupts = <99 85>;
b598b9f3 148 clocks = <&clks 49>;
f30fb03d
SG		 149 dmas = <&dma_apbh 3>;
150 dma-names = "rx-tx";
35d23047 151 fsl,ssp-dma-channel = <3>;
bc3a59c1
DA		 152 status = "disabled";
153 };
154
155 pinctrl@80018000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
ce4c6f9b 158 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 159 reg = <0x80018000 0x2000>;
bc3a59c1 160
ce4c6f9b
SG		 161 gpio0: gpio@0 {
162 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
163 interrupts = <127>;
164 gpio-controller;
165 #gpio-cells = <2>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 };
169
170 gpio1: gpio@1 {
171 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
172 interrupts = <126>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 };
178
179 gpio2: gpio@2 {
180 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
181 interrupts = <125>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
187
188 gpio3: gpio@3 {
189 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
190 interrupts = <124>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio4: gpio@4 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
199 interrupts = <123>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
bc3a59c1
DA		 206 duart_pins_a: duart@0 {
207 reg = <0>;
f14da767
SG		 208 fsl,pinmux-ids = <
209 0x3102 /* MX28_PAD_PWM0__DUART_RX */
210 0x3112 /* MX28_PAD_PWM1__DUART_TX */
211 >;
bc3a59c1
DA		 212 fsl,drive-strength = <0>;
213 fsl,voltage = <1>;
214 fsl,pull-up = <0>;
215 };
216
8385e7c1
MR		 217 duart_pins_b: duart@1 {
218 reg = <1>;
f14da767
SG		 219 fsl,pinmux-ids = <
220 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
221 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
222 >;
8385e7c1
MR		 223 fsl,drive-strength = <0>;
224 fsl,voltage = <1>;
225 fsl,pull-up = <0>;
226 };
227
e1a4d18f
SG		 228 duart_4pins_a: duart-4pins@0 {
229 reg = <0>;
230 fsl,pinmux-ids = <
231 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
232 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
233 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
234 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
235 >;
236 fsl,drive-strength = <0>;
237 fsl,voltage = <1>;
238 fsl,pull-up = <0>;
239 };
240
7a8e5149
HS		 241 gpmi_pins_a: gpmi-nand@0 {
242 reg = <0>;
f14da767
SG		 243 fsl,pinmux-ids = <
244 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
245 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
246 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
247 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
248 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
249 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
250 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
251 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
252 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
f14da767 253 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
f14da767
SG		 254 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
255 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
256 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
257 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
258 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
259 >;
7a8e5149
HS		 260 fsl,drive-strength = <0>;
261 fsl,voltage = <1>;
262 fsl,pull-up = <0>;
263 };
264
265 gpmi_status_cfg: gpmi-status-cfg {
f14da767
SG		 266 fsl,pinmux-ids = <
267 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
268 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
269 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
270 >;
7a8e5149
HS		 271 fsl,drive-strength = <2>;
272 };
273
80d969e4
FE		 274 auart0_pins_a: auart0@0 {
275 reg = <0>;
f14da767
SG		 276 fsl,pinmux-ids = <
277 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
278 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
279 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
280 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
281 >;
80d969e4 282 fsl,drive-strength = <0>;
8fa62e11
MV		 283 fsl,voltage = <1>;
284 fsl,pull-up = <0>;
285 };
286
287 auart0_2pins_a: auart0-2pins@0 {
288 reg = <0>;
289 fsl,pinmux-ids = <
290 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
291 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
292 >;
293 fsl,drive-strength = <0>;
80d969e4
FE		 294 fsl,voltage = <1>;
295 fsl,pull-up = <0>;
296 };
297
e1a4d18f
SG		 298 auart1_pins_a: auart1@0 {
299 reg = <0>;
300 fsl,pinmux-ids = <
301 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
302 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
303 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
304 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
305 >;
306 fsl,drive-strength = <0>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <0>;
309 };
310
3143bbb4
SG		 311 auart1_2pins_a: auart1-2pins@0 {
312 reg = <0>;
313 fsl,pinmux-ids = <
314 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
315 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
316 >;
317 fsl,drive-strength = <0>;
318 fsl,voltage = <1>;
319 fsl,pull-up = <0>;
320 };
321
322 auart2_2pins_a: auart2-2pins@0 {
323 reg = <0>;
324 fsl,pinmux-ids = <
325 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
326 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
327 >;
328 fsl,drive-strength = <0>;
329 fsl,voltage = <1>;
330 fsl,pull-up = <0>;
331 };
332
f8040cf5
EB		 333 auart2_2pins_b: auart2-2pins@1 {
334 reg = <1>;
335 fsl,pinmux-ids = <
336 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
337 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
338 >;
339 fsl,drive-strength = <0>;
340 fsl,voltage = <1>;
341 fsl,pull-up = <0>;
342 };
343
80d969e4
FE		 344 auart3_pins_a: auart3@0 {
345 reg = <0>;
f14da767
SG		 346 fsl,pinmux-ids = <
347 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
348 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
349 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
350 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
351 >;
80d969e4
FE		 352 fsl,drive-strength = <0>;
353 fsl,voltage = <1>;
354 fsl,pull-up = <0>;
355 };
356
3143bbb4
SG		 357 auart3_2pins_a: auart3-2pins@0 {
358 reg = <0>;
359 fsl,pinmux-ids = <
360 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
361 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
362 >;
363 fsl,drive-strength = <0>;
364 fsl,voltage = <1>;
365 fsl,pull-up = <0>;
366 };
367
4812e746
EB		 368 auart3_2pins_b: auart3-2pins@1 {
369 reg = <1>;
370 fsl,pinmux-ids = <
371 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
372 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
373 >;
374 fsl,drive-strength = <0>;
375 fsl,voltage = <1>;
376 fsl,pull-up = <0>;
377 };
378
bc3a59c1
DA		 379 mac0_pins_a: mac0@0 {
380 reg = <0>;
f14da767
SG		 381 fsl,pinmux-ids = <
382 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
383 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
384 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
385 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
386 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
387 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
388 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
389 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
390 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
391 >;
bc3a59c1
DA		 392 fsl,drive-strength = <1>;
393 fsl,voltage = <1>;
394 fsl,pull-up = <1>;
395 };
396
397 mac1_pins_a: mac1@0 {
398 reg = <0>;
f14da767
SG		 399 fsl,pinmux-ids = <
400 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
401 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
402 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
403 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
404 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
405 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
406 >;
bc3a59c1
DA		 407 fsl,drive-strength = <1>;
408 fsl,voltage = <1>;
409 fsl,pull-up = <1>;
410 };
35d23047
SG		 411
412 mmc0_8bit_pins_a: mmc0-8bit@0 {
413 reg = <0>;
f14da767
SG		 414 fsl,pinmux-ids = <
415 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
416 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
417 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
418 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
419 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
420 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
421 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
422 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
423 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
424 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
425 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
426 >;
35d23047
SG		 427 fsl,drive-strength = <1>;
428 fsl,voltage = <1>;
429 fsl,pull-up = <1>;
430 };
431
8385e7c1
MR		 432 mmc0_4bit_pins_a: mmc0-4bit@0 {
433 reg = <0>;
f14da767
SG		 434 fsl,pinmux-ids = <
435 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
436 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
437 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
438 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
439 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
440 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
441 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
442 >;
8385e7c1
MR		 443 fsl,drive-strength = <1>;
444 fsl,voltage = <1>;
445 fsl,pull-up = <1>;
446 };
447
35d23047 448 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767
SG		 449 fsl,pinmux-ids = <
450 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
451 >;
35d23047
SG		 452 fsl,pull-up = <0>;
453 };
454
455 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767
SG		 456 fsl,pinmux-ids = <
457 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
458 >;
35d23047
SG		 459 fsl,drive-strength = <2>;
460 fsl,pull-up = <0>;
461 };
2a96e391
SG		 462
463 i2c0_pins_a: i2c0@0 {
464 reg = <0>;
f14da767
SG		 465 fsl,pinmux-ids = <
466 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
467 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
468 >;
2a96e391
SG		 469 fsl,drive-strength = <1>;
470 fsl,voltage = <1>;
471 fsl,pull-up = <1>;
472 };
530f1d41 473
5c697ea2
MR		 474 i2c0_pins_b: i2c0@1 {
475 reg = <1>;
476 fsl,pinmux-ids = <
477 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
478 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
479 >;
480 fsl,drive-strength = <1>;
481 fsl,voltage = <1>;
482 fsl,pull-up = <1>;
483 };
484
de7e934f
MR		 485 i2c1_pins_a: i2c1@0 {
486 reg = <0>;
487 fsl,pinmux-ids = <
488 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
489 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
490 >;
491 fsl,drive-strength = <1>;
492 fsl,voltage = <1>;
493 fsl,pull-up = <1>;
494 };
495
530f1d41
SG		 496 saif0_pins_a: saif0@0 {
497 reg = <0>;
f14da767
SG		 498 fsl,pinmux-ids = <
499 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
500 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
501 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
502 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
503 >;
530f1d41
SG		 504 fsl,drive-strength = <2>;
505 fsl,voltage = <1>;
506 fsl,pull-up = <1>;
507 };
508
509 saif1_pins_a: saif1@0 {
510 reg = <0>;
f14da767
SG		 511 fsl,pinmux-ids = <
512 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
513 >;
530f1d41
SG		 514 fsl,drive-strength = <2>;
515 fsl,voltage = <1>;
516 fsl,pull-up = <1>;
517 };
52f7176b 518
e1a4d18f
SG		 519 pwm0_pins_a: pwm0@0 {
520 reg = <0>;
521 fsl,pinmux-ids = <
522 0x3100 /* MX28_PAD_PWM0__PWM_0 */
523 >;
524 fsl,drive-strength = <0>;
525 fsl,voltage = <1>;
526 fsl,pull-up = <0>;
527 };
528
52f7176b
SG		 529 pwm2_pins_a: pwm2@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
532 0x3120 /* MX28_PAD_PWM2__PWM_2 */
533 >;
534 fsl,drive-strength = <0>;
535 fsl,voltage = <1>;
536 fsl,pull-up = <0>;
537 };
a915ee42 538
2bde51cb
JB		 539 pwm3_pins_a: pwm3@0 {
540 reg = <0>;
541 fsl,pinmux-ids = <
542 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
543 >;
544 fsl,drive-strength = <0>;
545 fsl,voltage = <1>;
546 fsl,pull-up = <0>;
547 };
548
d248620c
MR		 549 pwm3_pins_b: pwm3@1 {
550 reg = <1>;
551 fsl,pinmux-ids = <
552 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
553 >;
554 fsl,drive-strength = <0>;
555 fsl,voltage = <1>;
556 fsl,pull-up = <0>;
557 };
558
2f44211f
MR		 559 pwm4_pins_a: pwm4@0 {
560 reg = <0>;
561 fsl,pinmux-ids = <
562 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
563 >;
564 fsl,drive-strength = <0>;
565 fsl,voltage = <1>;
566 fsl,pull-up = <0>;
567 };
568
a915ee42
SG		 569 lcdif_24bit_pins_a: lcdif-24bit@0 {
570 reg = <0>;
571 fsl,pinmux-ids = <
572 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
573 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
574 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
575 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
576 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
577 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
578 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
579 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
580 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
581 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
582 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
583 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
584 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
585 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
586 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
587 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
588 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
589 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
590 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
591 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
592 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
593 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
594 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
595 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
a915ee42
SG		 596 >;
597 fsl,drive-strength = <0>;
598 fsl,voltage = <1>;
599 fsl,pull-up = <0>;
600 };
6ca44acf 601
4ced2a40
GGM		 602 lcdif_16bit_pins_a: lcdif-16bit@0 {
603 reg = <0>;
604 fsl,pinmux-ids = <
605 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
606 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
607 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
608 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
609 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
610 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
611 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
612 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
613 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
614 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
615 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
616 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
617 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
618 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
619 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
620 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
621 >;
622 fsl,drive-strength = <0>;
623 fsl,voltage = <1>;
624 fsl,pull-up = <0>;
625 };
626
6ca44acf
SG		 627 can0_pins_a: can0@0 {
628 reg = <0>;
629 fsl,pinmux-ids = <
630 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
631 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
632 >;
633 fsl,drive-strength = <0>;
634 fsl,voltage = <1>;
635 fsl,pull-up = <0>;
636 };
637
638 can1_pins_a: can1@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
641 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
642 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
643 >;
644 fsl,drive-strength = <0>;
645 fsl,voltage = <1>;
646 fsl,pull-up = <0>;
647 };
7f122213
MV		 648
649 spi2_pins_a: spi2@0 {
650 reg = <0>;
651 fsl,pinmux-ids = <
652 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
653 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
654 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
655 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
656 >;
657 fsl,drive-strength = <1>;
658 fsl,voltage = <1>;
659 fsl,pull-up = <1>;
660 };
bb2f1261
MV		 661
662 usbphy0_pins_a: usbphy0@0 {
663 reg = <0>;
664 fsl,pinmux-ids = <
665 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
666 >;
667 fsl,drive-strength = <2>;
668 fsl,voltage = <1>;
669 fsl,pull-up = <0>;
670 };
671
672 usbphy0_pins_b: usbphy0@1 {
673 reg = <1>;
674 fsl,pinmux-ids = <
675 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
676 >;
677 fsl,drive-strength = <2>;
678 fsl,voltage = <1>;
679 fsl,pull-up = <0>;
680 };
681
682 usbphy1_pins_a: usbphy1@0 {
683 reg = <0>;
684 fsl,pinmux-ids = <
685 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
686 >;
687 fsl,drive-strength = <2>;
688 fsl,voltage = <1>;
689 fsl,pull-up = <0>;
690 };
bc3a59c1
DA		 691 };
692
693 digctl@8001c000 {
115581cf 694 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 695 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 696 interrupts = <89>;
697 status = "disabled";
698 };
699
700 etm@80022000 {
0f06cde7 701 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 702 status = "disabled";
703 };
704
f30fb03d 705 dma_apbx: dma-apbx@80024000 {
84f3570a 706 compatible = "fsl,imx28-dma-apbx";
0f06cde7 707 reg = <0x80024000 0x2000>;
f30fb03d
SG		 708 interrupts = <78 79 66 0
709 80 81 68 69
710 70 71 72 73
711 74 75 76 77>;
712 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
713 "saif0", "saif1", "i2c0", "i2c1",
714 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
715 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
716 #dma-cells = <1>;
717 dma-channels = <16>;
b598b9f3 718 clocks = <&clks 26>;
bc3a59c1
DA		 719 };
720
721 dcp@80028000 {
0f06cde7 722 reg = <0x80028000 0x2000>;
bc3a59c1
DA		 723 interrupts = <52 53 54>;
724 status = "disabled";
725 };
726
727 pxp@8002a000 {
0f06cde7 728 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 729 interrupts = <39>;
730 status = "disabled";
731 };
732
733 ocotp@8002c000 {
69d75a02 734 compatible = "fsl,ocotp";
0f06cde7 735 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 736 status = "disabled";
737 };
738
739 axi-ahb@8002e000 {
0f06cde7 740 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 741 status = "disabled";
742 };
743
744 lcdif@80030000 {
a915ee42 745 compatible = "fsl,imx28-lcdif";
0f06cde7 746 reg = <0x80030000 0x2000>;
bc3a59c1 747 interrupts = <38 86>;
b598b9f3 748 clocks = <&clks 55>;
f30fb03d
SG		 749 dmas = <&dma_apbh 13>;
750 dma-names = "rx";
bc3a59c1
DA		 751 status = "disabled";
752 };
753
754 can0: can@80032000 {
6ca44acf 755 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 756 reg = <0x80032000 0x2000>;
bc3a59c1 757 interrupts = <8>;
b598b9f3
SG		 758 clocks = <&clks 58>, <&clks 58>;
759 clock-names = "ipg", "per";
bc3a59c1
DA		 760 status = "disabled";
761 };
762
763 can1: can@80034000 {
6ca44acf 764 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 765 reg = <0x80034000 0x2000>;
bc3a59c1 766 interrupts = <9>;
b598b9f3
SG		 767 clocks = <&clks 59>, <&clks 59>;
768 clock-names = "ipg", "per";
bc3a59c1
DA		 769 status = "disabled";
770 };
771
772 simdbg@8003c000 {
0f06cde7 773 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 774 status = "disabled";
775 };
776
777 simgpmisel@8003c200 {
0f06cde7 778 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 779 status = "disabled";
780 };
781
782 simsspsel@8003c300 {
0f06cde7 783 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 784 status = "disabled";
785 };
786
787 simmemsel@8003c400 {
0f06cde7 788 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 789 status = "disabled";
790 };
791
792 gpiomon@8003c500 {
0f06cde7 793 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 794 status = "disabled";
795 };
796
797 simenet@8003c700 {
0f06cde7 798 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 799 status = "disabled";
800 };
801
802 armjtag@8003c800 {
0f06cde7 803 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 804 status = "disabled";
805 };
806 };
807
808 apbx@80040000 {
809 compatible = "simple-bus";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 reg = <0x80040000 0x40000>;
813 ranges;
814
b598b9f3 815 clks: clkctrl@80040000 {
8f7cf881 816 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 817 reg = <0x80040000 0x2000>;
b598b9f3 818 #clock-cells = <1>;
bc3a59c1
DA		 819 };
820
821 saif0: saif@80042000 {
530f1d41 822 compatible = "fsl,imx28-saif";
0f06cde7 823 reg = <0x80042000 0x2000>;
bc3a59c1 824 interrupts = <59 80>;
b598b9f3 825 clocks = <&clks 53>;
f30fb03d
SG		 826 dmas = <&dma_apbx 4>;
827 dma-names = "rx-tx";
530f1d41 828 fsl,saif-dma-channel = <4>;
bc3a59c1
DA		 829 status = "disabled";
830 };
831
832 power@80044000 {
0f06cde7 833 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 834 status = "disabled";
835 };
836
837 saif1: saif@80046000 {
530f1d41 838 compatible = "fsl,imx28-saif";
0f06cde7 839 reg = <0x80046000 0x2000>;
bc3a59c1 840 interrupts = <58 81>;
b598b9f3 841 clocks = <&clks 54>;
f30fb03d
SG		 842 dmas = <&dma_apbx 5>;
843 dma-names = "rx-tx";
530f1d41 844 fsl,saif-dma-channel = <5>;
bc3a59c1
DA		 845 status = "disabled";
846 };
847
848 lradc@80050000 {
aef35104 849 compatible = "fsl,imx28-lradc";
0f06cde7 850 reg = <0x80050000 0x2000>;
aef35104
MV		 851 interrupts = <10 14 15 16 17 18 19
852 20 21 22 23 24 25>;
bc3a59c1
DA		 853 status = "disabled";
854 };
855
856 spdif@80054000 {
0f06cde7 857 reg = <0x80054000 0x2000>;
bc3a59c1 858 interrupts = <45 66>;
f30fb03d
SG		 859 dmas = <&dma_apbx 2>;
860 dma-names = "tx";
bc3a59c1
DA		 861 status = "disabled";
862 };
863
864 rtc@80056000 {
f98c990c 865 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 866 reg = <0x80056000 0x2000>;
f98c990c 867 interrupts = <29>;
bc3a59c1
DA		 868 };
869
870 i2c0: i2c@80058000 {
2a96e391
SG		 871 #address-cells = <1>;
872 #size-cells = <0>;
873 compatible = "fsl,imx28-i2c";
0f06cde7 874 reg = <0x80058000 0x2000>;
bc3a59c1 875 interrupts = <111 68>;
cd4f2d4a 876 clock-frequency = <100000>;
f30fb03d
SG		 877 dmas = <&dma_apbx 6>;
878 dma-names = "rx-tx";
62885f59 879 fsl,i2c-dma-channel = <6>;
bc3a59c1
DA		 880 status = "disabled";
881 };
882
883 i2c1: i2c@8005a000 {
2a96e391
SG		 884 #address-cells = <1>;
885 #size-cells = <0>;
886 compatible = "fsl,imx28-i2c";
0f06cde7 887 reg = <0x8005a000 0x2000>;
bc3a59c1 888 interrupts = <110 69>;
cd4f2d4a 889 clock-frequency = <100000>;
f30fb03d
SG		 890 dmas = <&dma_apbx 7>;
891 dma-names = "rx-tx";
62885f59 892 fsl,i2c-dma-channel = <7>;
bc3a59c1
DA		 893 status = "disabled";
894 };
895
52f7176b
SG		 896 pwm: pwm@80064000 {
897 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 898 reg = <0x80064000 0x2000>;
b598b9f3 899 clocks = <&clks 44>;
52f7176b
SG		 900 #pwm-cells = <2>;
901 fsl,pwm-number = <8>;
bc3a59c1
DA		 902 status = "disabled";
903 };
904
905 timrot@80068000 {
eeca6e60 906 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 907 reg = <0x80068000 0x2000>;
eeca6e60 908 interrupts = <48 49 50 51>;
2efb9504 909 clocks = <&clks 26>;
bc3a59c1
DA		 910 };
911
912 auart0: serial@8006a000 {
80d969e4 913 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 914 reg = <0x8006a000 0x2000>;
915 interrupts = <112 70 71>;
f30fb03d
SG		 916 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
917 dma-names = "rx", "tx";
77a807dc 918 fsl,auart-dma-channel = <8 9>;
b598b9f3 919 clocks = <&clks 45>;
bc3a59c1
DA		 920 status = "disabled";
921 };
922
923 auart1: serial@8006c000 {
80d969e4 924 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 925 reg = <0x8006c000 0x2000>;
926 interrupts = <113 72 73>;
f30fb03d
SG		 927 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
928 dma-names = "rx", "tx";
b598b9f3 929 clocks = <&clks 45>;
bc3a59c1
DA		 930 status = "disabled";
931 };
932
933 auart2: serial@8006e000 {
80d969e4 934 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 935 reg = <0x8006e000 0x2000>;
936 interrupts = <114 74 75>;
f30fb03d
SG		 937 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
938 dma-names = "rx", "tx";
b598b9f3 939 clocks = <&clks 45>;
bc3a59c1
DA		 940 status = "disabled";
941 };
942
943 auart3: serial@80070000 {
80d969e4 944 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 945 reg = <0x80070000 0x2000>;
946 interrupts = <115 76 77>;
f30fb03d
SG		 947 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
948 dma-names = "rx", "tx";
b598b9f3 949 clocks = <&clks 45>;
bc3a59c1
DA		 950 status = "disabled";
951 };
952
953 auart4: serial@80072000 {
80d969e4 954 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 955 reg = <0x80072000 0x2000>;
956 interrupts = <116 78 79>;
f30fb03d
SG		 957 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
958 dma-names = "rx", "tx";
b598b9f3 959 clocks = <&clks 45>;
bc3a59c1
DA		 960 status = "disabled";
961 };
962
963 duart: serial@80074000 {
964 compatible = "arm,pl011", "arm,primecell";
965 reg = <0x80074000 0x1000>;
966 interrupts = <47>;
b598b9f3
SG		 967 clocks = <&clks 45>, <&clks 26>;
968 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 969 status = "disabled";
970 };
971
972 usbphy0: usbphy@8007c000 {
5da01270 973 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 974 reg = <0x8007c000 0x2000>;
b598b9f3 975 clocks = <&clks 62>;
bc3a59c1
DA		 976 status = "disabled";
977 };
978
979 usbphy1: usbphy@8007e000 {
5da01270 980 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 981 reg = <0x8007e000 0x2000>;
b598b9f3 982 clocks = <&clks 63>;
bc3a59c1
DA		 983 status = "disabled";
984 };
985 };
986 };
987
988 ahb@80080000 {
989 compatible = "simple-bus";
990 #address-cells = <1>;
991 #size-cells = <1>;
992 reg = <0x80080000 0x80000>;
993 ranges;
994
5da01270
RZ		 995 usb0: usb@80080000 {
996 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 997 reg = <0x80080000 0x10000>;
5da01270 998 interrupts = <93>;
b598b9f3 999 clocks = <&clks 60>;
5da01270 1000 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1001 status = "disabled";
1002 };
1003
5da01270
RZ		 1004 usb1: usb@80090000 {
1005 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1006 reg = <0x80090000 0x10000>;
5da01270 1007 interrupts = <92>;
b598b9f3 1008 clocks = <&clks 61>;
5da01270 1009 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 1010 status = "disabled";
1011 };
1012
1013 dflpt@800c0000 {
1014 reg = <0x800c0000 0x10000>;
1015 status = "disabled";
1016 };
1017
1018 mac0: ethernet@800f0000 {
1019 compatible = "fsl,imx28-fec";
1020 reg = <0x800f0000 0x4000>;
1021 interrupts = <101>;
f231a9fe
WS		 1022 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1023 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1024 status = "disabled";
1025 };
1026
1027 mac1: ethernet@800f4000 {
1028 compatible = "fsl,imx28-fec";
1029 reg = <0x800f4000 0x4000>;
1030 interrupts = <102>;
b598b9f3
SG		 1031 clocks = <&clks 57>, <&clks 57>;
1032 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1033 status = "disabled";
1034 };
1035
1036 switch@800f8000 {
1037 reg = <0x800f8000 0x8000>;
1038 status = "disabled";
1039 };
1040
1041 };
1042};
Linux kernel - Deliverables
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