projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d2a37b3d DGC |
1 | /* |
| 2 | * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | |
| 3 | * | |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | */ | |
| 11 | ||
| 36dffd8f | 12 | #include "skeleton.dtsi" |
| d2a37b3d DGC |
13 | |
| 14 | / { | |
| 15 | aliases { | |
| 16 | serial0 = &uart1; | |
| 17 | serial1 = &uart2; | |
| 18 | serial2 = &uart3; | |
| 19 | serial3 = &uart4; | |
| 20 | serial4 = &uart5; | |
| 21 | }; | |
| 22 | ||
| 070bd7e4 FE |
23 | cpus { |
| 24 | #address-cells = <0>; | |
| 25 | #size-cells = <0>; | |
| 26 | ||
| 27 | cpu { | |
| bc6cde35 | 28 | compatible = "arm,arm1136jf-s"; |
| 070bd7e4 FE |
29 | device_type = "cpu"; |
| 30 | }; | |
| 31 | }; | |
| 32 | ||
| d2a37b3d DGC |
33 | avic: avic-interrupt-controller@60000000 { |
| 34 | compatible = "fsl,imx31-avic", "fsl,avic"; | |
| 35 | interrupt-controller; | |
| 36 | #interrupt-cells = <1>; | |
| 37 | reg = <0x60000000 0x100000>; | |
| 38 | }; | |
| 39 | ||
| 40 | soc { | |
| 41 | #address-cells = <1>; | |
| 42 | #size-cells = <1>; | |
| 43 | compatible = "simple-bus"; | |
| 44 | interrupt-parent = <&avic>; | |
| 45 | ranges; | |
| 46 | ||
| 47 | aips@43f00000 { /* AIPS1 */ | |
| 48 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 49 | #address-cells = <1>; | |
| 50 | #size-cells = <1>; | |
| 51 | reg = <0x43f00000 0x100000>; | |
| 52 | ranges; | |
| 53 | ||
| 54 | uart1: serial@43f90000 { | |
| 55 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
| 56 | reg = <0x43f90000 0x4000>; | |
| 57 | interrupts = <45>; | |
| ef0e4a60 FE |
58 | clocks = <&clks 10>, <&clks 30>; |
| 59 | clock-names = "ipg", "per"; | |
| d2a37b3d DGC |
60 | status = "disabled"; |
| 61 | }; | |
| 62 | ||
| 63 | uart2: serial@43f94000 { | |
| 64 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
| 65 | reg = <0x43f94000 0x4000>; | |
| 66 | interrupts = <32>; | |
| ef0e4a60 FE |
67 | clocks = <&clks 10>, <&clks 31>; |
| 68 | clock-names = "ipg", "per"; | |
| d2a37b3d DGC |
69 | status = "disabled"; |
| 70 | }; | |
| 71 | ||
| d8c8c70c AK |
72 | kpp: kpp@43fa8000 { |
| 73 | compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; | |
| 74 | reg = <0x43fa8000 0x4000>; | |
| 75 | interrupts = <24>; | |
| 76 | clocks = <&clks 46>; | |
| 77 | status = "disabled"; | |
| 78 | }; | |
| 79 | ||
| d2a37b3d DGC |
80 | uart4: serial@43fb0000 { |
| 81 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
| 82 | reg = <0x43fb0000 0x4000>; | |
| ef0e4a60 FE |
83 | clocks = <&clks 10>, <&clks 49>; |
| 84 | clock-names = "ipg", "per"; | |
| d2a37b3d DGC |
85 | interrupts = <46>; |
| 86 | status = "disabled"; | |
| 87 | }; | |
| 88 | ||
| 89 | uart5: serial@43fb4000 { | |
| 90 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
| 91 | reg = <0x43fb4000 0x4000>; | |
| 92 | interrupts = <47>; | |
| ef0e4a60 FE |
93 | clocks = <&clks 10>, <&clks 50>; |
| 94 | clock-names = "ipg", "per"; | |
| d2a37b3d DGC |
95 | status = "disabled"; |
| 96 | }; | |
| 97 | }; | |
| 98 | ||
| 99 | spba@50000000 { | |
| 100 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 101 | #address-cells = <1>; | |
| 102 | #size-cells = <1>; | |
| 103 | reg = <0x50000000 0x100000>; | |
| 104 | ranges; | |
| 105 | ||
| 106 | uart3: serial@5000c000 { | |
| 107 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
| 108 | reg = <0x5000c000 0x4000>; | |
| 109 | interrupts = <18>; | |
| ef0e4a60 FE |
110 | clocks = <&clks 10>, <&clks 48>; |
| 111 | clock-names = "ipg", "per"; | |
| d2a37b3d DGC |
112 | status = "disabled"; |
| 113 | }; | |
| ef0e4a60 | 114 | |
| 9c5d5909 SH |
115 | iim: iim@5001c000 { |
| 116 | compatible = "fsl,imx31-iim", "fsl,imx27-iim"; | |
| 117 | reg = <0x5001c000 0x1000>; | |
| 118 | interrupts = <19>; | |
| 119 | clocks = <&clks 25>; | |
| 120 | }; | |
| 121 | ||
| ef0e4a60 FE |
122 | clks: ccm@53f80000{ |
| 123 | compatible = "fsl,imx31-ccm"; | |
| 124 | reg = <0x53f80000 0x4000>; | |
| 125 | interrupts = <0 31 0x04 0 53 0x04>; | |
| 126 | #clock-cells = <1>; | |
| 127 | }; | |
| d2a37b3d | 128 | }; |
| a44eed9a SH |
129 | |
| 130 | aips@53f00000 { /* AIPS2 */ | |
| 131 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 132 | #address-cells = <1>; | |
| 133 | #size-cells = <1>; | |
| 134 | reg = <0x53f00000 0x100000>; | |
| 135 | ranges; | |
| 136 | ||
| 137 | gpt: timer@53f90000 { | |
| 138 | compatible = "fsl,imx31-gpt"; | |
| 139 | reg = <0x53f90000 0x4000>; | |
| 140 | interrupts = <29>; | |
| 141 | clocks = <&clks 10>, <&clks 22>; | |
| 142 | clock-names = "ipg", "per"; | |
| 143 | }; | |
| 144 | }; | |
| d2a37b3d DGC |
145 | }; |
| 146 | }; |