Commit | Line | Data |
---|---|---|
c605cbf5 GU |
1 | /* |
2 | * Copyright 2013 Greg Ungerer <gerg@uclinux.org> | |
3 | * Copyright 2011 Freescale Semiconductor, Inc. | |
4 | * Copyright 2011 Linaro Ltd. | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /dts-v1/; | |
15 | #include "imx50.dtsi" | |
16 | ||
17 | / { | |
18 | model = "Freescale i.MX50 Evaluation Kit"; | |
19 | compatible = "fsl,imx50-evk", "fsl,imx50"; | |
20 | ||
21 | memory { | |
22 | reg = <0x70000000 0x80000000>; | |
23 | }; | |
24 | }; | |
25 | ||
26 | &cspi { | |
27 | pinctrl-names = "default"; | |
28 | pinctrl-0 = <&pinctrl_cspi>; | |
29 | fsl,spi-num-chipselects = <2>; | |
30 | cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; | |
31 | status = "okay"; | |
32 | ||
33 | flash: m25p32@1 { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <1>; | |
36 | compatible = "m25p32", "m25p80"; | |
37 | spi-max-frequency = <25000000>; | |
38 | reg = <1>; | |
39 | ||
40 | partition@0 { | |
41 | label = "bootloader"; | |
42 | reg = <0x0 0x100000>; | |
43 | read-only; | |
44 | }; | |
45 | ||
46 | partition@100000 { | |
47 | label = "kernel"; | |
48 | reg = <0x100000 0x300000>; | |
49 | }; | |
50 | }; | |
51 | }; | |
52 | ||
53 | &fec { | |
54 | pinctrl-names = "default"; | |
55 | pinctrl-0 = <&pinctrl_fec>; | |
56 | phy-mode = "rmii"; | |
57 | phy-reset-gpios = <&gpio4 12 0>; | |
58 | status = "okay"; | |
59 | }; | |
60 | ||
61 | &iomuxc { | |
62 | imx50-evk { | |
63 | pinctrl_cspi: cspigrp { | |
64 | fsl,pins = < | |
65 | MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 | |
66 | MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 | |
67 | MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 | |
68 | MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 | |
69 | MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 | |
70 | >; | |
71 | }; | |
72 | ||
73 | pinctrl_fec: fecgrp { | |
74 | fsl,pins = < | |
75 | MX50_PAD_SSI_RXFS__FEC_MDC 0x80 | |
76 | MX50_PAD_SSI_RXC__FEC_MDIO 0x80 | |
77 | MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 | |
78 | MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 | |
79 | MX50_PAD_DISP_D2__FEC_RX_DV 0x80 | |
80 | MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 | |
81 | MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 | |
82 | MX50_PAD_DISP_D5__FEC_TX_EN 0x80 | |
83 | MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 | |
84 | MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 | |
85 | >; | |
86 | }; | |
87 | ||
88 | pinctrl_uart1: uart1grp { | |
89 | fsl,pins = < | |
90 | MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 | |
91 | MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 | |
92 | MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 | |
93 | MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 | |
94 | >; | |
95 | }; | |
96 | }; | |
97 | }; | |
98 | ||
99 | &uart1 { | |
100 | pinctrl-names = "default"; | |
101 | pinctrl-0 = <&pinctrl_uart1>; | |
102 | status = "okay"; | |
103 | }; | |
104 | ||
105 | &usbh1 { | |
106 | status = "okay"; | |
107 | }; | |
108 | ||
109 | &usbh2 { | |
110 | status = "okay"; | |
111 | }; | |
112 | ||
113 | &usbh3 { | |
114 | status = "okay"; | |
115 | }; | |
116 | ||
117 | &usbotg { | |
118 | status = "okay"; | |
119 | }; |