[deliverable/linux.git] / arch / arm / boot / dts / imx50.dtsi

/*
 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>

/ {
	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
					         <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx50-ssi",
							"fsl,imx51-ssi",
							"fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
				         <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
				         <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
				         <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
				         <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
				         <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx50-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx50-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
				         <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
				         <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
				         <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
							"fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				dmas = <&sdma 28 0 0>,
				       <&sdma 29 0 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
64972acd GU	1	/*
	2	* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include "imx50-pinfunc.h"
6650d6db	16	#include <dt-bindings/clock/imx5-clock.h>
64972acd GU	17
	18	/ {
	19	aliases {
22970070	20	ethernet0 = &fec;
64972acd GU	21	gpio0 = &gpio1;
	22	gpio1 = &gpio2;
	23	gpio2 = &gpio3;
	24	gpio3 = &gpio4;
	25	gpio4 = &gpio5;
	26	gpio5 = &gpio6;
	27	serial0 = &uart1;
	28	serial1 = &uart2;
	29	serial2 = &uart3;
	30	serial3 = &uart4;
	31	serial4 = &uart5;
	32	};
	33
	34	cpus {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37	cpu@0 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a8";
	40	reg = <0x0>;
	41	};
	42	};
	43
	44	tzic: tz-interrupt-controller@0fffc000 {
	45	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	46	interrupt-controller;
	47	#interrupt-cells = <1>;
	48	reg = <0x0fffc000 0x4000>;
	49	};
	50
	51	clocks {
	52	#address-cells = <1>;
	53	#size-cells = <0>;
	54
	55	ckil {
	56	compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043	57	#clock-cells = <0>;
64972acd GU	58	clock-frequency = <32768>;
	59	};
	60
	61	ckih1 {
	62	compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043	63	#clock-cells = <0>;
64972acd GU	64	clock-frequency = <22579200>;
	65	};
	66
	67	ckih2 {
	68	compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043	69	#clock-cells = <0>;
64972acd GU	70	clock-frequency = <0>;
	71	};
	72
	73	osc {
	74	compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043	75	#clock-cells = <0>;
64972acd GU	76	clock-frequency = <24000000>;
	77	};
	78	};
	79
	80	soc {
	81	#address-cells = <1>;
	82	#size-cells = <1>;
	83	compatible = "simple-bus";
	84	interrupt-parent = <&tzic>;
	85	ranges;
	86
	87	aips@50000000 { /* AIPS1 */
	88	compatible = "fsl,aips-bus", "simple-bus";
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	reg = <0x50000000 0x10000000>;
	92	ranges;
	93
	94	spba@50000000 {
	95	compatible = "fsl,spba-bus", "simple-bus";
	96	#address-cells = <1>;
	97	#size-cells = <1>;
	98	reg = <0x50000000 0x40000>;
	99	ranges;
	100
	101	esdhc1: esdhc@50004000 {
	102	compatible = "fsl,imx50-esdhc";
	103	reg = <0x50004000 0x4000>;
	104	interrupts = <1>;
6650d6db LS	105	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	106	<&clks IMX5_CLK_DUMMY>,
	107	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
64972acd GU	108	clock-names = "ipg", "ahb", "per";
	109	bus-width = <4>;
	110	status = "disabled";
	111	};
	112
	113	esdhc2: esdhc@50008000 {
	114	compatible = "fsl,imx50-esdhc";
	115	reg = <0x50008000 0x4000>;
	116	interrupts = <2>;
6650d6db LS	117	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	118	<&clks IMX5_CLK_DUMMY>,
	119	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
64972acd GU	120	clock-names = "ipg", "ahb", "per";
	121	bus-width = <4>;
	122	status = "disabled";
	123	};
	124
	125	uart3: serial@5000c000 {
	126	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	127	reg = <0x5000c000 0x4000>;
	128	interrupts = <33>;
6650d6db LS	129	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
6650d6db LS	130	<&clks IMX5_CLK_UART3_PER_GATE>;
64972acd GU	131	clock-names = "ipg", "per";
	132	status = "disabled";
	133	};
	134
	135	ecspi1: ecspi@50010000 {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	139	reg = <0x50010000 0x4000>;
	140	interrupts = <36>;
6650d6db LS	141	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
6650d6db LS	142	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
64972acd GU	143	clock-names = "ipg", "per";
	144	status = "disabled";
	145	};
	146
	147	ssi2: ssi@50014000 {
6ff7f51e	148	#sound-dai-cells = <0>;
28f93d0b MP	149	compatible = "fsl,imx50-ssi",
	150	"fsl,imx51-ssi",
	151	"fsl,imx21-ssi";
64972acd GU	152	reg = <0x50014000 0x4000>;
64972acd GU	153	interrupts = <30>;
6650d6db	154	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
d9a9f38f MP	155	dmas = <&sdma 24 1 0>,
	156	<&sdma 25 1 0>;
	157	dma-names = "rx", "tx";
64972acd	158	fsl,fifo-depth = <15>;
64972acd GU	159	status = "disabled";
	160	};
	161
	162	esdhc3: esdhc@50020000 {
	163	compatible = "fsl,imx50-esdhc";
	164	reg = <0x50020000 0x4000>;
	165	interrupts = <3>;
6650d6db LS	166	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	167	<&clks IMX5_CLK_DUMMY>,
	168	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
64972acd GU	169	clock-names = "ipg", "ahb", "per";
	170	bus-width = <4>;
	171	status = "disabled";
	172	};
	173
	174	esdhc4: esdhc@50024000 {
	175	compatible = "fsl,imx50-esdhc";
	176	reg = <0x50024000 0x4000>;
	177	interrupts = <4>;
6650d6db LS	178	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	179	<&clks IMX5_CLK_DUMMY>,
	180	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
64972acd GU	181	clock-names = "ipg", "ahb", "per";
	182	bus-width = <4>;
	183	status = "disabled";
	184	};
	185	};
	186
	187	usbotg: usb@53f80000 {
	188	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	189	reg = <0x53f80000 0x0200>;
	190	interrupts = <18>;
6650d6db	191	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
64972acd GU	192	status = "disabled";
	193	};
	194
	195	usbh1: usb@53f80200 {
	196	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	197	reg = <0x53f80200 0x0200>;
	198	interrupts = <14>;
6650d6db	199	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
64972acd GU	200	status = "disabled";
	201	};
	202
	203	usbh2: usb@53f80400 {
	204	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	205	reg = <0x53f80400 0x0200>;
	206	interrupts = <16>;
6650d6db	207	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	208	status = "disabled";
	209	};
	210
	211	usbh3: usb@53f80600 {
	212	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	213	reg = <0x53f80600 0x0200>;
	214	interrupts = <17>;
6650d6db	215	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	216	status = "disabled";
	217	};
	218
	219	gpio1: gpio@53f84000 {
	220	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	221	reg = <0x53f84000 0x4000>;
	222	interrupts = <50 51>;
	223	gpio-controller;
	224	#gpio-cells = <2>;
	225	interrupt-controller;
	226	#interrupt-cells = <2>;
	227	};
	228
	229	gpio2: gpio@53f88000 {
	230	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	231	reg = <0x53f88000 0x4000>;
	232	interrupts = <52 53>;
	233	gpio-controller;
	234	#gpio-cells = <2>;
	235	interrupt-controller;
	236	#interrupt-cells = <2>;
	237	};
	238
	239	gpio3: gpio@53f8c000 {
	240	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	241	reg = <0x53f8c000 0x4000>;
	242	interrupts = <54 55>;
	243	gpio-controller;
	244	#gpio-cells = <2>;
	245	interrupt-controller;
	246	#interrupt-cells = <2>;
	247	};
	248
	249	gpio4: gpio@53f90000 {
	250	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	251	reg = <0x53f90000 0x4000>;
	252	interrupts = <56 57>;
	253	gpio-controller;
	254	#gpio-cells = <2>;
	255	interrupt-controller;
	256	#interrupt-cells = <2>;
	257	};
	258
	259	wdog1: wdog@53f98000 {
	260	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	261	reg = <0x53f98000 0x4000>;
	262	interrupts = <58>;
6650d6db	263	clocks = <&clks IMX5_CLK_DUMMY>;
64972acd GU	264	};
	265
	266	gpt: timer@53fa0000 {
	267	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	268	reg = <0x53fa0000 0x4000>;
	269	interrupts = <39>;
6650d6db LS	270	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
6650d6db LS	271	<&clks IMX5_CLK_GPT_HF_GATE>;
64972acd GU	272	clock-names = "ipg", "per";
	273	};
	274
	275	iomuxc: iomuxc@53fa8000 {
	276	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	277	reg = <0x53fa8000 0x4000>;
	278	};
	279
	280	gpr: iomuxc-gpr@53fa8000 {
	281	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	282	reg = <0x53fa8000 0xc>;
	283	};
	284
	285	pwm1: pwm@53fb4000 {
	286	#pwm-cells = <2>;
	287	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	288	reg = <0x53fb4000 0x4000>;
6650d6db LS	289	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
6650d6db LS	290	<&clks IMX5_CLK_PWM1_HF_GATE>;
64972acd GU	291	clock-names = "ipg", "per";
	292	interrupts = <61>;
	293	};
	294
	295	pwm2: pwm@53fb8000 {
	296	#pwm-cells = <2>;
	297	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	298	reg = <0x53fb8000 0x4000>;
6650d6db LS	299	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
6650d6db LS	300	<&clks IMX5_CLK_PWM2_HF_GATE>;
64972acd GU	301	clock-names = "ipg", "per";
	302	interrupts = <94>;
	303	};
	304
	305	uart1: serial@53fbc000 {
	306	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	307	reg = <0x53fbc000 0x4000>;
	308	interrupts = <31>;
6650d6db LS	309	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
6650d6db LS	310	<&clks IMX5_CLK_UART1_PER_GATE>;
64972acd GU	311	clock-names = "ipg", "per";
	312	status = "disabled";
	313	};
	314
	315	uart2: serial@53fc0000 {
	316	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	317	reg = <0x53fc0000 0x4000>;
	318	interrupts = <32>;
6650d6db LS	319	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
6650d6db LS	320	<&clks IMX5_CLK_UART2_PER_GATE>;
64972acd GU	321	clock-names = "ipg", "per";
	322	status = "disabled";
	323	};
	324
	325	src: src@53fd0000 {
	326	compatible = "fsl,imx50-src", "fsl,imx51-src";
	327	reg = <0x53fd0000 0x4000>;
	328	#reset-cells = <1>;
	329	};
	330
	331	clks: ccm@53fd4000{
	332	compatible = "fsl,imx50-ccm";
	333	reg = <0x53fd4000 0x4000>;
	334	interrupts = <0 71 0x04 0 72 0x04>;
	335	#clock-cells = <1>;
	336	};
	337
	338	gpio5: gpio@53fdc000 {
	339	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	340	reg = <0x53fdc000 0x4000>;
	341	interrupts = <103 104>;
	342	gpio-controller;
	343	#gpio-cells = <2>;
	344	interrupt-controller;
	345	#interrupt-cells = <2>;
	346	};
	347
	348	gpio6: gpio@53fe0000 {
	349	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	350	reg = <0x53fe0000 0x4000>;
	351	interrupts = <105 106>;
	352	gpio-controller;
	353	#gpio-cells = <2>;
	354	interrupt-controller;
	355	#interrupt-cells = <2>;
	356	};
	357
	358	i2c3: i2c@53fec000 {
	359	#address-cells = <1>;
	360	#size-cells = <0>;
	361	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	362	reg = <0x53fec000 0x4000>;
	363	interrupts = <64>;
6650d6db	364	clocks = <&clks IMX5_CLK_I2C3_GATE>;
64972acd GU	365	status = "disabled";
	366	};
	367
	368	uart4: serial@53ff0000 {
	369	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	370	reg = <0x53ff0000 0x4000>;
	371	interrupts = <13>;
6650d6db LS	372	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
6650d6db LS	373	<&clks IMX5_CLK_UART4_PER_GATE>;
64972acd GU	374	clock-names = "ipg", "per";
	375	status = "disabled";
	376	};
	377	};
	378
	379	aips@60000000 { /* AIPS2 */
	380	compatible = "fsl,aips-bus", "simple-bus";
	381	#address-cells = <1>;
	382	#size-cells = <1>;
	383	reg = <0x60000000 0x10000000>;
	384	ranges;
	385
	386	uart5: serial@63f90000 {
	387	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	388	reg = <0x63f90000 0x4000>;
	389	interrupts = <86>;
6650d6db LS	390	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
6650d6db LS	391	<&clks IMX5_CLK_UART5_PER_GATE>;
64972acd GU	392	clock-names = "ipg", "per";
	393	status = "disabled";
	394	};
	395
	396	owire: owire@63fa4000 {
	397	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	398	reg = <0x63fa4000 0x4000>;
6650d6db	399	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
64972acd GU	400	status = "disabled";
	401	};
	402
	403	ecspi2: ecspi@63fac000 {
	404	#address-cells = <1>;
	405	#size-cells = <0>;
	406	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	407	reg = <0x63fac000 0x4000>;
	408	interrupts = <37>;
6650d6db LS	409	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
6650d6db LS	410	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
64972acd GU	411	clock-names = "ipg", "per";
	412	status = "disabled";
	413	};
	414
	415	sdma: sdma@63fb0000 {
	416	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	417	reg = <0x63fb0000 0x4000>;
	418	interrupts = <6>;
6650d6db LS	419	clocks = <&clks IMX5_CLK_SDMA_GATE>,
6650d6db LS	420	<&clks IMX5_CLK_SDMA_GATE>;
64972acd GU	421	clock-names = "ipg", "ahb";
	422	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	423	};
	424
	425	cspi: cspi@63fc0000 {
	426	#address-cells = <1>;
	427	#size-cells = <0>;
	428	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	429	reg = <0x63fc0000 0x4000>;
	430	interrupts = <38>;
6650d6db LS	431	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
6650d6db LS	432	<&clks IMX5_CLK_CSPI_IPG_GATE>;
64972acd GU	433	clock-names = "ipg", "per";
	434	status = "disabled";
	435	};
	436
	437	i2c2: i2c@63fc4000 {
	438	#address-cells = <1>;
	439	#size-cells = <0>;
	440	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	441	reg = <0x63fc4000 0x4000>;
	442	interrupts = <63>;
6650d6db	443	clocks = <&clks IMX5_CLK_I2C2_GATE>;
64972acd GU	444	status = "disabled";
	445	};
	446
	447	i2c1: i2c@63fc8000 {
	448	#address-cells = <1>;
	449	#size-cells = <0>;
	450	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	451	reg = <0x63fc8000 0x4000>;
	452	interrupts = <62>;
6650d6db	453	clocks = <&clks IMX5_CLK_I2C1_GATE>;
64972acd GU	454	status = "disabled";
	455	};
	456
	457	ssi1: ssi@63fcc000 {
6ff7f51e	458	#sound-dai-cells = <0>;
28f93d0b MP	459	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
28f93d0b MP	460	"fsl,imx21-ssi";
64972acd GU	461	reg = <0x63fcc000 0x4000>;
64972acd GU	462	interrupts = <29>;
6650d6db	463	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
d9a9f38f MP	464	dmas = <&sdma 28 0 0>,
	465	<&sdma 29 0 0>;
	466	dma-names = "rx", "tx";
64972acd	467	fsl,fifo-depth = <15>;
64972acd GU	468	status = "disabled";
	469	};
	470
	471	audmux: audmux@63fd0000 {
	472	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	473	reg = <0x63fd0000 0x4000>;
	474	status = "disabled";
	475	};
	476
	477	fec: ethernet@63fec000 {
	478	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	479	reg = <0x63fec000 0x4000>;
	480	interrupts = <87>;
6650d6db LS	481	clocks = <&clks IMX5_CLK_FEC_GATE>,
	482	<&clks IMX5_CLK_FEC_GATE>,
	483	<&clks IMX5_CLK_FEC_GATE>;
64972acd GU	484	clock-names = "ipg", "ahb", "ptp";
	485	status = "disabled";
	486	};
	487	};
	488	};
	489	};