Commit | Line | Data |
---|---|---|
64972acd GU |
1 | /* |
2 | * Copyright 2013 Greg Ungerer <gerg@uclinux.org> | |
3 | * Copyright 2011 Freescale Semiconductor, Inc. | |
4 | * Copyright 2011 Linaro Ltd. | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | #include "skeleton.dtsi" | |
15 | #include "imx50-pinfunc.h" | |
6650d6db | 16 | #include <dt-bindings/clock/imx5-clock.h> |
64972acd GU |
17 | |
18 | / { | |
19 | aliases { | |
22970070 | 20 | ethernet0 = &fec; |
64972acd GU |
21 | gpio0 = &gpio1; |
22 | gpio1 = &gpio2; | |
23 | gpio2 = &gpio3; | |
24 | gpio3 = &gpio4; | |
25 | gpio4 = &gpio5; | |
26 | gpio5 = &gpio6; | |
27 | serial0 = &uart1; | |
28 | serial1 = &uart2; | |
29 | serial2 = &uart3; | |
30 | serial3 = &uart4; | |
31 | serial4 = &uart5; | |
32 | }; | |
33 | ||
34 | cpus { | |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | cpu@0 { | |
38 | device_type = "cpu"; | |
39 | compatible = "arm,cortex-a8"; | |
40 | reg = <0x0>; | |
41 | }; | |
42 | }; | |
43 | ||
44 | tzic: tz-interrupt-controller@0fffc000 { | |
45 | compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; | |
46 | interrupt-controller; | |
47 | #interrupt-cells = <1>; | |
48 | reg = <0x0fffc000 0x4000>; | |
49 | }; | |
50 | ||
51 | clocks { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | ||
55 | ckil { | |
56 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 57 | #clock-cells = <0>; |
64972acd GU |
58 | clock-frequency = <32768>; |
59 | }; | |
60 | ||
61 | ckih1 { | |
62 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 63 | #clock-cells = <0>; |
64972acd GU |
64 | clock-frequency = <22579200>; |
65 | }; | |
66 | ||
67 | ckih2 { | |
68 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
4b2b4043 | 69 | #clock-cells = <0>; |
64972acd GU |
70 | clock-frequency = <0>; |
71 | }; | |
72 | ||
73 | osc { | |
74 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 75 | #clock-cells = <0>; |
64972acd GU |
76 | clock-frequency = <24000000>; |
77 | }; | |
78 | }; | |
79 | ||
80 | soc { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | compatible = "simple-bus"; | |
84 | interrupt-parent = <&tzic>; | |
85 | ranges; | |
86 | ||
87 | aips@50000000 { /* AIPS1 */ | |
88 | compatible = "fsl,aips-bus", "simple-bus"; | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | reg = <0x50000000 0x10000000>; | |
92 | ranges; | |
93 | ||
94 | spba@50000000 { | |
95 | compatible = "fsl,spba-bus", "simple-bus"; | |
96 | #address-cells = <1>; | |
97 | #size-cells = <1>; | |
98 | reg = <0x50000000 0x40000>; | |
99 | ranges; | |
100 | ||
101 | esdhc1: esdhc@50004000 { | |
102 | compatible = "fsl,imx50-esdhc"; | |
103 | reg = <0x50004000 0x4000>; | |
104 | interrupts = <1>; | |
6650d6db LS |
105 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
106 | <&clks IMX5_CLK_DUMMY>, | |
107 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
64972acd GU |
108 | clock-names = "ipg", "ahb", "per"; |
109 | bus-width = <4>; | |
110 | status = "disabled"; | |
111 | }; | |
112 | ||
113 | esdhc2: esdhc@50008000 { | |
114 | compatible = "fsl,imx50-esdhc"; | |
115 | reg = <0x50008000 0x4000>; | |
116 | interrupts = <2>; | |
6650d6db LS |
117 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
118 | <&clks IMX5_CLK_DUMMY>, | |
119 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
64972acd GU |
120 | clock-names = "ipg", "ahb", "per"; |
121 | bus-width = <4>; | |
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | uart3: serial@5000c000 { | |
126 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | |
127 | reg = <0x5000c000 0x4000>; | |
128 | interrupts = <33>; | |
6650d6db LS |
129 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
130 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
64972acd GU |
131 | clock-names = "ipg", "per"; |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
135 | ecspi1: ecspi@50010000 { | |
136 | #address-cells = <1>; | |
137 | #size-cells = <0>; | |
138 | compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; | |
139 | reg = <0x50010000 0x4000>; | |
140 | interrupts = <36>; | |
6650d6db LS |
141 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
142 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
64972acd GU |
143 | clock-names = "ipg", "per"; |
144 | status = "disabled"; | |
145 | }; | |
146 | ||
147 | ssi2: ssi@50014000 { | |
6ff7f51e | 148 | #sound-dai-cells = <0>; |
28f93d0b MP |
149 | compatible = "fsl,imx50-ssi", |
150 | "fsl,imx51-ssi", | |
151 | "fsl,imx21-ssi"; | |
64972acd GU |
152 | reg = <0x50014000 0x4000>; |
153 | interrupts = <30>; | |
6650d6db | 154 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
d9a9f38f MP |
155 | dmas = <&sdma 24 1 0>, |
156 | <&sdma 25 1 0>; | |
157 | dma-names = "rx", "tx"; | |
64972acd | 158 | fsl,fifo-depth = <15>; |
64972acd GU |
159 | status = "disabled"; |
160 | }; | |
161 | ||
162 | esdhc3: esdhc@50020000 { | |
163 | compatible = "fsl,imx50-esdhc"; | |
164 | reg = <0x50020000 0x4000>; | |
165 | interrupts = <3>; | |
6650d6db LS |
166 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
167 | <&clks IMX5_CLK_DUMMY>, | |
168 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
64972acd GU |
169 | clock-names = "ipg", "ahb", "per"; |
170 | bus-width = <4>; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | esdhc4: esdhc@50024000 { | |
175 | compatible = "fsl,imx50-esdhc"; | |
176 | reg = <0x50024000 0x4000>; | |
177 | interrupts = <4>; | |
6650d6db LS |
178 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
179 | <&clks IMX5_CLK_DUMMY>, | |
180 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
64972acd GU |
181 | clock-names = "ipg", "ahb", "per"; |
182 | bus-width = <4>; | |
183 | status = "disabled"; | |
184 | }; | |
185 | }; | |
186 | ||
187 | usbotg: usb@53f80000 { | |
188 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | |
189 | reg = <0x53f80000 0x0200>; | |
190 | interrupts = <18>; | |
6650d6db | 191 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
64972acd GU |
192 | status = "disabled"; |
193 | }; | |
194 | ||
195 | usbh1: usb@53f80200 { | |
196 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | |
197 | reg = <0x53f80200 0x0200>; | |
198 | interrupts = <14>; | |
6650d6db | 199 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
3ec481ed | 200 | dr_mode = "host"; |
64972acd GU |
201 | status = "disabled"; |
202 | }; | |
203 | ||
204 | usbh2: usb@53f80400 { | |
205 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | |
206 | reg = <0x53f80400 0x0200>; | |
207 | interrupts = <16>; | |
6650d6db | 208 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
3ec481ed | 209 | dr_mode = "host"; |
64972acd GU |
210 | status = "disabled"; |
211 | }; | |
212 | ||
213 | usbh3: usb@53f80600 { | |
214 | compatible = "fsl,imx50-usb", "fsl,imx27-usb"; | |
215 | reg = <0x53f80600 0x0200>; | |
216 | interrupts = <17>; | |
6650d6db | 217 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
3ec481ed | 218 | dr_mode = "host"; |
64972acd GU |
219 | status = "disabled"; |
220 | }; | |
221 | ||
222 | gpio1: gpio@53f84000 { | |
223 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
224 | reg = <0x53f84000 0x4000>; | |
225 | interrupts = <50 51>; | |
226 | gpio-controller; | |
227 | #gpio-cells = <2>; | |
228 | interrupt-controller; | |
229 | #interrupt-cells = <2>; | |
230 | }; | |
231 | ||
232 | gpio2: gpio@53f88000 { | |
233 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
234 | reg = <0x53f88000 0x4000>; | |
235 | interrupts = <52 53>; | |
236 | gpio-controller; | |
237 | #gpio-cells = <2>; | |
238 | interrupt-controller; | |
239 | #interrupt-cells = <2>; | |
240 | }; | |
241 | ||
242 | gpio3: gpio@53f8c000 { | |
243 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
244 | reg = <0x53f8c000 0x4000>; | |
245 | interrupts = <54 55>; | |
246 | gpio-controller; | |
247 | #gpio-cells = <2>; | |
248 | interrupt-controller; | |
249 | #interrupt-cells = <2>; | |
250 | }; | |
251 | ||
252 | gpio4: gpio@53f90000 { | |
253 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
254 | reg = <0x53f90000 0x4000>; | |
255 | interrupts = <56 57>; | |
256 | gpio-controller; | |
257 | #gpio-cells = <2>; | |
258 | interrupt-controller; | |
259 | #interrupt-cells = <2>; | |
260 | }; | |
261 | ||
262 | wdog1: wdog@53f98000 { | |
263 | compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; | |
264 | reg = <0x53f98000 0x4000>; | |
265 | interrupts = <58>; | |
6650d6db | 266 | clocks = <&clks IMX5_CLK_DUMMY>; |
64972acd GU |
267 | }; |
268 | ||
269 | gpt: timer@53fa0000 { | |
270 | compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; | |
271 | reg = <0x53fa0000 0x4000>; | |
272 | interrupts = <39>; | |
6650d6db LS |
273 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
274 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
64972acd GU |
275 | clock-names = "ipg", "per"; |
276 | }; | |
277 | ||
278 | iomuxc: iomuxc@53fa8000 { | |
279 | compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; | |
280 | reg = <0x53fa8000 0x4000>; | |
281 | }; | |
282 | ||
283 | gpr: iomuxc-gpr@53fa8000 { | |
284 | compatible = "fsl,imx50-iomuxc-gpr", "syscon"; | |
285 | reg = <0x53fa8000 0xc>; | |
286 | }; | |
287 | ||
288 | pwm1: pwm@53fb4000 { | |
289 | #pwm-cells = <2>; | |
290 | compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; | |
291 | reg = <0x53fb4000 0x4000>; | |
6650d6db LS |
292 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
293 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
64972acd GU |
294 | clock-names = "ipg", "per"; |
295 | interrupts = <61>; | |
296 | }; | |
297 | ||
298 | pwm2: pwm@53fb8000 { | |
299 | #pwm-cells = <2>; | |
300 | compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; | |
301 | reg = <0x53fb8000 0x4000>; | |
6650d6db LS |
302 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
303 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
64972acd GU |
304 | clock-names = "ipg", "per"; |
305 | interrupts = <94>; | |
306 | }; | |
307 | ||
308 | uart1: serial@53fbc000 { | |
309 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | |
310 | reg = <0x53fbc000 0x4000>; | |
311 | interrupts = <31>; | |
6650d6db LS |
312 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
313 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
64972acd GU |
314 | clock-names = "ipg", "per"; |
315 | status = "disabled"; | |
316 | }; | |
317 | ||
318 | uart2: serial@53fc0000 { | |
319 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | |
320 | reg = <0x53fc0000 0x4000>; | |
321 | interrupts = <32>; | |
6650d6db LS |
322 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
323 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
64972acd GU |
324 | clock-names = "ipg", "per"; |
325 | status = "disabled"; | |
326 | }; | |
327 | ||
328 | src: src@53fd0000 { | |
329 | compatible = "fsl,imx50-src", "fsl,imx51-src"; | |
330 | reg = <0x53fd0000 0x4000>; | |
331 | #reset-cells = <1>; | |
332 | }; | |
333 | ||
334 | clks: ccm@53fd4000{ | |
335 | compatible = "fsl,imx50-ccm"; | |
336 | reg = <0x53fd4000 0x4000>; | |
337 | interrupts = <0 71 0x04 0 72 0x04>; | |
338 | #clock-cells = <1>; | |
339 | }; | |
340 | ||
341 | gpio5: gpio@53fdc000 { | |
342 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
343 | reg = <0x53fdc000 0x4000>; | |
344 | interrupts = <103 104>; | |
345 | gpio-controller; | |
346 | #gpio-cells = <2>; | |
347 | interrupt-controller; | |
348 | #interrupt-cells = <2>; | |
349 | }; | |
350 | ||
351 | gpio6: gpio@53fe0000 { | |
352 | compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; | |
353 | reg = <0x53fe0000 0x4000>; | |
354 | interrupts = <105 106>; | |
355 | gpio-controller; | |
356 | #gpio-cells = <2>; | |
357 | interrupt-controller; | |
358 | #interrupt-cells = <2>; | |
359 | }; | |
360 | ||
361 | i2c3: i2c@53fec000 { | |
362 | #address-cells = <1>; | |
363 | #size-cells = <0>; | |
364 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | |
365 | reg = <0x53fec000 0x4000>; | |
366 | interrupts = <64>; | |
6650d6db | 367 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
64972acd GU |
368 | status = "disabled"; |
369 | }; | |
370 | ||
371 | uart4: serial@53ff0000 { | |
372 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | |
373 | reg = <0x53ff0000 0x4000>; | |
374 | interrupts = <13>; | |
6650d6db LS |
375 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
376 | <&clks IMX5_CLK_UART4_PER_GATE>; | |
64972acd GU |
377 | clock-names = "ipg", "per"; |
378 | status = "disabled"; | |
379 | }; | |
380 | }; | |
381 | ||
382 | aips@60000000 { /* AIPS2 */ | |
383 | compatible = "fsl,aips-bus", "simple-bus"; | |
384 | #address-cells = <1>; | |
385 | #size-cells = <1>; | |
386 | reg = <0x60000000 0x10000000>; | |
387 | ranges; | |
388 | ||
389 | uart5: serial@63f90000 { | |
390 | compatible = "fsl,imx50-uart", "fsl,imx21-uart"; | |
391 | reg = <0x63f90000 0x4000>; | |
392 | interrupts = <86>; | |
6650d6db LS |
393 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
394 | <&clks IMX5_CLK_UART5_PER_GATE>; | |
64972acd GU |
395 | clock-names = "ipg", "per"; |
396 | status = "disabled"; | |
397 | }; | |
398 | ||
399 | owire: owire@63fa4000 { | |
400 | compatible = "fsl,imx50-owire", "fsl,imx21-owire"; | |
401 | reg = <0x63fa4000 0x4000>; | |
6650d6db | 402 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
64972acd GU |
403 | status = "disabled"; |
404 | }; | |
405 | ||
406 | ecspi2: ecspi@63fac000 { | |
407 | #address-cells = <1>; | |
408 | #size-cells = <0>; | |
409 | compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; | |
410 | reg = <0x63fac000 0x4000>; | |
411 | interrupts = <37>; | |
6650d6db LS |
412 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
413 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
64972acd GU |
414 | clock-names = "ipg", "per"; |
415 | status = "disabled"; | |
416 | }; | |
417 | ||
418 | sdma: sdma@63fb0000 { | |
419 | compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; | |
420 | reg = <0x63fb0000 0x4000>; | |
421 | interrupts = <6>; | |
6650d6db LS |
422 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
423 | <&clks IMX5_CLK_SDMA_GATE>; | |
64972acd GU |
424 | clock-names = "ipg", "ahb"; |
425 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; | |
426 | }; | |
427 | ||
428 | cspi: cspi@63fc0000 { | |
429 | #address-cells = <1>; | |
430 | #size-cells = <0>; | |
431 | compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; | |
432 | reg = <0x63fc0000 0x4000>; | |
433 | interrupts = <38>; | |
6650d6db LS |
434 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
435 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
64972acd GU |
436 | clock-names = "ipg", "per"; |
437 | status = "disabled"; | |
438 | }; | |
439 | ||
440 | i2c2: i2c@63fc4000 { | |
441 | #address-cells = <1>; | |
442 | #size-cells = <0>; | |
443 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | |
444 | reg = <0x63fc4000 0x4000>; | |
445 | interrupts = <63>; | |
6650d6db | 446 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
64972acd GU |
447 | status = "disabled"; |
448 | }; | |
449 | ||
450 | i2c1: i2c@63fc8000 { | |
451 | #address-cells = <1>; | |
452 | #size-cells = <0>; | |
453 | compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; | |
454 | reg = <0x63fc8000 0x4000>; | |
455 | interrupts = <62>; | |
6650d6db | 456 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
64972acd GU |
457 | status = "disabled"; |
458 | }; | |
459 | ||
460 | ssi1: ssi@63fcc000 { | |
6ff7f51e | 461 | #sound-dai-cells = <0>; |
28f93d0b MP |
462 | compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", |
463 | "fsl,imx21-ssi"; | |
64972acd GU |
464 | reg = <0x63fcc000 0x4000>; |
465 | interrupts = <29>; | |
6650d6db | 466 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
d9a9f38f MP |
467 | dmas = <&sdma 28 0 0>, |
468 | <&sdma 29 0 0>; | |
469 | dma-names = "rx", "tx"; | |
64972acd | 470 | fsl,fifo-depth = <15>; |
64972acd GU |
471 | status = "disabled"; |
472 | }; | |
473 | ||
474 | audmux: audmux@63fd0000 { | |
475 | compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; | |
476 | reg = <0x63fd0000 0x4000>; | |
477 | status = "disabled"; | |
478 | }; | |
479 | ||
480 | fec: ethernet@63fec000 { | |
481 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; | |
482 | reg = <0x63fec000 0x4000>; | |
483 | interrupts = <87>; | |
6650d6db LS |
484 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
485 | <&clks IMX5_CLK_FEC_GATE>, | |
486 | <&clks IMX5_CLK_FEC_GATE>; | |
64972acd GU |
487 | clock-names = "ipg", "ahb", "ptp"; |
488 | status = "disabled"; | |
489 | }; | |
490 | }; | |
491 | }; | |
492 | }; |